The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)

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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/include/dt-bindings/pinctrl/samsung.h

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    1 /* SPDX-License-Identifier: GPL-2.0 */
    2 /*
    3  * Samsung's Exynos pinctrl bindings
    4  *
    5  * Copyright (c) 2016 Samsung Electronics Co., Ltd.
    6  *              http://www.samsung.com
    7  * Author: Krzysztof Kozlowski <krzk@kernel.org>
    8  */
    9 
   10 #ifndef __DT_BINDINGS_PINCTRL_SAMSUNG_H__
   11 #define __DT_BINDINGS_PINCTRL_SAMSUNG_H__
   12 
   13 #define EXYNOS_PIN_PULL_NONE            0
   14 #define EXYNOS_PIN_PULL_DOWN            1
   15 #define EXYNOS_PIN_PULL_UP              3
   16 
   17 #define S3C64XX_PIN_PULL_NONE           0
   18 #define S3C64XX_PIN_PULL_DOWN           1
   19 #define S3C64XX_PIN_PULL_UP             2
   20 
   21 /* Pin function in power down mode */
   22 #define EXYNOS_PIN_PDN_OUT0             0
   23 #define EXYNOS_PIN_PDN_OUT1             1
   24 #define EXYNOS_PIN_PDN_INPUT            2
   25 #define EXYNOS_PIN_PDN_PREV             3
   26 
   27 /* Drive strengths for Exynos3250, Exynos4 (all) and Exynos5250 */
   28 #define EXYNOS4_PIN_DRV_LV1             0
   29 #define EXYNOS4_PIN_DRV_LV2             2
   30 #define EXYNOS4_PIN_DRV_LV3             1
   31 #define EXYNOS4_PIN_DRV_LV4             3
   32 
   33 /* Drive strengths for Exynos5260 */
   34 #define EXYNOS5260_PIN_DRV_LV1          0
   35 #define EXYNOS5260_PIN_DRV_LV2          1
   36 #define EXYNOS5260_PIN_DRV_LV4          2
   37 #define EXYNOS5260_PIN_DRV_LV6          3
   38 
   39 /*
   40  * Drive strengths for Exynos5410, Exynos542x, Exynos5800 and Exynos850 (except
   41  * GPIO_HSI block)
   42  */
   43 #define EXYNOS5420_PIN_DRV_LV1          0
   44 #define EXYNOS5420_PIN_DRV_LV2          1
   45 #define EXYNOS5420_PIN_DRV_LV3          2
   46 #define EXYNOS5420_PIN_DRV_LV4          3
   47 
   48 /* Drive strengths for Exynos5433 */
   49 #define EXYNOS5433_PIN_DRV_FAST_SR1     0
   50 #define EXYNOS5433_PIN_DRV_FAST_SR2     1
   51 #define EXYNOS5433_PIN_DRV_FAST_SR3     2
   52 #define EXYNOS5433_PIN_DRV_FAST_SR4     3
   53 #define EXYNOS5433_PIN_DRV_FAST_SR5     4
   54 #define EXYNOS5433_PIN_DRV_FAST_SR6     5
   55 #define EXYNOS5433_PIN_DRV_SLOW_SR1     8
   56 #define EXYNOS5433_PIN_DRV_SLOW_SR2     9
   57 #define EXYNOS5433_PIN_DRV_SLOW_SR3     0xa
   58 #define EXYNOS5433_PIN_DRV_SLOW_SR4     0xb
   59 #define EXYNOS5433_PIN_DRV_SLOW_SR5     0xc
   60 #define EXYNOS5433_PIN_DRV_SLOW_SR6     0xf
   61 
   62 /* Drive strengths for Exynos850 GPIO_HSI block */
   63 #define EXYNOS850_HSI_PIN_DRV_LV1       0       /* 1x   */
   64 #define EXYNOS850_HSI_PIN_DRV_LV1_5     1       /* 1.5x */
   65 #define EXYNOS850_HSI_PIN_DRV_LV2       2       /* 2x   */
   66 #define EXYNOS850_HSI_PIN_DRV_LV2_5     3       /* 2.5x */
   67 #define EXYNOS850_HSI_PIN_DRV_LV3       4       /* 3x   */
   68 #define EXYNOS850_HSI_PIN_DRV_LV4       5       /* 4x   */
   69 
   70 #define EXYNOS_PIN_FUNC_INPUT           0
   71 #define EXYNOS_PIN_FUNC_OUTPUT          1
   72 #define EXYNOS_PIN_FUNC_2               2
   73 #define EXYNOS_PIN_FUNC_3               3
   74 #define EXYNOS_PIN_FUNC_4               4
   75 #define EXYNOS_PIN_FUNC_5               5
   76 #define EXYNOS_PIN_FUNC_6               6
   77 #define EXYNOS_PIN_FUNC_EINT            0xf
   78 #define EXYNOS_PIN_FUNC_F               EXYNOS_PIN_FUNC_EINT
   79 
   80 /* Drive strengths for Exynos7 FSYS1 block */
   81 #define EXYNOS7_FSYS1_PIN_DRV_LV1       0
   82 #define EXYNOS7_FSYS1_PIN_DRV_LV2       4
   83 #define EXYNOS7_FSYS1_PIN_DRV_LV3       2
   84 #define EXYNOS7_FSYS1_PIN_DRV_LV4       6
   85 #define EXYNOS7_FSYS1_PIN_DRV_LV5       1
   86 #define EXYNOS7_FSYS1_PIN_DRV_LV6       5
   87 
   88 #endif /* __DT_BINDINGS_PINCTRL_SAMSUNG_H__ */

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