The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)

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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/include/dt-bindings/reset/imx8mp-reset.h

Version: -  FREEBSD  -  FREEBSD-13-STABLE  -  FREEBSD-13-0  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  l41  -  OPENBSD  -  linux-2.6  -  MK84  -  PLAN9  -  xnu-8792 
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    1 /* SPDX-License-Identifier: GPL-2.0-only */
    2 /*
    3  * Copyright 2020 NXP
    4  */
    5 
    6 #ifndef DT_BINDING_RESET_IMX8MP_H
    7 #define DT_BINDING_RESET_IMX8MP_H
    8 
    9 #define IMX8MP_RESET_A53_CORE_POR_RESET0        0
   10 #define IMX8MP_RESET_A53_CORE_POR_RESET1        1
   11 #define IMX8MP_RESET_A53_CORE_POR_RESET2        2
   12 #define IMX8MP_RESET_A53_CORE_POR_RESET3        3
   13 #define IMX8MP_RESET_A53_CORE_RESET0            4
   14 #define IMX8MP_RESET_A53_CORE_RESET1            5
   15 #define IMX8MP_RESET_A53_CORE_RESET2            6
   16 #define IMX8MP_RESET_A53_CORE_RESET3            7
   17 #define IMX8MP_RESET_A53_DBG_RESET0             8
   18 #define IMX8MP_RESET_A53_DBG_RESET1             9
   19 #define IMX8MP_RESET_A53_DBG_RESET2             10
   20 #define IMX8MP_RESET_A53_DBG_RESET3             11
   21 #define IMX8MP_RESET_A53_ETM_RESET0             12
   22 #define IMX8MP_RESET_A53_ETM_RESET1             13
   23 #define IMX8MP_RESET_A53_ETM_RESET2             14
   24 #define IMX8MP_RESET_A53_ETM_RESET3             15
   25 #define IMX8MP_RESET_A53_SOC_DBG_RESET          16
   26 #define IMX8MP_RESET_A53_L2RESET                17
   27 #define IMX8MP_RESET_SW_NON_SCLR_M7C_RST        18
   28 #define IMX8MP_RESET_OTG1_PHY_RESET             19
   29 #define IMX8MP_RESET_OTG2_PHY_RESET             20
   30 #define IMX8MP_RESET_SUPERMIX_RESET             21
   31 #define IMX8MP_RESET_AUDIOMIX_RESET             22
   32 #define IMX8MP_RESET_MLMIX_RESET                23
   33 #define IMX8MP_RESET_PCIEPHY                    24
   34 #define IMX8MP_RESET_PCIEPHY_PERST              25
   35 #define IMX8MP_RESET_PCIE_CTRL_APPS_EN          26
   36 #define IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF     27
   37 #define IMX8MP_RESET_HDMI_PHY_APB_RESET         28
   38 #define IMX8MP_RESET_MEDIA_RESET                29
   39 #define IMX8MP_RESET_GPU2D_RESET                30
   40 #define IMX8MP_RESET_GPU3D_RESET                31
   41 #define IMX8MP_RESET_GPU_RESET                  32
   42 #define IMX8MP_RESET_VPU_RESET                  33
   43 #define IMX8MP_RESET_VPU_G1_RESET               34
   44 #define IMX8MP_RESET_VPU_G2_RESET               35
   45 #define IMX8MP_RESET_VPUVC8KE_RESET             36
   46 #define IMX8MP_RESET_NOC_RESET                  37
   47 
   48 #define IMX8MP_RESET_NUM                        38
   49 
   50 #endif

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