The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)

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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/include/dt-bindings/reset/imx8ulp-pcc-reset.h

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    1 /* SPDX-License-Identifier: GPL-2.0-only */
    2 /*
    3  * Copyright 2021 NXP
    4  */
    5 
    6 #ifndef DT_BINDING_PCC_RESET_IMX8ULP_H
    7 #define DT_BINDING_PCC_RESET_IMX8ULP_H
    8 
    9 /* PCC3 */
   10 #define PCC3_WDOG3_SWRST        0
   11 #define PCC3_WDOG4_SWRST        1
   12 #define PCC3_LPIT1_SWRST        2
   13 #define PCC3_TPM4_SWRST         3
   14 #define PCC3_TPM5_SWRST         4
   15 #define PCC3_FLEXIO1_SWRST      5
   16 #define PCC3_I3C2_SWRST         6
   17 #define PCC3_LPI2C4_SWRST       7
   18 #define PCC3_LPI2C5_SWRST       8
   19 #define PCC3_LPUART4_SWRST      9
   20 #define PCC3_LPUART5_SWRST      10
   21 #define PCC3_LPSPI4_SWRST       11
   22 #define PCC3_LPSPI5_SWRST       12
   23 
   24 /* PCC4 */
   25 #define PCC4_FLEXSPI2_SWRST     0
   26 #define PCC4_TPM6_SWRST         1
   27 #define PCC4_TPM7_SWRST         2
   28 #define PCC4_LPI2C6_SWRST       3
   29 #define PCC4_LPI2C7_SWRST       4
   30 #define PCC4_LPUART6_SWRST      5
   31 #define PCC4_LPUART7_SWRST      6
   32 #define PCC4_SAI4_SWRST         7
   33 #define PCC4_SAI5_SWRST         8
   34 #define PCC4_USDHC0_SWRST       9
   35 #define PCC4_USDHC1_SWRST       10
   36 #define PCC4_USDHC2_SWRST       11
   37 #define PCC4_USB0_SWRST         12
   38 #define PCC4_USB0_PHY_SWRST     13
   39 #define PCC4_USB1_SWRST         14
   40 #define PCC4_USB1_PHY_SWRST     15
   41 #define PCC4_ENET_SWRST         16
   42 
   43 /* PCC5 */
   44 #define PCC5_TPM8_SWRST         0
   45 #define PCC5_SAI6_SWRST         1
   46 #define PCC5_SAI7_SWRST         2
   47 #define PCC5_SPDIF_SWRST        3
   48 #define PCC5_ISI_SWRST          4
   49 #define PCC5_CSI_REGS_SWRST     5
   50 #define PCC5_CSI_SWRST          6
   51 #define PCC5_DSI_SWRST          7
   52 #define PCC5_WDOG5_SWRST        8
   53 #define PCC5_EPDC_SWRST         9
   54 #define PCC5_PXP_SWRST          10
   55 #define PCC5_GPU2D_SWRST        11
   56 #define PCC5_GPU3D_SWRST        12
   57 #define PCC5_DC_NANO_SWRST      13
   58 
   59 #endif /*DT_BINDING_RESET_IMX8ULP_H */

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