The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arc/haps_hs.dts

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    1 // SPDX-License-Identifier: GPL-2.0-only
    2 /*
    3  * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com)
    4  */
    5 /dts-v1/;
    6 
    7 /include/ "skeleton_hs.dtsi"
    8 
    9 / {
   10         model = "snps,zebu_hs";
   11         compatible = "snps,zebu_hs";
   12         #address-cells = <2>;
   13         #size-cells = <2>;
   14         interrupt-parent = <&core_intc>;
   15 
   16         memory {
   17                 device_type = "memory";
   18                 /* CONFIG_LINUX_RAM_BASE needs to match low mem start */
   19                 reg = <0x0 0x80000000 0x0 0x40000000    /* 1 GB low mem */
   20                        0x1 0x00000000 0x0 0x40000000>;  /* 1 GB highmem */
   21         };
   22 
   23         chosen {
   24                 bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
   25         };
   26 
   27         aliases {
   28                 serial0 = &uart0;
   29         };
   30 
   31         fpga {
   32                 compatible = "simple-bus";
   33                 #address-cells = <1>;
   34                 #size-cells = <1>;
   35 
   36                 /* only perip space at end of low mem accessible
   37                           bus addr,  parent bus addr, size    */
   38                 ranges = <0x80000000 0x0 0x80000000 0x80000000>;
   39 
   40                 core_clk: core_clk {
   41                         #clock-cells = <0>;
   42                         compatible = "fixed-clock";
   43                         clock-frequency = <50000000>;
   44                 };
   45 
   46                 core_intc: interrupt-controller {
   47                         compatible = "snps,archs-intc";
   48                         interrupt-controller;
   49                         #interrupt-cells = <1>;
   50                 };
   51 
   52                 uart0: serial@f0000000 {
   53                         compatible = "ns16550a";
   54                         reg = <0xf0000000 0x2000>;
   55                         interrupts = <24>;
   56                         clock-frequency = <50000000>;
   57                         baud = <115200>;
   58                         reg-shift = <2>;
   59                         reg-io-width = <4>;
   60                         no-loopback-test = <1>;
   61                 };
   62 
   63                 arcpct0: pct {
   64                         compatible = "snps,archs-pct";
   65                         #interrupt-cells = <1>;
   66                         interrupts = <20>;
   67                 };
   68 
   69                 virtio0: virtio@f0100000 {
   70                         compatible = "virtio,mmio";
   71                         reg = <0xf0100000 0x2000>;
   72                         interrupts = <31>;
   73                 };
   74 
   75                 virtio1: virtio@f0102000 {
   76                         compatible = "virtio,mmio";
   77                         reg = <0xf0102000 0x2000>;
   78                         interrupts = <32>;
   79                 };
   80 
   81                 virtio2: virtio@f0104000 {
   82                         compatible = "virtio,mmio";
   83                         reg = <0xf0104000 0x2000>;
   84                         interrupts = <33>;
   85                 };
   86 
   87                 virtio3: virtio@f0106000 {
   88                         compatible = "virtio,mmio";
   89                         reg = <0xf0106000 0x2000>;
   90                         interrupts = <34>;
   91                 };
   92 
   93                 virtio4: virtio@f0108000 {
   94                         compatible = "virtio,mmio";
   95                         reg = <0xf0108000 0x2000>;
   96                         interrupts = <35>;
   97                 };
   98         };
   99 };

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