Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arc/hsdk.dts
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1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com) 4 */ 5 6 /* 7 * Device Tree for ARC HS Development Kit 8 */ 9 /dts-v1/; 10 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/reset/snps,hsdk-reset.h> 13 14 / { 15 model = "snps,hsdk"; 16 compatible = "snps,hsdk"; 17 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 chosen { 22 bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1"; 23 }; 24 25 aliases { 26 ethernet = &gmac; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu@0 { 34 device_type = "cpu"; 35 compatible = "snps,archs38"; 36 reg = <0>; 37 clocks = <&core_clk>; 38 }; 39 40 cpu@1 { 41 device_type = "cpu"; 42 compatible = "snps,archs38"; 43 reg = <1>; 44 clocks = <&core_clk>; 45 }; 46 47 cpu@2 { 48 device_type = "cpu"; 49 compatible = "snps,archs38"; 50 reg = <2>; 51 clocks = <&core_clk>; 52 }; 53 54 cpu@3 { 55 device_type = "cpu"; 56 compatible = "snps,archs38"; 57 reg = <3>; 58 clocks = <&core_clk>; 59 }; 60 }; 61 62 input_clk: input-clk { 63 #clock-cells = <0>; 64 compatible = "fixed-clock"; 65 clock-frequency = <33333333>; 66 }; 67 68 reg_5v0: regulator-5v0 { 69 compatible = "regulator-fixed"; 70 71 regulator-name = "5v0-supply"; 72 regulator-min-microvolt = <5000000>; 73 regulator-max-microvolt = <5000000>; 74 }; 75 76 cpu_intc: cpu-interrupt-controller { 77 compatible = "snps,archs-intc"; 78 interrupt-controller; 79 #interrupt-cells = <1>; 80 }; 81 82 idu_intc: idu-interrupt-controller { 83 compatible = "snps,archs-idu-intc"; 84 interrupt-controller; 85 #interrupt-cells = <1>; 86 interrupt-parent = <&cpu_intc>; 87 }; 88 89 arcpct: pct { 90 compatible = "snps,archs-pct"; 91 interrupt-parent = <&cpu_intc>; 92 interrupts = <20>; 93 }; 94 95 /* TIMER0 with interrupt for clockevent */ 96 timer { 97 compatible = "snps,arc-timer"; 98 interrupts = <16>; 99 interrupt-parent = <&cpu_intc>; 100 clocks = <&core_clk>; 101 }; 102 103 /* 64-bit Global Free Running Counter */ 104 gfrc { 105 compatible = "snps,archs-timer-gfrc"; 106 clocks = <&core_clk>; 107 }; 108 109 soc { 110 compatible = "simple-bus"; 111 #address-cells = <1>; 112 #size-cells = <1>; 113 interrupt-parent = <&idu_intc>; 114 115 ranges = <0x00000000 0x0 0xf0000000 0x10000000>; 116 117 cgu_rst: reset-controller@8a0 { 118 compatible = "snps,hsdk-reset"; 119 #reset-cells = <1>; 120 reg = <0x8a0 0x4>, <0xff0 0x4>; 121 }; 122 123 core_clk: core-clk@0 { 124 compatible = "snps,hsdk-core-pll-clock"; 125 reg = <0x00 0x10>, <0x14b8 0x4>; 126 #clock-cells = <0>; 127 clocks = <&input_clk>; 128 129 /* 130 * Set initial core pll output frequency to 1GHz. 131 * It will be applied at the core pll driver probing 132 * on early boot. 133 */ 134 assigned-clocks = <&core_clk>; 135 assigned-clock-rates = <1000000000>; 136 }; 137 138 serial: serial@5000 { 139 compatible = "snps,dw-apb-uart"; 140 reg = <0x5000 0x100>; 141 clock-frequency = <33330000>; 142 interrupts = <6>; 143 baud = <115200>; 144 reg-shift = <2>; 145 reg-io-width = <4>; 146 }; 147 148 gmacclk: gmacclk { 149 compatible = "fixed-clock"; 150 clock-frequency = <400000000>; 151 #clock-cells = <0>; 152 }; 153 154 mmcclk_ciu: mmcclk-ciu { 155 compatible = "fixed-clock"; 156 /* 157 * DW sdio controller has external ciu clock divider 158 * controlled via register in SDIO IP. Due to its 159 * unexpected default value (it should divide by 1 160 * but it divides by 8) SDIO IP uses wrong clock and 161 * works unstable (see STAR 9001204800) 162 * We switched to the minimum possible value of the 163 * divisor (div-by-2) in HSDK platform code. 164 * So add temporary fix and change clock frequency 165 * to 50000000 Hz until we fix dw sdio driver itself. 166 */ 167 clock-frequency = <50000000>; 168 #clock-cells = <0>; 169 }; 170 171 mmcclk_biu: mmcclk-biu { 172 compatible = "fixed-clock"; 173 clock-frequency = <400000000>; 174 #clock-cells = <0>; 175 }; 176 177 gpu_core_clk: gpu-core-clk { 178 compatible = "fixed-clock"; 179 clock-frequency = <400000000>; 180 #clock-cells = <0>; 181 }; 182 183 gpu_dma_clk: gpu-dma-clk { 184 compatible = "fixed-clock"; 185 clock-frequency = <400000000>; 186 #clock-cells = <0>; 187 }; 188 189 gpu_cfg_clk: gpu-cfg-clk { 190 compatible = "fixed-clock"; 191 clock-frequency = <200000000>; 192 #clock-cells = <0>; 193 }; 194 195 dmac_core_clk: dmac-core-clk { 196 compatible = "fixed-clock"; 197 clock-frequency = <400000000>; 198 #clock-cells = <0>; 199 }; 200 201 dmac_cfg_clk: dmac-gpu-cfg-clk { 202 compatible = "fixed-clock"; 203 clock-frequency = <200000000>; 204 #clock-cells = <0>; 205 }; 206 207 gmac: ethernet@8000 { 208 #interrupt-cells = <1>; 209 compatible = "snps,dwmac"; 210 reg = <0x8000 0x2000>; 211 interrupts = <10>; 212 interrupt-names = "macirq"; 213 phy-mode = "rgmii-id"; 214 snps,pbl = <32>; 215 snps,multicast-filter-bins = <256>; 216 clocks = <&gmacclk>; 217 clock-names = "stmmaceth"; 218 phy-handle = <&phy0>; 219 resets = <&cgu_rst HSDK_ETH_RESET>; 220 reset-names = "stmmaceth"; 221 mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */ 222 dma-coherent; 223 224 tx-fifo-depth = <4096>; 225 rx-fifo-depth = <4096>; 226 227 mdio { 228 #address-cells = <1>; 229 #size-cells = <0>; 230 compatible = "snps,dwmac-mdio"; 231 phy0: ethernet-phy@0 { /* Micrel KSZ9031 */ 232 reg = <0>; 233 }; 234 }; 235 }; 236 237 ohci@60000 { 238 compatible = "snps,hsdk-v1.0-ohci", "generic-ohci"; 239 reg = <0x60000 0x100>; 240 interrupts = <15>; 241 resets = <&cgu_rst HSDK_USB_RESET>; 242 dma-coherent; 243 }; 244 245 ehci@40000 { 246 compatible = "snps,hsdk-v1.0-ehci", "generic-ehci"; 247 reg = <0x40000 0x100>; 248 interrupts = <15>; 249 resets = <&cgu_rst HSDK_USB_RESET>; 250 dma-coherent; 251 }; 252 253 mmc@a000 { 254 compatible = "altr,socfpga-dw-mshc"; 255 reg = <0xa000 0x400>; 256 num-slots = <1>; 257 fifo-depth = <16>; 258 card-detect-delay = <200>; 259 clocks = <&mmcclk_biu>, <&mmcclk_ciu>; 260 clock-names = "biu", "ciu"; 261 interrupts = <12>; 262 bus-width = <4>; 263 dma-coherent; 264 }; 265 266 spi0: spi@20000 { 267 compatible = "snps,dw-apb-ssi"; 268 reg = <0x20000 0x100>; 269 #address-cells = <1>; 270 #size-cells = <0>; 271 interrupts = <16>; 272 num-cs = <2>; 273 reg-io-width = <4>; 274 clocks = <&input_clk>; 275 cs-gpios = <&creg_gpio 0 GPIO_ACTIVE_LOW>, 276 <&creg_gpio 1 GPIO_ACTIVE_LOW>; 277 278 flash@0 { 279 compatible = "sst26wf016b", "jedec,spi-nor"; 280 reg = <0>; 281 #address-cells = <1>; 282 #size-cells = <1>; 283 spi-max-frequency = <4000000>; 284 }; 285 286 adc@1 { 287 compatible = "ti,adc108s102"; 288 reg = <1>; 289 vref-supply = <®_5v0>; 290 spi-max-frequency = <1000000>; 291 }; 292 }; 293 294 creg_gpio: gpio@14b0 { 295 compatible = "snps,creg-gpio-hsdk"; 296 reg = <0x14b0 0x4>; 297 gpio-controller; 298 #gpio-cells = <2>; 299 ngpios = <2>; 300 }; 301 302 gpio: gpio@3000 { 303 compatible = "snps,dw-apb-gpio"; 304 reg = <0x3000 0x20>; 305 #address-cells = <1>; 306 #size-cells = <0>; 307 308 gpio_port_a: gpio-controller@0 { 309 compatible = "snps,dw-apb-gpio-port"; 310 gpio-controller; 311 #gpio-cells = <2>; 312 snps,nr-gpios = <24>; 313 reg = <0>; 314 }; 315 }; 316 317 gpu_3d: gpu@90000 { 318 compatible = "vivante,gc"; 319 reg = <0x90000 0x4000>; 320 clocks = <&gpu_dma_clk>, 321 <&gpu_cfg_clk>, 322 <&gpu_core_clk>, 323 <&gpu_core_clk>; 324 clock-names = "bus", "reg", "core", "shader"; 325 interrupts = <28>; 326 }; 327 328 dmac: dmac@80000 { 329 compatible = "snps,axi-dma-1.01a"; 330 reg = <0x80000 0x400>; 331 interrupts = <27>; 332 clocks = <&dmac_core_clk>, <&dmac_cfg_clk>; 333 clock-names = "core-clk", "cfgr-clk"; 334 335 dma-channels = <4>; 336 snps,dma-masters = <2>; 337 snps,data-width = <3>; 338 snps,block-size = <4096 4096 4096 4096>; 339 snps,priority = <0 1 2 3>; 340 snps,axi-max-burst-len = <16>; 341 }; 342 }; 343 344 memory@80000000 { 345 #address-cells = <2>; 346 #size-cells = <2>; 347 device_type = "memory"; 348 reg = <0x0 0x80000000 0x0 0x40000000>; /* 1 GB lowmem */ 349 /* 0x1 0x00000000 0x0 0x40000000>; 1 GB highmem */ 350 }; 351 };
Cache object: 6b1a1b6f0f1241530676fb898368141b
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