am4372.dtsi

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    1 // SPDX-License-Identifier: GPL-2.0-only
    2 /*
    3  * Device Tree Source for AM4372 SoC
    4  *
    5  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
    6  */
    7 
    8 #include <dt-bindings/bus/ti-sysc.h>
    9 #include <dt-bindings/gpio/gpio.h>
   10 #include <dt-bindings/interrupt-controller/arm-gic.h>
   11 #include <dt-bindings/clock/am4.h>
   12 
   13 / {
   14         compatible = "ti,am4372", "ti,am43";
   15         interrupt-parent = <&wakeupgen>;
   16         #address-cells = <1>;
   17         #size-cells = <1>;
   18         chosen { };
   19 
   20         memory@0 {
   21                 device_type = "memory";
   22                 reg = <0 0>;
   23         };
   24 
   25         aliases {
   26                 i2c0 = &i2c0;
   27                 i2c1 = &i2c1;
   28                 i2c2 = &i2c2;
   29                 serial0 = &uart0;
   30                 serial1 = &uart1;
   31                 serial2 = &uart2;
   32                 serial3 = &uart3;
   33                 serial4 = &uart4;
   34                 serial5 = &uart5;
   35                 ethernet0 = &cpsw_port1;
   36                 ethernet1 = &cpsw_port2;
   37                 spi0 = &qspi;
   38         };
   39 
   40         cpus {
   41                 #address-cells = <1>;
   42                 #size-cells = <0>;
   43                 cpu: cpu@0 {
   44                         compatible = "arm,cortex-a9";
   45                         enable-method = "ti,am4372";
   46                         device_type = "cpu";
   47                         reg = <0>;
   48 
   49                         clocks = <&dpll_mpu_ck>;
   50                         clock-names = "cpu";
   51 
   52                         operating-points-v2 = <&cpu0_opp_table>;
   53 
   54                         clock-latency = <300000>; /* From omap-cpufreq driver */
   55                         cpu-idle-states = <&mpu_gate>;
   56                 };
   57 
   58                 idle-states {
   59                         mpu_gate: mpu_gate {
   60                                 compatible = "arm,idle-state";
   61                                 entry-latency-us = <40>;
   62                                 exit-latency-us = <100>;
   63                                 min-residency-us = <300>;
   64                                 local-timer-stop;
   65                         };
   66                 };
   67         };
   68 
   69         cpu0_opp_table: opp-table {
   70                 compatible = "operating-points-v2-ti-cpu";
   71                 syscon = <&scm_conf>;
   72 
   73                 opp50-300000000 {
   74                         opp-hz = /bits/ 64 <300000000>;
   75                         opp-microvolt = <950000 931000 969000>;
   76                         opp-supported-hw = <0xFF 0x01>;
   77                         opp-suspend;
   78                 };
   79 
   80                 opp100-600000000 {
   81                         opp-hz = /bits/ 64 <600000000>;
   82                         opp-microvolt = <1100000 1078000 1122000>;
   83                         opp-supported-hw = <0xFF 0x04>;
   84                 };
   85 
   86                 opp120-720000000 {
   87                         opp-hz = /bits/ 64 <720000000>;
   88                         opp-microvolt = <1200000 1176000 1224000>;
   89                         opp-supported-hw = <0xFF 0x08>;
   90                 };
   91 
   92                 oppturbo-800000000 {
   93                         opp-hz = /bits/ 64 <800000000>;
   94                         opp-microvolt = <1260000 1234800 1285200>;
   95                         opp-supported-hw = <0xFF 0x10>;
   96                 };
   97 
   98                 oppnitro-1000000000 {
   99                         opp-hz = /bits/ 64 <1000000000>;
  100                         opp-microvolt = <1325000 1298500 1351500>;
  101                         opp-supported-hw = <0xFF 0x20>;
  102                 };
  103         };
  104 
  105         soc {
  106                 compatible = "ti,omap-infra";
  107         };
  108 
  109         gic: interrupt-controller@48241000 {
  110                 compatible = "arm,cortex-a9-gic";
  111                 interrupt-controller;
  112                 #interrupt-cells = <3>;
  113                 reg = <0x48241000 0x1000>,
  114                       <0x48240100 0x0100>;
  115                 interrupt-parent = <&gic>;
  116         };
  117 
  118         wakeupgen: interrupt-controller@48281000 {
  119                 compatible = "ti,omap4-wugen-mpu";
  120                 interrupt-controller;
  121                 #interrupt-cells = <3>;
  122                 reg = <0x48281000 0x1000>;
  123                 interrupt-parent = <&gic>;
  124         };
  125 
  126         scu: scu@48240000 {
  127                 compatible = "arm,cortex-a9-scu";
  128                 reg = <0x48240000 0x100>;
  129         };
  130 
  131         global_timer: timer@48240200 {
  132                 compatible = "arm,cortex-a9-global-timer";
  133                 reg = <0x48240200 0x100>;
  134                 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
  135                 interrupt-parent = <&gic>;
  136                 clocks = <&mpu_periphclk>;
  137         };
  138 
  139         local_timer: timer@48240600 {
  140                 compatible = "arm,cortex-a9-twd-timer";
  141                 reg = <0x48240600 0x100>;
  142                 interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
  143                 interrupt-parent = <&gic>;
  144                 clocks = <&mpu_periphclk>;
  145         };
  146 
  147         cache-controller@48242000 {
  148                 compatible = "arm,pl310-cache";
  149                 reg = <0x48242000 0x1000>;
  150                 cache-unified;
  151                 cache-level = <2>;
  152         };
  153 
  154         ocp@44000000 {
  155                 compatible = "simple-pm-bus";
  156                 power-domains = <&prm_per>;
  157                 clocks = <&l3_clkctrl AM4_L3_L3_MAIN_CLKCTRL 0>;
  158                 clock-names = "fck";
  159                 #address-cells = <1>;
  160                 #size-cells = <1>;
  161                 ranges;
  162                 ti,no-idle;
  163 
  164                 l3-noc@44000000 {
  165                         compatible = "ti,am4372-l3-noc";
  166                         reg = <0x44000000 0x400000>,
  167                               <0x44800000 0x400000>;
  168                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
  169                                      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
  170                 };
  171 
  172                 l4_wkup: interconnect@44c00000 {
  173                 };
  174                 l4_per: interconnect@48000000 {
  175                 };
  176                 l4_fast: interconnect@4a000000 {
  177                 };
  178 
  179                 target-module@4c000000 {
  180                         compatible = "ti,sysc-omap4-simple", "ti,sysc";
  181                         reg = <0x4c000000 0x4>;
  182                         reg-names = "rev";
  183                         clocks = <&emif_clkctrl AM4_EMIF_EMIF_CLKCTRL 0>;
  184                         clock-names = "fck";
  185                         ti,no-idle;
  186                         #address-cells = <1>;
  187                         #size-cells = <1>;
  188                         ranges = <0x0 0x4c000000 0x1000000>;
  189 
  190                         emif: emif@0 {
  191                                 compatible = "ti,emif-am4372";
  192                                 reg = <0 0x1000000>;
  193                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
  194                                 sram = <&pm_sram_code
  195                                         &pm_sram_data>;
  196                         };
  197                 };
  198 
  199                 target-module@49000000 {
  200                         compatible = "ti,sysc-omap4", "ti,sysc";
  201                         reg = <0x49000000 0x4>;
  202                         reg-names = "rev";
  203                         clocks = <&l3_clkctrl AM4_L3_TPCC_CLKCTRL 0>;
  204                         clock-names = "fck";
  205                         #address-cells = <1>;
  206                         #size-cells = <1>;
  207                         ranges = <0x0 0x49000000 0x10000>;
  208 
  209                         edma: dma@0 {
  210                                 compatible = "ti,edma3-tpcc";
  211                                 reg = <0 0x10000>;
  212                                 reg-names = "edma3_cc";
  213                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
  214                                              <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
  215                                              <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
  216                                 interrupt-names = "edma3_ccint", "edma3_mperr",
  217                                                   "edma3_ccerrint";
  218                                 dma-requests = <64>;
  219                                 #dma-cells = <2>;
  220 
  221                                 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
  222                                            <&edma_tptc2 0>;
  223 
  224                                 ti,edma-memcpy-channels = <58 59>;
  225                         };
  226                 };
  227 
  228                 target-module@49800000 {
  229                         compatible = "ti,sysc-omap4", "ti,sysc";
  230                         reg = <0x49800000 0x4>,
  231                               <0x49800010 0x4>;
  232                         reg-names = "rev", "sysc";
  233                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
  234                         ti,sysc-midle = <SYSC_IDLE_FORCE>;
  235                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  236                                         <SYSC_IDLE_SMART>;
  237                         clocks = <&l3_clkctrl AM4_L3_TPTC0_CLKCTRL 0>;
  238                         clock-names = "fck";
  239                         #address-cells = <1>;
  240                         #size-cells = <1>;
  241                         ranges = <0x0 0x49800000 0x100000>;
  242 
  243                         edma_tptc0: dma@0 {
  244                                 compatible = "ti,edma3-tptc";
  245                                 reg = <0 0x100000>;
  246                                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
  247                                 interrupt-names = "edma3_tcerrint";
  248                         };
  249                 };
  250 
  251                 target-module@49900000 {
  252                         compatible = "ti,sysc-omap4", "ti,sysc";
  253                         reg = <0x49900000 0x4>,
  254                               <0x49900010 0x4>;
  255                         reg-names = "rev", "sysc";
  256                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
  257                         ti,sysc-midle = <SYSC_IDLE_FORCE>;
  258                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  259                                         <SYSC_IDLE_SMART>;
  260                         clocks = <&l3_clkctrl AM4_L3_TPTC1_CLKCTRL 0>;
  261                         clock-names = "fck";
  262                         #address-cells = <1>;
  263                         #size-cells = <1>;
  264                         ranges = <0x0 0x49900000 0x100000>;
  265 
  266                         edma_tptc1: dma@0 {
  267                                 compatible = "ti,edma3-tptc";
  268                                 reg = <0 0x100000>;
  269                                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
  270                                 interrupt-names = "edma3_tcerrint";
  271                         };
  272                 };
  273 
  274                 target-module@49a00000 {
  275                         compatible = "ti,sysc-omap4", "ti,sysc";
  276                         reg = <0x49a00000 0x4>,
  277                               <0x49a00010 0x4>;
  278                         reg-names = "rev", "sysc";
  279                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
  280                         ti,sysc-midle = <SYSC_IDLE_FORCE>;
  281                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  282                                         <SYSC_IDLE_SMART>;
  283                         clocks = <&l3_clkctrl AM4_L3_TPTC2_CLKCTRL 0>;
  284                         clock-names = "fck";
  285                         #address-cells = <1>;
  286                         #size-cells = <1>;
  287                         ranges = <0x0 0x49a00000 0x100000>;
  288 
  289                         edma_tptc2: dma@0 {
  290                                 compatible = "ti,edma3-tptc";
  291                                 reg = <0 0x100000>;
  292                                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
  293                                 interrupt-names = "edma3_tcerrint";
  294                         };
  295                 };
  296 
  297                 target-module@47810000 {
  298                         compatible = "ti,sysc-omap2", "ti,sysc";
  299                         reg = <0x478102fc 0x4>,
  300                               <0x47810110 0x4>,
  301                               <0x47810114 0x4>;
  302                         reg-names = "rev", "sysc", "syss";
  303                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  304                                          SYSC_OMAP2_ENAWAKEUP |
  305                                          SYSC_OMAP2_SOFTRESET |
  306                                          SYSC_OMAP2_AUTOIDLE)>;
  307                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  308                                         <SYSC_IDLE_NO>,
  309                                         <SYSC_IDLE_SMART>;
  310                         ti,syss-mask = <1>;
  311                         clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>;
  312                         clock-names = "fck";
  313                         #address-cells = <1>;
  314                         #size-cells = <1>;
  315                         ranges = <0x0 0x47810000 0x1000>;
  316 
  317                         mmc3: mmc@0 {
  318                                 compatible = "ti,am437-sdhci";
  319                                 ti,needs-special-reset;
  320                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
  321                                 reg = <0x0 0x1000>;
  322                                 status = "disabled";
  323                         };
  324                 };
  325 
  326                 sham_target: target-module@53100000 {
  327                         compatible = "ti,sysc-omap3-sham", "ti,sysc";
  328                         reg = <0x53100100 0x4>,
  329                               <0x53100110 0x4>,
  330                               <0x53100114 0x4>;
  331                         reg-names = "rev", "sysc", "syss";
  332                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
  333                                          SYSC_OMAP2_AUTOIDLE)>;
  334                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  335                                         <SYSC_IDLE_NO>,
  336                                         <SYSC_IDLE_SMART>;
  337                         ti,syss-mask = <1>;
  338                         /* Domains (P, C): per_pwrdm, l3_clkdm */
  339                         clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>;
  340                         clock-names = "fck";
  341                         #address-cells = <1>;
  342                         #size-cells = <1>;
  343                         ranges = <0x0 0x53100000 0x1000>;
  344 
  345                         sham: sham@0 {
  346                                 compatible = "ti,omap5-sham";
  347                                 reg = <0 0x300>;
  348                                 dmas = <&edma 36 0>;
  349                                 dma-names = "rx";
  350                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
  351                         };
  352                 };
  353 
  354                 aes_target: target-module@53501000 {
  355                         compatible = "ti,sysc-omap2", "ti,sysc";
  356                         reg = <0x53501080 0x4>,
  357                               <0x53501084 0x4>,
  358                               <0x53501088 0x4>;
  359                         reg-names = "rev", "sysc", "syss";
  360                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
  361                                          SYSC_OMAP2_AUTOIDLE)>;
  362                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  363                                         <SYSC_IDLE_NO>,
  364                                         <SYSC_IDLE_SMART>,
  365                                         <SYSC_IDLE_SMART_WKUP>;
  366                         ti,syss-mask = <1>;
  367                         /* Domains (P, C): per_pwrdm, l3_clkdm */
  368                         clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>;
  369                         clock-names = "fck";
  370                         #address-cells = <1>;
  371                         #size-cells = <1>;
  372                         ranges = <0x0 0x53501000 0x1000>;
  373 
  374                         aes: aes@0 {
  375                                 compatible = "ti,omap4-aes";
  376                                 reg = <0 0xa0>;
  377                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
  378                                 dmas = <&edma 6 0>,
  379                                       <&edma 5 0>;
  380                                 dma-names = "tx", "rx";
  381                         };
  382                 };
  383 
  384                 des_target: target-module@53701000 {
  385                         compatible = "ti,sysc-omap2", "ti,sysc";
  386                         reg = <0x53701030 0x4>,
  387                               <0x53701034 0x4>,
  388                               <0x53701038 0x4>;
  389                         reg-names = "rev", "sysc", "syss";
  390                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
  391                                          SYSC_OMAP2_AUTOIDLE)>;
  392                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  393                                         <SYSC_IDLE_NO>,
  394                                         <SYSC_IDLE_SMART>,
  395                                         <SYSC_IDLE_SMART_WKUP>;
  396                         ti,syss-mask = <1>;
  397                         /* Domains (P, C): per_pwrdm, l3_clkdm */
  398                         clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>;
  399                         clock-names = "fck";
  400                         #address-cells = <1>;
  401                         #size-cells = <1>;
  402                         ranges = <0 0x53701000 0x1000>;
  403 
  404                         des: des@0 {
  405                                 compatible = "ti,omap4-des";
  406                                 reg = <0 0xa0>;
  407                                 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
  408                                 dmas = <&edma 34 0>,
  409                                        <&edma 33 0>;
  410                                 dma-names = "tx", "rx";
  411                         };
  412                 };
  413 
  414                 pruss_tm: target-module@54400000 {
  415                         compatible = "ti,sysc-pruss", "ti,sysc";
  416                         reg = <0x54426000 0x4>,
  417                               <0x54426004 0x4>;
  418                         reg-names = "rev", "sysc";
  419                         ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
  420                                          SYSC_PRUSS_SUB_MWAIT)>;
  421                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
  422                                         <SYSC_IDLE_NO>,
  423                                         <SYSC_IDLE_SMART>;
  424                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  425                                         <SYSC_IDLE_NO>,
  426                                         <SYSC_IDLE_SMART>;
  427                         clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>;
  428                         clock-names = "fck";
  429                         resets = <&prm_per 1>;
  430                         reset-names = "rstctrl";
  431                         #address-cells = <1>;
  432                         #size-cells = <1>;
  433                         ranges = <0x0 0x54400000 0x80000>;
  434 
  435                         pruss1: pruss@0 {
  436                                 compatible = "ti,am4376-pruss1";
  437                                 reg = <0x0 0x40000>;
  438                                 #address-cells = <1>;
  439                                 #size-cells = <1>;
  440                                 ranges;
  441 
  442                                 pruss1_mem: memories@0 {
  443                                         reg = <0x0 0x2000>,
  444                                               <0x2000 0x2000>,
  445                                               <0x10000 0x8000>;
  446                                         reg-names = "dram0", "dram1",
  447                                                     "shrdram2";
  448                                 };
  449 
  450                                 pruss1_cfg: cfg@26000 {
  451                                         compatible = "ti,pruss-cfg", "syscon";
  452                                         reg = <0x26000 0x2000>;
  453                                         #address-cells = <1>;
  454                                         #size-cells = <1>;
  455                                         ranges = <0x0 0x26000 0x2000>;
  456 
  457                                         clocks {
  458                                                 #address-cells = <1>;
  459                                                 #size-cells = <0>;
  460 
  461                                                 pruss1_iepclk_mux: iepclk-mux@30 {
  462                                                         reg = <0x30>;
  463                                                         #clock-cells = <0>;
  464                                                         clocks = <&sysclk_div>,     /* icss_iep_gclk */
  465                                                                  <&pruss_ocp_gclk>; /* icss_ocp_gclk */
  466                                                 };
  467                                         };
  468                                 };
  469 
  470                                 pruss1_mii_rt: mii-rt@32000 {
  471                                         compatible = "ti,pruss-mii", "syscon";
  472                                         reg = <0x32000 0x58>;
  473                                 };
  474 
  475                                 pruss1_intc: interrupt-controller@20000 {
  476                                         compatible = "ti,pruss-intc";
  477                                         reg = <0x20000 0x2000>;
  478                                         interrupt-controller;
  479                                         #interrupt-cells = <3>;
  480                                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
  481                                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
  482                                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
  483                                                      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
  484                                                      <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
  485                                                      <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
  486                                                      <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
  487                                         interrupt-names = "host_intr0", "host_intr1",
  488                                                           "host_intr2", "host_intr3",
  489                                                           "host_intr4",
  490                                                           "host_intr6", "host_intr7";
  491                                         ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
  492                                 };
  493 
  494                                 pru1_0: pru@34000 {
  495                                         compatible = "ti,am4376-pru";
  496                                         reg = <0x34000 0x3000>,
  497                                               <0x22000 0x400>,
  498                                               <0x22400 0x100>;
  499                                         reg-names = "iram", "control", "debug";
  500                                         firmware-name = "am437x-pru1_0-fw";
  501                                 };
  502 
  503                                 pru1_1: pru@38000 {
  504                                         compatible = "ti,am4376-pru";
  505                                         reg = <0x38000 0x3000>,
  506                                               <0x24000 0x400>,
  507                                               <0x24400 0x100>;
  508                                         reg-names = "iram", "control", "debug";
  509                                         firmware-name = "am437x-pru1_1-fw";
  510                                 };
  511 
  512                                 pruss1_mdio: mdio@32400 {
  513                                         compatible = "ti,davinci_mdio";
  514                                         reg = <0x32400 0x90>;
  515                                         clocks = <&dpll_core_m4_ck>;
  516                                         clock-names = "fck";
  517                                         bus_freq = <1000000>;
  518                                         #address-cells = <1>;
  519                                         #size-cells = <0>;
  520                                 };
  521                         };
  522 
  523                         pruss0: pruss@40000 {
  524                                 compatible = "ti,am4376-pruss0";
  525                                 reg = <0x40000 0x40000>;
  526                                 #address-cells = <1>;
  527                                 #size-cells = <1>;
  528                                 ranges;
  529 
  530                                 pruss0_mem: memories@40000 {
  531                                         reg = <0x40000 0x1000>,
  532                                               <0x42000 0x1000>;
  533                                         reg-names = "dram0", "dram1";
  534                                 };
  535 
  536                                 pruss0_cfg: cfg@66000 {
  537                                         compatible = "ti,pruss-cfg", "syscon";
  538                                         reg = <0x66000 0x2000>;
  539                                         #address-cells = <1>;
  540                                         #size-cells = <1>;
  541                                         ranges = <0x0 0x66000 0x2000>;
  542 
  543                                         clocks {
  544                                                 #address-cells = <1>;
  545                                                 #size-cells = <0>;
  546 
  547                                                 pruss0_iepclk_mux: iepclk-mux@30 {
  548                                                         reg = <0x30>;
  549                                                         #clock-cells = <0>;
  550                                                         clocks = <&sysclk_div>,     /* icss_iep_gclk */
  551                                                                  <&pruss_ocp_gclk>; /* icss_ocp_gclk */
  552                                                 };
  553                                         };
  554                                 };
  555 
  556                                 pruss0_mii_rt: mii-rt@72000 {
  557                                         compatible = "ti,pruss-mii", "syscon";
  558                                         reg = <0x72000 0x58>;
  559                                         status = "disabled";
  560                                 };
  561 
  562                                 pruss0_intc: interrupt-controller@60000 {
  563                                         compatible = "ti,pruss-intc";
  564                                         reg = <0x60000 0x2000>;
  565                                         interrupt-controller;
  566                                         #interrupt-cells = <3>;
  567                                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
  568                                                      <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
  569                                                      <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
  570                                                      <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
  571                                                      <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
  572                                                      <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
  573                                                      <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
  574                                         interrupt-names = "host_intr0", "host_intr1",
  575                                                           "host_intr2", "host_intr3",
  576                                                           "host_intr4",
  577                                                           "host_intr6", "host_intr7";
  578                                         ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
  579                                 };
  580 
  581                                 pru0_0: pru@74000 {
  582                                         compatible = "ti,am4376-pru";
  583                                         reg = <0x74000 0x1000>,
  584                                               <0x62000 0x400>,
  585                                               <0x62400 0x100>;
  586                                         reg-names = "iram", "control", "debug";
  587                                         firmware-name = "am437x-pru0_0-fw";
  588                                 };
  589 
  590                                 pru0_1: pru@78000 {
  591                                         compatible = "ti,am4376-pru";
  592                                         reg = <0x78000 0x1000>,
  593                                               <0x64000 0x400>,
  594                                               <0x64400 0x100>;
  595                                         reg-names = "iram", "control", "debug";
  596                                         firmware-name = "am437x-pru0_1-fw";
  597                                 };
  598                         };
  599                 };
  600 
  601                 target-module@50000000 {
  602                         compatible = "ti,sysc-omap2", "ti,sysc";
  603                         reg = <0x50000000 4>,
  604                               <0x50000010 4>,
  605                               <0x50000014 4>;
  606                         reg-names = "rev", "sysc", "syss";
  607                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  608                                         <SYSC_IDLE_NO>,
  609                                         <SYSC_IDLE_SMART>;
  610                         ti,syss-mask = <1>;
  611                         clocks = <&l3s_clkctrl AM4_L3S_GPMC_CLKCTRL 0>;
  612                         clock-names = "fck";
  613                         #address-cells = <1>;
  614                         #size-cells = <1>;
  615                         ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
  616                                  <0x00000000 0x00000000 0x40000000>; /* data */
  617 
  618                         gpmc: gpmc@50000000 {
  619                                 compatible = "ti,am3352-gpmc";
  620                                 dmas = <&edma 52 0>;
  621                                 dma-names = "rxtx";
  622                                 clocks = <&l3s_gclk>;
  623                                 clock-names = "fck";
  624                                 reg = <0x50000000 0x2000>;
  625                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
  626                                 gpmc,num-cs = <7>;
  627                                 gpmc,num-waitpins = <2>;
  628                                 #address-cells = <2>;
  629                                 #size-cells = <1>;
  630                                 interrupt-controller;
  631                                 #interrupt-cells = <2>;
  632                                 gpio-controller;
  633                                 #gpio-cells = <2>;
  634                                 status = "disabled";
  635                         };
  636                 };
  637 
  638                 target-module@47900000 {
  639                         compatible = "ti,sysc-omap4", "ti,sysc";
  640                         reg = <0x47900000 0x4>,
  641                               <0x47900010 0x4>;
  642                         reg-names = "rev", "sysc";
  643                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  644                                         <SYSC_IDLE_NO>,
  645                                         <SYSC_IDLE_SMART>,
  646                                         <SYSC_IDLE_SMART_WKUP>;
  647                         clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>;
  648                         clock-names = "fck";
  649                         #address-cells = <1>;
  650                         #size-cells = <1>;
  651                         ranges = <0x0 0x47900000 0x1000>,
  652                                  <0x30000000 0x30000000 0x4000000>;
  653 
  654                         qspi: spi@0 {
  655                                 compatible = "ti,am4372-qspi";
  656                                 reg = <0 0x100>,
  657                                       <0x30000000 0x4000000>;
  658                                 reg-names = "qspi_base", "qspi_mmap";
  659                                 clocks = <&dpll_per_m2_div4_ck>;
  660                                 clock-names = "fck";
  661                                 #address-cells = <1>;
  662                                 #size-cells = <0>;
  663                                 interrupts = <0 138 0x4>;
  664                                 num-cs = <4>;
  665                         };
  666                 };
  667 
  668                 target-module@40300000 {
  669                         compatible = "ti,sysc-omap4-simple", "ti,sysc";
  670                         clocks = <&l3_clkctrl AM4_L3_OCMCRAM_CLKCTRL 0>;
  671                         clock-names = "fck";
  672                         ti,no-idle;
  673                         #address-cells = <1>;
  674                         #size-cells = <1>;
  675                         ranges = <0 0x40300000 0x40000>;
  676 
  677                         ocmcram: sram@0 {
  678                                 compatible = "mmio-sram";
  679                                 reg = <0 0x40000>; /* 256k */
  680                                 ranges = <0 0 0x40000>;
  681                                 #address-cells = <1>;
  682                                 #size-cells = <1>;
  683 
  684                                 pm_sram_code: pm-code-sram@0 {
  685                                         compatible = "ti,sram";
  686                                         reg = <0x0 0x1000>;
  687                                         protect-exec;
  688                                 };
  689 
  690                                 pm_sram_data: pm-data-sram@1000 {
  691                                         compatible = "ti,sram";
  692                                         reg = <0x1000 0x1000>;
  693                                         pool;
  694                                 };
  695                         };
  696                 };
  697 
  698                 target-module@56000000 {
  699                         compatible = "ti,sysc-omap4", "ti,sysc";
  700                         reg = <0x5600fe00 0x4>,
  701                               <0x5600fe10 0x4>;
  702                         reg-names = "rev", "sysc";
  703                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
  704                                         <SYSC_IDLE_NO>,
  705                                         <SYSC_IDLE_SMART>;
  706                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  707                                         <SYSC_IDLE_NO>,
  708                                         <SYSC_IDLE_SMART>;
  709                         clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>;
  710                         clock-names = "fck";
  711                         power-domains = <&prm_gfx>;
  712                         resets = <&prm_gfx 0>;
  713                         reset-names = "rstctrl";
  714                         #address-cells = <1>;
  715                         #size-cells = <1>;
  716                         ranges = <0 0x56000000 0x1000000>;
  717                 };
  718         };
  719 };
  720 
  721 #include "am437x-l4.dtsi"
  722 #include "am43xx-clocks.dtsi"
  723 
  724 &prcm {
  725         prm_mpu: prm@300 {
  726                 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
  727                 reg = <0x300 0x100>;
  728                 #power-domain-cells = <0>;
  729         };
  730 
  731         prm_gfx: prm@400 {
  732                 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
  733                 reg = <0x400 0x100>;
  734                 #power-domain-cells = <0>;
  735                 #reset-cells = <1>;
  736         };
  737 
  738         prm_rtc: prm@500 {
  739                 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
  740                 reg = <0x500 0x100>;
  741                 #power-domain-cells = <0>;
  742         };
  743 
  744         prm_tamper: prm@600 {
  745                 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
  746                 reg = <0x600 0x100>;
  747                 #power-domain-cells = <0>;
  748         };
  749 
  750         prm_cefuse: prm@700 {
  751                 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
  752                 reg = <0x700 0x100>;
  753                 #power-domain-cells = <0>;
  754         };
  755 
  756         prm_per: prm@800 {
  757                 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
  758                 reg = <0x800 0x100>;
  759                 #reset-cells = <1>;
  760                 #power-domain-cells = <0>;
  761         };
  762 
  763         prm_wkup: prm@2000 {
  764                 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
  765                 reg = <0x2000 0x100>;
  766                 #reset-cells = <1>;
  767                 #power-domain-cells = <0>;
  768         };
  769 
  770         prm_device: prm@4000 {
  771                 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
  772                 reg = <0x4000 0x100>;
  773                 #reset-cells = <1>;
  774         };
  775 };
  776 
  777 /* Preferred always-on timer for clocksource */
  778 &timer1_target {
  779         ti,no-reset-on-init;
  780         ti,no-idle;
  781         clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>,
  782                  <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>;
  783         clock-names = "fck", "ick";
  784         timer@0 {
  785                 assigned-clocks = <&timer1_fck>;
  786                 assigned-clock-parents = <&sys_clkin_ck>;
  787         };
  788 };
  789 
  790 /* Preferred timer for clockevent */
  791 &timer2_target {
  792         ti,no-reset-on-init;
  793         ti,no-idle;
  794         clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>,
  795                  <&l4ls_clkctrl AM4_L4LS_L4_LS_CLKCTRL 0>;
  796         clock-names = "fck", "ick";
  797         timer@0 {
  798                 assigned-clocks = <&timer2_fck>;
  799                 assigned-clock-parents = <&sys_clkin_ck>;
  800         };
  801 };
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