Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/arm-realview-pbx.dtsi
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1 /* 2 * Copyright 2016 Linaro Ltd 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to deal 6 * in the Software without restriction, including without limitation the rights 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 * copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 * THE SOFTWARE. 21 */ 22 23 #include <dt-bindings/interrupt-controller/irq.h> 24 #include <dt-bindings/gpio/gpio.h> 25 26 / { 27 #address-cells = <1>; 28 #size-cells = <1>; 29 compatible = "arm,realview-pbx"; 30 31 chosen { }; 32 33 aliases { 34 serial0 = &serial0; 35 serial1 = &serial1; 36 serial2 = &serial2; 37 serial3 = &serial3; 38 i2c0 = &i2c0; 39 i2c1 = &i2c1; 40 }; 41 42 memory { 43 device_type = "memory"; 44 /* 128 MiB memory @ 0x0 */ 45 reg = <0x00000000 0x08000000>; 46 }; 47 48 /* The voltage to the MMC card is hardwired at 3.3V */ 49 vmmc: regulator-vmmc { 50 compatible = "regulator-fixed"; 51 regulator-name = "vmmc"; 52 regulator-min-microvolt = <3300000>; 53 regulator-max-microvolt = <3300000>; 54 regulator-boot-on; 55 }; 56 57 veth: regulator-veth { 58 compatible = "regulator-fixed"; 59 regulator-name = "veth"; 60 regulator-min-microvolt = <3300000>; 61 regulator-max-microvolt = <3300000>; 62 regulator-boot-on; 63 }; 64 65 xtal24mhz: xtal24mhz@24M { 66 #clock-cells = <0>; 67 compatible = "fixed-clock"; 68 clock-frequency = <24000000>; 69 }; 70 71 refclk32khz: refclk32khz { 72 #clock-cells = <0>; 73 compatible = "fixed-clock"; 74 clock-frequency = <32768>; 75 }; 76 77 timclk: timclk@1M { 78 #clock-cells = <0>; 79 compatible = "fixed-factor-clock"; 80 clock-div = <24>; 81 clock-mult = <1>; 82 clocks = <&xtal24mhz>; 83 }; 84 85 mclk: mclk@24M { 86 #clock-cells = <0>; 87 compatible = "fixed-factor-clock"; 88 clock-div = <1>; 89 clock-mult = <1>; 90 clocks = <&xtal24mhz>; 91 }; 92 93 kmiclk: kmiclk@24M { 94 #clock-cells = <0>; 95 compatible = "fixed-factor-clock"; 96 clock-div = <1>; 97 clock-mult = <1>; 98 clocks = <&xtal24mhz>; 99 }; 100 101 sspclk: sspclk@24M { 102 #clock-cells = <0>; 103 compatible = "fixed-factor-clock"; 104 clock-div = <1>; 105 clock-mult = <1>; 106 clocks = <&xtal24mhz>; 107 }; 108 109 uartclk: uartclk@24M { 110 #clock-cells = <0>; 111 compatible = "fixed-factor-clock"; 112 clock-div = <1>; 113 clock-mult = <1>; 114 clocks = <&xtal24mhz>; 115 }; 116 117 wdogclk: wdogclk@24M { 118 #clock-cells = <0>; 119 compatible = "fixed-factor-clock"; 120 clock-div = <1>; 121 clock-mult = <1>; 122 clocks = <&xtal24mhz>; 123 }; 124 125 /* FIXME: this actually hangs off the PLL clocks */ 126 pclk: pclk@0 { 127 #clock-cells = <0>; 128 compatible = "fixed-clock"; 129 clock-frequency = <0>; 130 }; 131 132 flash0@40000000 { 133 /* 2 * 32MiB NOR Flash memory */ 134 compatible = "arm,versatile-flash", "cfi-flash"; 135 reg = <0x40000000 0x04000000>; 136 bank-width = <4>; 137 partitions { 138 compatible = "arm,arm-firmware-suite"; 139 }; 140 }; 141 142 flash1@44000000 { 143 /* 2 * 32MiB NOR Flash memory */ 144 compatible = "arm,versatile-flash", "cfi-flash"; 145 reg = <0x44000000 0x04000000>; 146 bank-width = <4>; 147 partitions { 148 compatible = "arm,arm-firmware-suite"; 149 }; 150 }; 151 152 /* SMSC 9118 ethernet with PHY and EEPROM */ 153 ethernet: ethernet@4e000000 { 154 compatible = "smsc,lan9118", "smsc,lan9115"; 155 reg = <0x4e000000 0x10000>; 156 phy-mode = "mii"; 157 reg-io-width = <4>; 158 smsc,irq-active-high; 159 smsc,irq-push-pull; 160 vdd33a-supply = <&veth>; 161 vddvario-supply = <&veth>; 162 }; 163 164 usb: usb@4f000000 { 165 compatible = "nxp,usb-isp1761"; 166 reg = <0x4f000000 0x20000>; 167 dr_mode = "peripheral"; 168 }; 169 170 bridge { 171 compatible = "ti,ths8134a", "ti,ths8134"; 172 #address-cells = <1>; 173 #size-cells = <0>; 174 175 ports { 176 #address-cells = <1>; 177 #size-cells = <0>; 178 179 port@0 { 180 reg = <0>; 181 182 vga_bridge_in: endpoint { 183 remote-endpoint = <&clcd_pads>; 184 }; 185 }; 186 187 port@1 { 188 reg = <1>; 189 190 vga_bridge_out: endpoint { 191 remote-endpoint = <&vga_con_in>; 192 }; 193 }; 194 }; 195 }; 196 197 vga { 198 /* 199 * This DDC I2C is connected directly to the DVI portions 200 * of the connector, so it's not really working when the 201 * monitor is connected to the VGA connector. 202 */ 203 compatible = "vga-connector"; 204 ddc-i2c-bus = <&i2c1>; 205 206 port { 207 vga_con_in: endpoint { 208 remote-endpoint = <&vga_bridge_out>; 209 }; 210 }; 211 }; 212 213 soc: soc { 214 compatible = "arm,realview-pbx-soc", "simple-bus"; 215 #address-cells = <1>; 216 #size-cells = <1>; 217 regmap = <&syscon>; 218 ranges; 219 220 syscon: syscon@10000000 { 221 compatible = "arm,realview-pbx-syscon", "syscon", "simple-mfd"; 222 reg = <0x10000000 0x1000>; 223 ranges = <0x0 0x10000000 0x1000>; 224 #address-cells = <1>; 225 #size-cells = <1>; 226 227 led@8,0 { 228 compatible = "register-bit-led"; 229 reg = <0x08 0x04>; 230 offset = <0x08>; 231 mask = <0x01>; 232 label = "versatile:0"; 233 linux,default-trigger = "heartbeat"; 234 default-state = "on"; 235 }; 236 led@8,1 { 237 compatible = "register-bit-led"; 238 reg = <0x08 0x04>; 239 offset = <0x08>; 240 mask = <0x02>; 241 label = "versatile:1"; 242 linux,default-trigger = "mmc0"; 243 default-state = "off"; 244 }; 245 led@8,2 { 246 compatible = "register-bit-led"; 247 reg = <0x08 0x04>; 248 offset = <0x08>; 249 mask = <0x04>; 250 label = "versatile:2"; 251 linux,default-trigger = "cpu0"; 252 default-state = "off"; 253 }; 254 led@8,3 { 255 compatible = "register-bit-led"; 256 reg = <0x08 0x04>; 257 offset = <0x08>; 258 mask = <0x08>; 259 label = "versatile:3"; 260 default-state = "off"; 261 }; 262 led@8,4 { 263 compatible = "register-bit-led"; 264 reg = <0x08 0x04>; 265 offset = <0x08>; 266 mask = <0x10>; 267 label = "versatile:4"; 268 default-state = "off"; 269 }; 270 led@8,5 { 271 compatible = "register-bit-led"; 272 reg = <0x08 0x04>; 273 offset = <0x08>; 274 mask = <0x20>; 275 label = "versatile:5"; 276 default-state = "off"; 277 }; 278 led@8,6 { 279 compatible = "register-bit-led"; 280 reg = <0x08 0x04>; 281 offset = <0x08>; 282 mask = <0x40>; 283 label = "versatile:6"; 284 default-state = "off"; 285 }; 286 led@8,7 { 287 compatible = "register-bit-led"; 288 reg = <0x08 0x04>; 289 offset = <0x08>; 290 mask = <0x80>; 291 label = "versatile:7"; 292 default-state = "off"; 293 }; 294 oscclk0: clock-controller@c { 295 compatible = "arm,syscon-icst307"; 296 reg = <0x0c 0x04>; 297 #clock-cells = <0>; 298 lock-offset = <0x20>; 299 vco-offset = <0x0C>; 300 clocks = <&xtal24mhz>; 301 }; 302 oscclk1: clock-controller@10 { 303 compatible = "arm,syscon-icst307"; 304 reg = <0x10 0x04>; 305 #clock-cells = <0>; 306 lock-offset = <0x20>; 307 vco-offset = <0x10>; 308 clocks = <&xtal24mhz>; 309 }; 310 oscclk2: clock-controller@14 { 311 compatible = "arm,syscon-icst307"; 312 reg = <0x14 0x04>; 313 #clock-cells = <0>; 314 lock-offset = <0x20>; 315 vco-offset = <0x14>; 316 clocks = <&xtal24mhz>; 317 }; 318 oscclk3: clock-controller@18 { 319 compatible = "arm,syscon-icst307"; 320 reg = <0x18 0x04>; 321 #clock-cells = <0>; 322 lock-offset = <0x20>; 323 vco-offset = <0x18>; 324 clocks = <&xtal24mhz>; 325 }; 326 oscclk4: clock-controller@1c { 327 compatible = "arm,syscon-icst307"; 328 reg = <0x1c 0x04>; 329 #clock-cells = <0>; 330 lock-offset = <0x20>; 331 vco-offset = <0x1c>; 332 clocks = <&xtal24mhz>; 333 }; 334 }; 335 336 sp810_syscon0: sysctl@10001000 { 337 compatible = "arm,sp810", "arm,primecell"; 338 reg = <0x10001000 0x1000>; 339 clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>; 340 clock-names = "refclk", "timclk", "apb_pclk"; 341 #clock-cells = <1>; 342 clock-output-names = "timerclk0", 343 "timerclk1", 344 "timerclk2", 345 "timerclk3"; 346 assigned-clocks = <&sp810_syscon0 0>, 347 <&sp810_syscon0 1>, 348 <&sp810_syscon0 2>, 349 <&sp810_syscon0 3>; 350 assigned-clock-parents = <&timclk>, 351 <&timclk>, 352 <&timclk>, 353 <&timclk>; 354 }; 355 356 i2c0: i2c@10002000 { 357 #address-cells = <1>; 358 #size-cells = <0>; 359 compatible = "arm,versatile-i2c"; 360 reg = <0x10002000 0x1000>; 361 362 rtc@68 { 363 compatible = "dallas,ds1338"; 364 reg = <0x68>; 365 }; 366 }; 367 368 serial0: serial@10009000 { 369 compatible = "arm,pl011", "arm,primecell"; 370 reg = <0x10009000 0x1000>; 371 clocks = <&uartclk>, <&pclk>; 372 clock-names = "uartclk", "apb_pclk"; 373 }; 374 375 serial1: serial@1000a000 { 376 compatible = "arm,pl011", "arm,primecell"; 377 reg = <0x1000a000 0x1000>; 378 clocks = <&uartclk>, <&pclk>; 379 clock-names = "uartclk", "apb_pclk"; 380 }; 381 382 serial2: serial@1000b000 { 383 compatible = "arm,pl011", "arm,primecell"; 384 reg = <0x1000b000 0x1000>; 385 clocks = <&uartclk>, <&pclk>; 386 clock-names = "uartclk", "apb_pclk"; 387 }; 388 389 ssp: spi@1000d000 { 390 compatible = "arm,pl022", "arm,primecell"; 391 reg = <0x1000d000 0x1000>; 392 clocks = <&sspclk>, <&pclk>; 393 clock-names = "sspclk", "apb_pclk"; 394 }; 395 396 wdog0: watchdog@1000f000 { 397 compatible = "arm,sp805", "arm,primecell"; 398 reg = <0x1000f000 0x1000>; 399 clocks = <&wdogclk>, <&pclk>; 400 clock-names = "wdog_clk", "apb_pclk"; 401 status = "disabled"; 402 }; 403 404 wdog1: watchdog@10010000 { 405 compatible = "arm,sp805", "arm,primecell"; 406 reg = <0x10010000 0x1000>; 407 clocks = <&wdogclk>, <&pclk>; 408 clock-names = "wdog_clk", "apb_pclk"; 409 status = "disabled"; 410 }; 411 412 timer01: timer@10011000 { 413 compatible = "arm,sp804", "arm,primecell"; 414 reg = <0x10011000 0x1000>; 415 clocks = <&sp810_syscon0 0>, 416 <&sp810_syscon0 1>, 417 <&pclk>; 418 clock-names = "timerclk0", 419 "timerclk1", 420 "apb_pclk"; 421 }; 422 423 timer23: timer@10012000 { 424 compatible = "arm,sp804", "arm,primecell"; 425 reg = <0x10012000 0x1000>; 426 clocks = <&sp810_syscon0 2>, 427 <&sp810_syscon0 3>, 428 <&pclk>; 429 clock-names = "timerclk2", 430 "timerclk3", 431 "apb_pclk"; 432 }; 433 434 gpio0: gpio@10013000 { 435 compatible = "arm,pl061", "arm,primecell"; 436 reg = <0x10013000 0x1000>; 437 gpio-controller; 438 #gpio-cells = <2>; 439 interrupt-controller; 440 #interrupt-cells = <2>; 441 clocks = <&pclk>; 442 clock-names = "apb_pclk"; 443 }; 444 445 gpio1: gpio@10014000 { 446 compatible = "arm,pl061", "arm,primecell"; 447 reg = <0x10014000 0x1000>; 448 gpio-controller; 449 #gpio-cells = <2>; 450 interrupt-controller; 451 #interrupt-cells = <2>; 452 clocks = <&pclk>; 453 clock-names = "apb_pclk"; 454 }; 455 456 gpio2: gpio@10015000 { 457 compatible = "arm,pl061", "arm,primecell"; 458 reg = <0x10015000 0x1000>; 459 gpio-controller; 460 #gpio-cells = <2>; 461 interrupt-controller; 462 #interrupt-cells = <2>; 463 clocks = <&pclk>; 464 clock-names = "apb_pclk"; 465 }; 466 467 i2c1: i2c@10016000 { 468 #address-cells = <1>; 469 #size-cells = <0>; 470 compatible = "arm,versatile-i2c"; 471 reg = <0x10016000 0x1000>; 472 }; 473 474 rtc: rtc@10017000 { 475 compatible = "arm,pl031", "arm,primecell"; 476 reg = <0x10017000 0x1000>; 477 clocks = <&pclk>; 478 clock-names = "apb_pclk"; 479 }; 480 481 timer45: timer@10018000 { 482 compatible = "arm,sp804", "arm,primecell"; 483 reg = <0x10018000 0x1000>; 484 clocks = <&timclk>, <&timclk>, <&pclk>; 485 clock-names = "timerclk4", "timerclk5", "apb_pclk"; 486 }; 487 488 timer67: timer@10019000 { 489 compatible = "arm,sp804", "arm,primecell"; 490 reg = <0x10019000 0x1000>; 491 clocks = <&timclk>, <&timclk>, <&pclk>; 492 clock-names = "timerclk6", "timerclk7", "apb_pclk"; 493 }; 494 495 sp810_syscon1: sysctl@1001a000 { 496 compatible = "arm,sp810", "arm,primecell"; 497 reg = <0x1001a000 0x1000>; 498 clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>; 499 clock-names = "refclk", "timclk", "apb_pclk"; 500 #clock-cells = <1>; 501 clock-output-names = "timerclk4", 502 "timerclk5", 503 "timerclk6", 504 "timerclk7"; 505 assigned-clocks = <&sp810_syscon1 0>, 506 <&sp810_syscon1 1>, 507 <&sp810_syscon1 2>, 508 <&sp810_syscon1 3>; 509 assigned-clock-parents = <&timclk>, 510 <&timclk>, 511 <&timclk>, 512 <&timclk>; 513 }; 514 }; 515 516 517 /* These peripherals are inside the FPGA */ 518 fpga { 519 #address-cells = <1>; 520 #size-cells = <1>; 521 compatible = "simple-bus"; 522 ranges; 523 524 aaci: aaci@10004000 { 525 compatible = "arm,pl041", "arm,primecell"; 526 reg = <0x10004000 0x1000>; 527 clocks = <&pclk>; 528 clock-names = "apb_pclk"; 529 }; 530 531 mmc: mmcsd@10005000 { 532 compatible = "arm,pl18x", "arm,primecell"; 533 reg = <0x10005000 0x1000>; 534 535 /* Due to frequent FIFO overruns, use just 500 kHz */ 536 max-frequency = <500000>; 537 bus-width = <4>; 538 cap-sd-highspeed; 539 cap-mmc-highspeed; 540 clocks = <&mclk>, <&pclk>; 541 clock-names = "mclk", "apb_pclk"; 542 vmmc-supply = <&vmmc>; 543 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 544 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; 545 }; 546 547 kmi0: kmi@10006000 { 548 compatible = "arm,pl050", "arm,primecell"; 549 reg = <0x10006000 0x1000>; 550 clocks = <&kmiclk>, <&pclk>; 551 clock-names = "KMIREFCLK", "apb_pclk"; 552 }; 553 554 kmi1: kmi@10007000 { 555 compatible = "arm,pl050", "arm,primecell"; 556 reg = <0x10007000 0x1000>; 557 clocks = <&kmiclk>, <&pclk>; 558 clock-names = "KMIREFCLK", "apb_pclk"; 559 }; 560 561 serial3: serial@1000c000 { 562 compatible = "arm,pl011", "arm,primecell"; 563 reg = <0x1000c000 0x1000>; 564 clocks = <&uartclk>, <&pclk>; 565 clock-names = "uartclk", "apb_pclk"; 566 }; 567 }; 568 569 /* These peripherals are inside the NEC ISSP */ 570 issp { 571 #address-cells = <1>; 572 #size-cells = <1>; 573 compatible = "simple-bus"; 574 ranges; 575 576 clcd: clcd@10020000 { 577 compatible = "arm,pl111", "arm,primecell"; 578 reg = <0x10020000 0x1000>; 579 interrupt-names = "combined"; 580 clocks = <&oscclk4>, <&pclk>; 581 clock-names = "clcdclk", "apb_pclk"; 582 /* 1024x768 16bpp @65MHz works fine */ 583 max-memory-bandwidth = <95000000>; 584 585 port { 586 clcd_pads: endpoint { 587 remote-endpoint = <&vga_bridge_in>; 588 arm,pl11x,tft-r0g0b0-pads = <0 8 16>; 589 }; 590 }; 591 }; 592 }; 593 };
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