The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)

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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/armada-385-clearfog-gtr-s4.dts

Version: -  FREEBSD  -  FREEBSD-13-STABLE  -  FREEBSD-13-0  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  l41  -  OPENBSD  -  linux-2.6  -  MK84  -  PLAN9  -  xnu-8792 
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    1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
    2 
    3 #include "armada-385-clearfog-gtr.dtsi"
    4 
    5 / {
    6         model = "SolidRun Clearfog GTR S4";
    7 };
    8 
    9 &sfp0 {
   10         tx-fault-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
   11 };
   12 
   13 &mdio {
   14         switch0: switch0@4 {
   15                 compatible = "marvell,mv88e6085";
   16                 reg = <4>;
   17                 pinctrl-names = "default";
   18                 pinctrl-0 = <&cf_gtr_switch_reset_pins>;
   19                 reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
   20 
   21                 ports {
   22                         #address-cells = <1>;
   23                         #size-cells = <0>;
   24 
   25                         port@1 {
   26                                 reg = <1>;
   27                                 label = "lan2";
   28                                 phy-handle = <&switch0phy0>;
   29                         };
   30 
   31                         port@2 {
   32                                 reg = <2>;
   33                                 label = "lan1";
   34                                 phy-handle = <&switch0phy1>;
   35                         };
   36 
   37                         port@3 {
   38                                 reg = <3>;
   39                                 label = "lan4";
   40                                 phy-handle = <&switch0phy2>;
   41                         };
   42 
   43                         port@4 {
   44                                 reg = <4>;
   45                                 label = "lan3";
   46                                 phy-handle = <&switch0phy3>;
   47                         };
   48 
   49                         port@5 {
   50                                 reg = <5>;
   51                                 label = "cpu";
   52                                 ethernet = <&eth1>;
   53                         };
   54 
   55                 };
   56 
   57                 mdio {
   58                         #address-cells = <1>;
   59                         #size-cells = <0>;
   60 
   61                         switch0phy0: switch0phy0@11 {
   62                                 reg = <0x11>;
   63                         };
   64 
   65                         switch0phy1: switch0phy1@12 {
   66                                 reg = <0x12>;
   67                         };
   68 
   69                         switch0phy2: switch0phy2@13 {
   70                                 reg = <0x13>;
   71                         };
   72 
   73                         switch0phy3: switch0phy3@14 {
   74                                 reg = <0x14>;
   75                         };
   76                 };
   77 
   78         };
   79 };

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