armada-385-db-ap.dts

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    1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
    2 /*
    3  * Device Tree file for Marvell Armada 385 Access Point Development board
    4  * (DB-88F6820-AP)
    5  *
    6  *  Copyright (C) 2014 Marvell
    7  *
    8  * Nadav Haklai <nadavh@marvell.com>
    9  */
   10 
   11 /dts-v1/;
   12 #include "armada-385.dtsi"
   13 
   14 #include <dt-bindings/gpio/gpio.h>
   15 
   16 / {
   17         model = "Marvell Armada 385 Access Point Development Board";
   18         compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada380";
   19 
   20         chosen {
   21                 stdout-path = "serial1:115200n8";
   22         };
   23 
   24         memory {
   25                 device_type = "memory";
   26                 reg = <0x00000000 0x80000000>; /* 2GB */
   27         };
   28 
   29         soc {
   30                 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
   31                           MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
   32                           MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
   33                           MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
   34                           MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
   35 
   36                 internal-regs {
   37                         i2c0: i2c@11000 {
   38                                 pinctrl-names = "default";
   39                                 pinctrl-0 = <&i2c0_pins>;
   40                                 status = "okay";
   41 
   42                                 /*
   43                                  * This bus is wired to two EEPROM
   44                                  * sockets, one of which holding the
   45                                  * board ID used by the bootloader.
   46                                  * Erasing this EEPROM's content will
   47                                  * brick the board.
   48                                  * Use this bus with caution.
   49                                  */
   50                         };
   51 
   52                         mdio@72004 {
   53                                 pinctrl-names = "default";
   54                                 pinctrl-0 = <&mdio_pins>;
   55 
   56                                 phy0: ethernet-phy@1 {
   57                                         reg = <1>;
   58                                 };
   59 
   60                                 phy1: ethernet-phy@4 {
   61                                         reg = <4>;
   62                                 };
   63 
   64                                 phy2: ethernet-phy@6 {
   65                                         reg = <6>;
   66                                 };
   67                         };
   68 
   69                         /* UART0 is exposed through the JP8 connector */
   70                         uart0: serial@12000 {
   71                                 pinctrl-names = "default";
   72                                 pinctrl-0 = <&uart0_pins>;
   73                                 status = "okay";
   74                         };
   75 
   76                         /*
   77                          * UART1 is exposed through a FTDI chip
   78                          * wired to the mini-USB connector
   79                          */
   80                         uart1: serial@12100 {
   81                                 pinctrl-names = "default";
   82                                 pinctrl-0 = <&uart1_pins>;
   83                                 status = "okay";
   84                         };
   85 
   86                         pinctrl@18000 {
   87                                 xhci0_vbus_pins: xhci0-vbus-pins {
   88                                         marvell,pins = "mpp44";
   89                                         marvell,function = "gpio";
   90                                 };
   91                         };
   92 
   93                         /* CON3 */
   94                         ethernet@30000 {
   95                                 status = "okay";
   96                                 phy = <&phy2>;
   97                                 phy-mode = "sgmii";
   98                                 buffer-manager = <&bm>;
   99                                 bm,pool-long = <1>;
  100                                 bm,pool-short = <3>;
  101                         };
  102 
  103                         /* CON2 */
  104                         ethernet@34000 {
  105                                 status = "okay";
  106                                 phy = <&phy1>;
  107                                 phy-mode = "sgmii";
  108                                 buffer-manager = <&bm>;
  109                                 bm,pool-long = <2>;
  110                                 bm,pool-short = <3>;
  111                         };
  112 
  113                         usb@58000 {
  114                                 status = "okay";
  115                         };
  116 
  117                         /* CON4 */
  118                         ethernet@70000 {
  119                                 pinctrl-names = "default";
  120 
  121                                 /*
  122                                  * The Reference Clock 0 is used to
  123                                  * provide a clock to the PHY
  124                                  */
  125                                 pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
  126                                 status = "okay";
  127                                 phy = <&phy0>;
  128                                 phy-mode = "rgmii-id";
  129                                 buffer-manager = <&bm>;
  130                                 bm,pool-long = <0>;
  131                                 bm,pool-short = <3>;
  132                         };
  133 
  134                         bm@c8000 {
  135                                 status = "okay";
  136                         };
  137 
  138                         usb3@f0000 {
  139                                 status = "okay";
  140                                 usb-phy = <&usb3_phy>;
  141                         };
  142                 };
  143 
  144                 bm-bppi {
  145                         status = "okay";
  146                 };
  147 
  148                 pcie {
  149                         status = "okay";
  150 
  151                         /*
  152                          * The three PCIe units are accessible through
  153                          * standard mini-PCIe slots on the board.
  154                          */
  155                         pcie@1,0 {
  156                                 /* Port 0, Lane 0 */
  157                                 status = "okay";
  158                         };
  159 
  160                         pcie@2,0 {
  161                                 /* Port 1, Lane 0 */
  162                                 status = "okay";
  163                         };
  164 
  165                         pcie@3,0 {
  166                                 /* Port 2, Lane 0 */
  167                                 status = "okay";
  168                         };
  169                 };
  170         };
  171 
  172         usb3_phy: usb3_phy {
  173                 compatible = "usb-nop-xceiv";
  174                 vcc-supply = <&reg_xhci0_vbus>;
  175                 #phy-cells = <0>;
  176         };
  177 
  178         reg_xhci0_vbus: xhci0-vbus {
  179                 compatible = "regulator-fixed";
  180                 pinctrl-names = "default";
  181                 pinctrl-0 = <&xhci0_vbus_pins>;
  182                 regulator-name = "xhci0-vbus";
  183                 regulator-min-microvolt = <5000000>;
  184                 regulator-max-microvolt = <5000000>;
  185                 enable-active-high;
  186                 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
  187         };
  188 };
  189 
  190 &spi1 {
  191         pinctrl-names = "default";
  192         pinctrl-0 = <&spi1_pins>;
  193         status = "okay";
  194 
  195         flash@0 {
  196                 #address-cells = <1>;
  197                 #size-cells = <1>;
  198                 compatible = "st,m25p128", "jedec,spi-nor";
  199                 reg = <0>; /* Chip select 0 */
  200                 spi-max-frequency = <54000000>;
  201         };
  202 };
  203 
  204 &nand_controller {
  205         status = "okay";
  206 
  207         nand@0 {
  208                 reg = <0>;
  209                 label = "pxa3xx_nand-0";
  210                 nand-rb = <0>;
  211                 nand-on-flash-bbt;
  212                 nand-ecc-strength = <4>;
  213                 nand-ecc-step-size = <512>;
  214 
  215                 partitions {
  216                         compatible = "fixed-partitions";
  217                         #address-cells = <1>;
  218                         #size-cells = <1>;
  219 
  220                         partition@0 {
  221                                 label = "U-Boot";
  222                                 reg = <0x00000000 0x00800000>;
  223                                 read-only;
  224                         };
  225 
  226                         partition@800000 {
  227                                 label = "uImage";
  228                                 reg = <0x00800000 0x00400000>;
  229                                 read-only;
  230                         };
  231 
  232                         partition@c00000 {
  233                                 label = "Root";
  234                                 reg = <0x00c00000 0x3f400000>;
  235                         };
  236                 };
  237         };
  238 };

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