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sys/contrib/device-tree/src/arm/armada-385.dtsi
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1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Device Tree Include file for Marvell Armada 385 SoC. 4 * 5 * Copyright (C) 2014 Marvell 6 * 7 * Lior Amsalem <alior@marvell.com> 8 * Gregory CLEMENT <gregory.clement@free-electrons.com> 9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 10 */ 11 12 #include "armada-38x.dtsi" 13 14 / { 15 model = "Marvell Armada 385 family SoC"; 16 compatible = "marvell,armada385", "marvell,armada380"; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 enable-method = "marvell,armada-380-smp"; 22 23 cpu@0 { 24 device_type = "cpu"; 25 compatible = "arm,cortex-a9"; 26 reg = <0>; 27 }; 28 cpu@1 { 29 device_type = "cpu"; 30 compatible = "arm,cortex-a9"; 31 reg = <1>; 32 }; 33 }; 34 35 soc { 36 pciec: pcie { 37 compatible = "marvell,armada-370-pcie"; 38 status = "disabled"; 39 device_type = "pci"; 40 41 #address-cells = <3>; 42 #size-cells = <2>; 43 44 msi-parent = <&mpic>; 45 bus-range = <0x00 0xff>; 46 47 ranges = 48 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 49 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 50 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 51 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 52 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ 53 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ 54 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ 55 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ 56 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ 57 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */ 58 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */ 59 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>; 60 61 /* 62 * This port can be either x4 or x1. When 63 * configured in x4 by the bootloader, then 64 * pcie@4,0 is not available. 65 */ 66 pcie1: pcie@1,0 { 67 device_type = "pci"; 68 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; 69 reg = <0x0800 0 0 0 0>; 70 #address-cells = <3>; 71 #size-cells = <2>; 72 interrupt-names = "intx"; 73 interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 74 #interrupt-cells = <1>; 75 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 76 0x81000000 0 0 0x81000000 0x1 0 1 0>; 77 bus-range = <0x00 0xff>; 78 interrupt-map-mask = <0 0 0 7>; 79 interrupt-map = <0 0 0 1 &pcie1_intc 0>, 80 <0 0 0 2 &pcie1_intc 1>, 81 <0 0 0 3 &pcie1_intc 2>, 82 <0 0 0 4 &pcie1_intc 3>; 83 marvell,pcie-port = <0>; 84 marvell,pcie-lane = <0>; 85 clocks = <&gateclk 8>; 86 status = "disabled"; 87 pcie1_intc: interrupt-controller { 88 interrupt-controller; 89 #interrupt-cells = <1>; 90 }; 91 }; 92 93 /* x1 port */ 94 pcie2: pcie@2,0 { 95 device_type = "pci"; 96 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 97 reg = <0x1000 0 0 0 0>; 98 #address-cells = <3>; 99 #size-cells = <2>; 100 interrupt-names = "intx"; 101 interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 102 #interrupt-cells = <1>; 103 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 104 0x81000000 0 0 0x81000000 0x2 0 1 0>; 105 bus-range = <0x00 0xff>; 106 interrupt-map-mask = <0 0 0 7>; 107 interrupt-map = <0 0 0 1 &pcie2_intc 0>, 108 <0 0 0 2 &pcie2_intc 1>, 109 <0 0 0 3 &pcie2_intc 2>, 110 <0 0 0 4 &pcie2_intc 3>; 111 marvell,pcie-port = <1>; 112 marvell,pcie-lane = <0>; 113 clocks = <&gateclk 5>; 114 status = "disabled"; 115 pcie2_intc: interrupt-controller { 116 interrupt-controller; 117 #interrupt-cells = <1>; 118 }; 119 }; 120 121 /* x1 port */ 122 pcie3: pcie@3,0 { 123 device_type = "pci"; 124 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; 125 reg = <0x1800 0 0 0 0>; 126 #address-cells = <3>; 127 #size-cells = <2>; 128 interrupt-names = "intx"; 129 interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 130 #interrupt-cells = <1>; 131 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 132 0x81000000 0 0 0x81000000 0x3 0 1 0>; 133 bus-range = <0x00 0xff>; 134 interrupt-map-mask = <0 0 0 7>; 135 interrupt-map = <0 0 0 1 &pcie3_intc 0>, 136 <0 0 0 2 &pcie3_intc 1>, 137 <0 0 0 3 &pcie3_intc 2>, 138 <0 0 0 4 &pcie3_intc 3>; 139 marvell,pcie-port = <2>; 140 marvell,pcie-lane = <0>; 141 clocks = <&gateclk 6>; 142 status = "disabled"; 143 pcie3_intc: interrupt-controller { 144 interrupt-controller; 145 #interrupt-cells = <1>; 146 }; 147 }; 148 149 /* 150 * x1 port only available when pcie@1,0 is 151 * configured as a x1 port 152 */ 153 pcie4: pcie@4,0 { 154 device_type = "pci"; 155 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; 156 reg = <0x2000 0 0 0 0>; 157 #address-cells = <3>; 158 #size-cells = <2>; 159 interrupt-names = "intx"; 160 interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 161 #interrupt-cells = <1>; 162 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 163 0x81000000 0 0 0x81000000 0x4 0 1 0>; 164 bus-range = <0x00 0xff>; 165 interrupt-map-mask = <0 0 0 7>; 166 interrupt-map = <0 0 0 1 &pcie4_intc 0>, 167 <0 0 0 2 &pcie4_intc 1>, 168 <0 0 0 3 &pcie4_intc 2>, 169 <0 0 0 4 &pcie4_intc 3>; 170 marvell,pcie-port = <3>; 171 marvell,pcie-lane = <0>; 172 clocks = <&gateclk 7>; 173 status = "disabled"; 174 pcie4_intc: interrupt-controller { 175 interrupt-controller; 176 #interrupt-cells = <1>; 177 }; 178 }; 179 }; 180 }; 181 }; 182 183 &pinctrl { 184 compatible = "marvell,mv88f6820-pinctrl"; 185 };
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