armada-388-rd.dts

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    1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
    2 /*
    3  * Device Tree file for Marvell Armada 388 Reference Design board
    4  * (RD-88F6820-AP)
    5  *
    6  *  Copyright (C) 2014 Marvell
    7  *
    8  * Gregory CLEMENT <gregory.clement@free-electrons.com>
    9  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   10  */
   11 
   12 /dts-v1/;
   13 #include "armada-388.dtsi"
   14 
   15 / {
   16         model = "Marvell Armada 385 Reference Design";
   17         compatible = "marvell,a385-rd", "marvell,armada388",
   18                 "marvell,armada385","marvell,armada380";
   19 
   20         chosen {
   21                 stdout-path = "serial0:115200n8";
   22         };
   23 
   24         memory {
   25                 device_type = "memory";
   26                 reg = <0x00000000 0x10000000>; /* 256 MB */
   27         };
   28 
   29         soc {
   30                 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
   31                           MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
   32                           MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
   33                           MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
   34 
   35                 internal-regs {
   36                         i2c@11000 {
   37                                 status = "okay";
   38                                 clock-frequency = <100000>;
   39                         };
   40 
   41                         sdhci@d8000 {
   42                                 pinctrl-names = "default";
   43                                 pinctrl-0 = <&sdhci_pins>;
   44                                 broken-cd;
   45                                 no-1-8-v;
   46                                 wp-inverted;
   47                                 bus-width = <8>;
   48                                 status = "okay";
   49                         };
   50 
   51                         serial@12000 {
   52                                 status = "okay";
   53                         };
   54 
   55                         ethernet@30000 {
   56                                 status = "okay";
   57                                 phy = <&phy0>;
   58                                 phy-mode = "rgmii-id";
   59                         };
   60 
   61                         ethernet@70000 {
   62                                 status = "okay";
   63                                 phy = <&phy1>;
   64                                 phy-mode = "rgmii-id";
   65                         };
   66 
   67 
   68                         mdio@72004 {
   69                                 phy0: ethernet-phy@0 {
   70                                         reg = <0>;
   71                                 };
   72 
   73                                 phy1: ethernet-phy@1 {
   74                                         reg = <1>;
   75                                 };
   76                         };
   77 
   78                         usb3@f0000 {
   79                                 status = "okay";
   80                         };
   81                 };
   82 
   83                 pcie {
   84                         status = "okay";
   85                         /*
   86                          * One PCIe units is accessible through
   87                          * standard PCIe slot on the board.
   88                          */
   89                         pcie@1,0 {
   90                                 /* Port 0, Lane 0 */
   91                                 status = "okay";
   92                         };
   93                 };
   94         };
   95 };
   96 
   97 &spi0 {
   98         status = "okay";
   99 
  100         flash@0 {
  101                 #address-cells = <1>;
  102                 #size-cells = <1>;
  103                 compatible = "st,m25p128", "jedec,spi-nor";
  104                 reg = <0>; /* Chip select 0 */
  105                 spi-max-frequency = <108000000>;
  106         };
  107 };
  108

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