The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/armada-38x-solidrun-microsom.dtsi

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    1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
    2 /*
    3  * Device Tree file for SolidRun Armada 38x Microsom
    4  *
    5  *  Copyright (C) 2015 Russell King
    6  */
    7 #include <dt-bindings/input/input.h>
    8 #include <dt-bindings/gpio/gpio.h>
    9 
   10 / {
   11         memory {
   12                 device_type = "memory";
   13                 reg = <0x00000000 0x10000000>; /* 256 MB */
   14         };
   15 
   16         soc {
   17                 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
   18                           MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
   19                           MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
   20                           MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
   21                           MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
   22 
   23                 internal-regs {
   24                         rtc@a3800 {
   25                                 /*
   26                                  * If the rtc doesn't work, run "date reset"
   27                                  * twice in u-boot.
   28                                  */
   29                                 status = "okay";
   30                         };
   31                 };
   32         };
   33 };
   34 
   35 &bm {
   36         status = "okay";
   37 };
   38 
   39 &bm_bppi {
   40         status = "okay";
   41 };
   42 
   43 &eth0 {
   44         /* ethernet@70000 */
   45         pinctrl-0 = <&ge0_rgmii_pins>;
   46         pinctrl-names = "default";
   47         phy = <&phy_dedicated>;
   48         phy-mode = "rgmii-id";
   49         buffer-manager = <&bm>;
   50         bm,pool-long = <0>;
   51         bm,pool-short = <1>;
   52         status = "okay";
   53 };
   54 
   55 &mdio {
   56         /*
   57          * Add the phy clock here, so the phy can be accessed to read its
   58          * IDs prior to binding with the driver.
   59          */
   60         pinctrl-0 = <&mdio_pins &microsom_phy_clk_pins>;
   61         pinctrl-names = "default";
   62 
   63         phy_dedicated: ethernet-phy@0 {
   64                 /*
   65                  * Annoyingly, the marvell phy driver configures the LED
   66                  * register, rather than preserving reset-loaded setting.
   67                  * We undo that rubbish here.
   68                  */
   69                 marvell,reg-init = <3 16 0 0x101e>;
   70                 reg = <0>;
   71         };
   72 };
   73 
   74 &i2c0 {
   75         clock-frequency = <400000>;
   76         pinctrl-0 = <&i2c0_pins>;
   77         pinctrl-names = "default";
   78         status = "okay";
   79 
   80         eeprom@53 {
   81                 compatible = "atmel,24c02";
   82                 reg = <0x53>;
   83                 pagesize = <16>;
   84         };
   85 };
   86 
   87 &pinctrl {
   88         microsom_phy_clk_pins: microsom-phy-clk-pins {
   89                 marvell,pins = "mpp45";
   90                 marvell,function = "ref";
   91         };
   92         /* Optional eMMC */
   93         microsom_sdhci_pins: microsom-sdhci-pins {
   94                 marvell,pins = "mpp21", "mpp28", "mpp37",
   95                                "mpp38", "mpp39", "mpp40";
   96                 marvell,function = "sd0";
   97         };
   98 };
   99 
  100 &spi1 {
  101         /* The microsom has an optional W25Q32 on board, connected to CS0 */
  102         pinctrl-0 = <&spi1_pins>;
  103 
  104         w25q32: flash@0 {
  105                 #address-cells = <1>;
  106                 #size-cells = <1>;
  107                 compatible = "w25q32", "jedec,spi-nor";
  108                 reg = <0>; /* Chip select 0 */
  109                 spi-max-frequency = <3000000>;
  110         };
  111 };
  112 
  113 &uart0 {
  114         pinctrl-0 = <&uart0_pins>;
  115         pinctrl-names = "default";
  116         status = "okay";
  117 };

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