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sys/contrib/device-tree/src/arm/armada-38x.dtsi
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1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Device Tree Include file for Marvell Armada 38x family of SoCs. 4 * 5 * Copyright (C) 2014 Marvell 6 * 7 * Lior Amsalem <alior@marvell.com> 8 * Gregory CLEMENT <gregory.clement@free-electrons.com> 9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 10 */ 11 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 #include <dt-bindings/interrupt-controller/irq.h> 14 15 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) 16 17 / { 18 #address-cells = <1>; 19 #size-cells = <1>; 20 21 model = "Marvell Armada 38x family SoC"; 22 compatible = "marvell,armada380"; 23 24 aliases { 25 gpio0 = &gpio0; 26 gpio1 = &gpio1; 27 serial0 = &uart0; 28 serial1 = &uart1; 29 }; 30 31 pmu { 32 compatible = "arm,cortex-a9-pmu"; 33 interrupts-extended = <&mpic 3>; 34 }; 35 36 soc { 37 compatible = "marvell,armada380-mbus", "simple-bus"; 38 #address-cells = <2>; 39 #size-cells = <1>; 40 controller = <&mbusc>; 41 interrupt-parent = <&gic>; 42 pcie-mem-aperture = <0xe0000000 0x8000000>; 43 pcie-io-aperture = <0xe8000000 0x100000>; 44 45 bootrom { 46 compatible = "marvell,bootrom"; 47 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>; 48 }; 49 50 devbus_bootcs: devbus-bootcs { 51 compatible = "marvell,mvebu-devbus"; 52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>; 53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; 54 #address-cells = <1>; 55 #size-cells = <1>; 56 clocks = <&coreclk 0>; 57 status = "disabled"; 58 }; 59 60 devbus_cs0: devbus-cs0 { 61 compatible = "marvell,mvebu-devbus"; 62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>; 63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; 64 #address-cells = <1>; 65 #size-cells = <1>; 66 clocks = <&coreclk 0>; 67 status = "disabled"; 68 }; 69 70 devbus_cs1: devbus-cs1 { 71 compatible = "marvell,mvebu-devbus"; 72 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>; 73 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; 74 #address-cells = <1>; 75 #size-cells = <1>; 76 clocks = <&coreclk 0>; 77 status = "disabled"; 78 }; 79 80 devbus_cs2: devbus-cs2 { 81 compatible = "marvell,mvebu-devbus"; 82 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>; 83 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; 84 #address-cells = <1>; 85 #size-cells = <1>; 86 clocks = <&coreclk 0>; 87 status = "disabled"; 88 }; 89 90 devbus_cs3: devbus-cs3 { 91 compatible = "marvell,mvebu-devbus"; 92 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>; 93 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; 94 #address-cells = <1>; 95 #size-cells = <1>; 96 clocks = <&coreclk 0>; 97 status = "disabled"; 98 }; 99 100 internal-regs { 101 compatible = "simple-bus"; 102 #address-cells = <1>; 103 #size-cells = <1>; 104 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; 105 106 sdramc: sdramc@1400 { 107 compatible = "marvell,armada-xp-sdram-controller"; 108 reg = <0x1400 0x500>; 109 }; 110 111 L2: cache-controller@8000 { 112 compatible = "arm,pl310-cache"; 113 reg = <0x8000 0x1000>; 114 cache-unified; 115 cache-level = <2>; 116 arm,double-linefill-incr = <0>; 117 arm,double-linefill-wrap = <0>; 118 arm,double-linefill = <0>; 119 prefetch-data = <1>; 120 }; 121 122 scu@c000 { 123 compatible = "arm,cortex-a9-scu"; 124 reg = <0xc000 0x58>; 125 }; 126 127 timer@c200 { 128 compatible = "arm,cortex-a9-global-timer"; 129 reg = <0xc200 0x20>; 130 interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; 131 clocks = <&coreclk 2>; 132 }; 133 134 timer@c600 { 135 compatible = "arm,cortex-a9-twd-timer"; 136 reg = <0xc600 0x20>; 137 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; 138 clocks = <&coreclk 2>; 139 }; 140 141 gic: interrupt-controller@d000 { 142 compatible = "arm,cortex-a9-gic"; 143 #interrupt-cells = <3>; 144 #size-cells = <0>; 145 interrupt-controller; 146 reg = <0xd000 0x1000>, 147 <0xc100 0x100>; 148 }; 149 150 i2c0: i2c@11000 { 151 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c"; 152 reg = <0x11000 0x20>; 153 #address-cells = <1>; 154 #size-cells = <0>; 155 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 156 clocks = <&coreclk 0>; 157 status = "disabled"; 158 }; 159 160 i2c1: i2c@11100 { 161 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c"; 162 reg = <0x11100 0x20>; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 166 clocks = <&coreclk 0>; 167 status = "disabled"; 168 }; 169 170 uart0: serial@12000 { 171 compatible = "marvell,armada-38x-uart", "ns16550a"; 172 reg = <0x12000 0x100>; 173 reg-shift = <2>; 174 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 175 reg-io-width = <1>; 176 clocks = <&coreclk 0>; 177 status = "disabled"; 178 }; 179 180 uart1: serial@12100 { 181 compatible = "marvell,armada-38x-uart", "ns16550a"; 182 reg = <0x12100 0x100>; 183 reg-shift = <2>; 184 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 185 reg-io-width = <1>; 186 clocks = <&coreclk 0>; 187 status = "disabled"; 188 }; 189 190 pinctrl: pinctrl@18000 { 191 reg = <0x18000 0x20>; 192 193 ge0_rgmii_pins: ge-rgmii-pins-0 { 194 marvell,pins = "mpp6", "mpp7", "mpp8", 195 "mpp9", "mpp10", "mpp11", 196 "mpp12", "mpp13", "mpp14", 197 "mpp15", "mpp16", "mpp17"; 198 marvell,function = "ge0"; 199 }; 200 201 ge1_rgmii_pins: ge-rgmii-pins-1 { 202 marvell,pins = "mpp21", "mpp27", "mpp28", 203 "mpp29", "mpp30", "mpp31", 204 "mpp32", "mpp37", "mpp38", 205 "mpp39", "mpp40", "mpp41"; 206 marvell,function = "ge1"; 207 }; 208 209 i2c0_pins: i2c-pins-0 { 210 marvell,pins = "mpp2", "mpp3"; 211 marvell,function = "i2c0"; 212 }; 213 214 mdio_pins: mdio-pins { 215 marvell,pins = "mpp4", "mpp5"; 216 marvell,function = "ge"; 217 }; 218 219 ref_clk0_pins: ref-clk-pins-0 { 220 marvell,pins = "mpp45"; 221 marvell,function = "ref"; 222 }; 223 224 ref_clk1_pins: ref-clk-pins-1 { 225 marvell,pins = "mpp46"; 226 marvell,function = "ref"; 227 }; 228 229 spi0_pins: spi-pins-0 { 230 marvell,pins = "mpp22", "mpp23", "mpp24", 231 "mpp25"; 232 marvell,function = "spi0"; 233 }; 234 235 spi1_pins: spi-pins-1 { 236 marvell,pins = "mpp56", "mpp57", "mpp58", 237 "mpp59"; 238 marvell,function = "spi1"; 239 }; 240 241 nand_pins: nand-pins { 242 marvell,pins = "mpp22", "mpp34", "mpp23", 243 "mpp33", "mpp38", "mpp28", 244 "mpp40", "mpp42", "mpp35", 245 "mpp36", "mpp25", "mpp30", 246 "mpp32"; 247 marvell,function = "dev"; 248 }; 249 250 nand_rb: nand-rb { 251 marvell,pins = "mpp41"; 252 marvell,function = "nand"; 253 }; 254 255 uart0_pins: uart-pins-0 { 256 marvell,pins = "mpp0", "mpp1"; 257 marvell,function = "ua0"; 258 }; 259 260 uart1_pins: uart-pins-1 { 261 marvell,pins = "mpp19", "mpp20"; 262 marvell,function = "ua1"; 263 }; 264 265 sdhci_pins: sdhci-pins { 266 marvell,pins = "mpp48", "mpp49", "mpp50", 267 "mpp52", "mpp53", "mpp54", 268 "mpp55", "mpp57", "mpp58", 269 "mpp59"; 270 marvell,function = "sd0"; 271 }; 272 273 sata0_pins: sata-pins-0 { 274 marvell,pins = "mpp20"; 275 marvell,function = "sata0"; 276 }; 277 278 sata1_pins: sata-pins-1 { 279 marvell,pins = "mpp19"; 280 marvell,function = "sata1"; 281 }; 282 283 sata2_pins: sata-pins-2 { 284 marvell,pins = "mpp47"; 285 marvell,function = "sata2"; 286 }; 287 288 sata3_pins: sata-pins-3 { 289 marvell,pins = "mpp44"; 290 marvell,function = "sata3"; 291 }; 292 }; 293 294 gpio0: gpio@18100 { 295 compatible = "marvell,armada-370-gpio", 296 "marvell,orion-gpio"; 297 reg = <0x18100 0x40>, <0x181c0 0x08>; 298 reg-names = "gpio", "pwm"; 299 ngpios = <32>; 300 gpio-controller; 301 #gpio-cells = <2>; 302 #pwm-cells = <2>; 303 interrupt-controller; 304 #interrupt-cells = <2>; 305 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 309 clocks = <&coreclk 0>; 310 }; 311 312 gpio1: gpio@18140 { 313 compatible = "marvell,armada-370-gpio", 314 "marvell,orion-gpio"; 315 reg = <0x18140 0x40>, <0x181c8 0x08>; 316 reg-names = "gpio", "pwm"; 317 ngpios = <28>; 318 gpio-controller; 319 #gpio-cells = <2>; 320 #pwm-cells = <2>; 321 interrupt-controller; 322 #interrupt-cells = <2>; 323 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&coreclk 0>; 328 }; 329 330 systemc: system-controller@18200 { 331 compatible = "marvell,armada-380-system-controller", 332 "marvell,armada-370-xp-system-controller"; 333 reg = <0x18200 0x100>; 334 }; 335 336 gateclk: clock-gating-control@18220 { 337 compatible = "marvell,armada-380-gating-clock"; 338 reg = <0x18220 0x4>; 339 clocks = <&coreclk 0>; 340 #clock-cells = <1>; 341 }; 342 343 comphy: phy@18300 { 344 compatible = "marvell,armada-380-comphy"; 345 reg-names = "comphy", "conf"; 346 reg = <0x18300 0x100>, <0x18460 4>; 347 #address-cells = <1>; 348 #size-cells = <0>; 349 350 comphy0: phy@0 { 351 reg = <0>; 352 #phy-cells = <1>; 353 }; 354 355 comphy1: phy@1 { 356 reg = <1>; 357 #phy-cells = <1>; 358 }; 359 360 comphy2: phy@2 { 361 reg = <2>; 362 #phy-cells = <1>; 363 }; 364 365 comphy3: phy@3 { 366 reg = <3>; 367 #phy-cells = <1>; 368 }; 369 370 comphy4: phy@4 { 371 reg = <4>; 372 #phy-cells = <1>; 373 }; 374 375 comphy5: phy@5 { 376 reg = <5>; 377 #phy-cells = <1>; 378 }; 379 }; 380 381 coreclk: mvebu-sar@18600 { 382 compatible = "marvell,armada-380-core-clock"; 383 reg = <0x18600 0x04>; 384 #clock-cells = <1>; 385 }; 386 387 mbusc: mbus-controller@20000 { 388 compatible = "marvell,mbus-controller"; 389 reg = <0x20000 0x100>, <0x20180 0x20>, 390 <0x20250 0x8>; 391 }; 392 393 mpic: interrupt-controller@20a00 { 394 compatible = "marvell,mpic"; 395 reg = <0x20a00 0x2d0>, <0x21070 0x58>; 396 #interrupt-cells = <1>; 397 #size-cells = <1>; 398 interrupt-controller; 399 msi-controller; 400 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 401 }; 402 403 timer: timer@20300 { 404 compatible = "marvell,armada-380-timer", 405 "marvell,armada-xp-timer"; 406 reg = <0x20300 0x30>, <0x21040 0x30>; 407 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 408 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 409 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 410 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 411 <&mpic 5>, 412 <&mpic 6>; 413 clocks = <&coreclk 2>, <&refclk>; 414 clock-names = "nbclk", "fixed"; 415 }; 416 417 watchdog: watchdog@20300 { 418 compatible = "marvell,armada-380-wdt"; 419 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>; 420 clocks = <&coreclk 2>, <&refclk>; 421 clock-names = "nbclk", "fixed"; 422 interrupts-extended = <&gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 423 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 424 }; 425 426 cpurst: cpurst@20800 { 427 compatible = "marvell,armada-370-cpu-reset"; 428 reg = <0x20800 0x10>; 429 }; 430 431 mpcore-soc-ctrl@20d20 { 432 compatible = "marvell,armada-380-mpcore-soc-ctrl"; 433 reg = <0x20d20 0x6c>; 434 }; 435 436 coherencyfab: coherency-fabric@21010 { 437 compatible = "marvell,armada-380-coherency-fabric"; 438 reg = <0x21010 0x1c>; 439 }; 440 441 pmsu: pmsu@22000 { 442 compatible = "marvell,armada-380-pmsu"; 443 reg = <0x22000 0x1000>; 444 }; 445 446 /* 447 * As a special exception to the "order by 448 * register address" rule, the eth0 node is 449 * placed here to ensure that it gets 450 * registered as the first interface, since 451 * the network subsystem doesn't allow naming 452 * interfaces using DT aliases. Without this, 453 * the ordering of interfaces is different 454 * from the one used in U-Boot and the 455 * labeling of interfaces on the boards, which 456 * is very confusing for users. 457 */ 458 eth0: ethernet@70000 { 459 compatible = "marvell,armada-370-neta"; 460 reg = <0x70000 0x4000>; 461 interrupts-extended = <&mpic 8>; 462 clocks = <&gateclk 4>; 463 tx-csum-limit = <9800>; 464 status = "disabled"; 465 }; 466 467 eth1: ethernet@30000 { 468 compatible = "marvell,armada-370-neta"; 469 reg = <0x30000 0x4000>; 470 interrupts-extended = <&mpic 10>; 471 clocks = <&gateclk 3>; 472 status = "disabled"; 473 }; 474 475 eth2: ethernet@34000 { 476 compatible = "marvell,armada-370-neta"; 477 reg = <0x34000 0x4000>; 478 interrupts-extended = <&mpic 12>; 479 clocks = <&gateclk 2>; 480 status = "disabled"; 481 }; 482 483 usb0: usb@58000 { 484 compatible = "marvell,orion-ehci"; 485 reg = <0x58000 0x500>; 486 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&gateclk 18>; 488 status = "disabled"; 489 }; 490 491 xor0: xor@60800 { 492 compatible = "marvell,armada-380-xor", "marvell,orion-xor"; 493 reg = <0x60800 0x100 494 0x60a00 0x100>; 495 clocks = <&gateclk 22>; 496 status = "okay"; 497 498 xor00 { 499 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 500 dmacap,memcpy; 501 dmacap,xor; 502 }; 503 xor01 { 504 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 505 dmacap,memcpy; 506 dmacap,xor; 507 dmacap,memset; 508 }; 509 }; 510 511 xor1: xor@60900 { 512 compatible = "marvell,armada-380-xor", "marvell,orion-xor"; 513 reg = <0x60900 0x100 514 0x60b00 0x100>; 515 clocks = <&gateclk 28>; 516 status = "okay"; 517 518 xor10 { 519 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 520 dmacap,memcpy; 521 dmacap,xor; 522 }; 523 xor11 { 524 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 525 dmacap,memcpy; 526 dmacap,xor; 527 dmacap,memset; 528 }; 529 }; 530 531 mdio: mdio@72004 { 532 #address-cells = <1>; 533 #size-cells = <0>; 534 compatible = "marvell,orion-mdio"; 535 reg = <0x72004 0x4>; 536 clocks = <&gateclk 4>; 537 }; 538 539 cesa: crypto@90000 { 540 compatible = "marvell,armada-38x-crypto"; 541 reg = <0x90000 0x10000>; 542 reg-names = "regs"; 543 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 545 clocks = <&gateclk 23>, <&gateclk 21>, 546 <&gateclk 14>, <&gateclk 16>; 547 clock-names = "cesa0", "cesa1", 548 "cesaz0", "cesaz1"; 549 marvell,crypto-srams = <&crypto_sram0>, 550 <&crypto_sram1>; 551 marvell,crypto-sram-size = <0x800>; 552 }; 553 554 rtc: rtc@a3800 { 555 compatible = "marvell,armada-380-rtc"; 556 reg = <0xa3800 0x20>, <0x184a0 0x0c>; 557 reg-names = "rtc", "rtc-soc"; 558 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 559 }; 560 561 ahci0: sata@a8000 { 562 compatible = "marvell,armada-380-ahci"; 563 reg = <0xa8000 0x2000>; 564 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 565 clocks = <&gateclk 15>; 566 status = "disabled"; 567 }; 568 569 bm: bm@c8000 { 570 compatible = "marvell,armada-380-neta-bm"; 571 reg = <0xc8000 0xac>; 572 clocks = <&gateclk 13>; 573 internal-mem = <&bm_bppi>; 574 status = "disabled"; 575 }; 576 577 ahci1: sata@e0000 { 578 compatible = "marvell,armada-380-ahci"; 579 reg = <0xe0000 0x2000>; 580 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&gateclk 30>; 582 status = "disabled"; 583 }; 584 585 coredivclk: clock@e4250 { 586 compatible = "marvell,armada-380-corediv-clock"; 587 reg = <0xe4250 0xc>; 588 #clock-cells = <1>; 589 clocks = <&mainpll>; 590 clock-output-names = "nand"; 591 }; 592 593 thermal: thermal@e8078 { 594 compatible = "marvell,armada380-thermal"; 595 reg = <0xe4078 0x4>, <0xe4070 0x8>; 596 status = "okay"; 597 }; 598 599 nand_controller: nand-controller@d0000 { 600 compatible = "marvell,armada370-nand-controller"; 601 reg = <0xd0000 0x54>; 602 #address-cells = <1>; 603 #size-cells = <0>; 604 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 605 clocks = <&coredivclk 0>; 606 status = "disabled"; 607 }; 608 609 sdhci: sdhci@d8000 { 610 compatible = "marvell,armada-380-sdhci"; 611 reg-names = "sdhci", "mbus", "conf-sdio3"; 612 reg = <0xd8000 0x1000>, 613 <0xdc000 0x100>, 614 <0x18454 0x4>; 615 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 616 clocks = <&gateclk 17>; 617 mrvl,clk-delay-cycles = <0x1F>; 618 status = "disabled"; 619 }; 620 621 usb3_0: usb3@f0000 { 622 compatible = "marvell,armada-380-xhci"; 623 reg = <0xf0000 0x4000>,<0xf4000 0x4000>; 624 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 625 clocks = <&gateclk 9>; 626 status = "disabled"; 627 }; 628 629 usb3_1: usb3@f8000 { 630 compatible = "marvell,armada-380-xhci"; 631 reg = <0xf8000 0x4000>,<0xfc000 0x4000>; 632 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 633 clocks = <&gateclk 10>; 634 status = "disabled"; 635 }; 636 }; 637 638 crypto_sram0: sa-sram0 { 639 compatible = "mmio-sram"; 640 reg = <MBUS_ID(0x09, 0x19) 0 0x800>; 641 clocks = <&gateclk 23>; 642 #address-cells = <1>; 643 #size-cells = <1>; 644 ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>; 645 }; 646 647 crypto_sram1: sa-sram1 { 648 compatible = "mmio-sram"; 649 reg = <MBUS_ID(0x09, 0x15) 0 0x800>; 650 clocks = <&gateclk 21>; 651 #address-cells = <1>; 652 #size-cells = <1>; 653 ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>; 654 }; 655 656 bm_bppi: bm-bppi { 657 compatible = "mmio-sram"; 658 reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>; 659 ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>; 660 #address-cells = <1>; 661 #size-cells = <1>; 662 clocks = <&gateclk 13>; 663 no-memory-wc; 664 status = "disabled"; 665 }; 666 667 spi0: spi@10600 { 668 compatible = "marvell,armada-380-spi", 669 "marvell,orion-spi"; 670 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>; 671 #address-cells = <1>; 672 #size-cells = <0>; 673 cell-index = <0>; 674 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 675 clocks = <&coreclk 0>; 676 status = "disabled"; 677 }; 678 679 spi1: spi@10680 { 680 compatible = "marvell,armada-380-spi", 681 "marvell,orion-spi"; 682 reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>; 683 #address-cells = <1>; 684 #size-cells = <0>; 685 cell-index = <1>; 686 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 687 clocks = <&coreclk 0>; 688 status = "disabled"; 689 }; 690 }; 691 692 clocks { 693 /* 1 GHz fixed main PLL */ 694 mainpll: mainpll { 695 compatible = "fixed-clock"; 696 #clock-cells = <0>; 697 clock-frequency = <1000000000>; 698 }; 699 700 /* 25 MHz reference crystal */ 701 refclk: oscillator { 702 compatible = "fixed-clock"; 703 #clock-cells = <0>; 704 clock-frequency = <25000000>; 705 }; 706 }; 707 };
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