armada-xp-98dx3236.dtsi

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    1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
    2 /*
    3  * Device Tree Include file for Marvell 98dx3236 family SoC
    4  *
    5  * Copyright (C) 2016 Allied Telesis Labs
    6  *
    7  * Contains definitions specific to the 98dx3236 SoC that are not
    8  * common to all Armada XP SoCs.
    9  */
   10 
   11 #include "armada-370-xp.dtsi"
   12 
   13 / {
   14         #address-cells = <2>;
   15         #size-cells = <2>;
   16 
   17         model = "Marvell 98DX3236 SoC";
   18         compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
   19 
   20         aliases {
   21                 gpio0 = &gpio0;
   22                 gpio1 = &gpio1;
   23                 gpio2 = &gpio2;
   24         };
   25 
   26         cpus {
   27                 #address-cells = <1>;
   28                 #size-cells = <0>;
   29                 enable-method = "marvell,98dx3236-smp";
   30 
   31                 cpu@0 {
   32                         device_type = "cpu";
   33                         compatible = "marvell,sheeva-v7";
   34                         reg = <0>;
   35                         clocks = <&cpuclk 0>;
   36                         clock-latency = <1000000>;
   37                 };
   38         };
   39 
   40         soc {
   41                 compatible = "marvell,armadaxp-mbus", "simple-bus";
   42 
   43                 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
   44                           MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
   45                           MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
   46                           MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
   47                           MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
   48 
   49                 bootrom {
   50                         compatible = "marvell,bootrom";
   51                         reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
   52                 };
   53 
   54                 /*
   55                  * 98DX3236 has 1 x1 PCIe unit Gen2.0
   56                  */
   57                 pciec: pcie@82000000 {
   58                         compatible = "marvell,armada-xp-pcie";
   59                         status = "disabled";
   60                         device_type = "pci";
   61 
   62                         #address-cells = <3>;
   63                         #size-cells = <2>;
   64 
   65                         msi-parent = <&mpic>;
   66                         bus-range = <0x00 0xff>;
   67 
   68                         ranges =
   69                                <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
   70                                 0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
   71                                 0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */>;
   72 
   73                         pcie1: pcie@1,0 {
   74                                 device_type = "pci";
   75                                 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
   76                                 reg = <0x0800 0 0 0 0>;
   77                                 #address-cells = <3>;
   78                                 #size-cells = <2>;
   79                                 #interrupt-cells = <1>;
   80                                 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
   81                                           0x81000000 0 0 0x81000000 0x1 0 1 0>;
   82                                 bus-range = <0x00 0xff>;
   83                                 interrupt-map-mask = <0 0 0 0>;
   84                                 interrupt-map = <0 0 0 0 &mpic 58>;
   85                                 marvell,pcie-port = <0>;
   86                                 marvell,pcie-lane = <0>;
   87                                 clocks = <&gateclk 5>;
   88                                 status = "disabled";
   89                         };
   90                 };
   91 
   92                 internal-regs {
   93                         sdramc: sdramc@1400 {
   94                                 compatible = "marvell,armada-xp-sdram-controller";
   95                                 reg = <0x1400 0x500>;
   96                         };
   97 
   98                         L2: l2-cache@8000 {
   99                                 compatible = "marvell,aurora-system-cache";
  100                                 reg = <0x08000 0x1000>;
  101                                 cache-id-part = <0x100>;
  102                                 cache-level = <2>;
  103                                 cache-unified;
  104                                 wt-override;
  105                         };
  106 
  107                         gpio0: gpio@18100 {
  108                                 compatible = "marvell,orion-gpio";
  109                                 reg = <0x18100 0x40>;
  110                                 ngpios = <32>;
  111                                 gpio-controller;
  112                                 #gpio-cells = <2>;
  113                                 interrupt-controller;
  114                                 #interrupt-cells = <2>;
  115                                 interrupts = <82>, <83>, <84>, <85>;
  116                         };
  117 
  118                         /* does not exist */
  119                         gpio1: gpio@18140 {
  120                                 compatible = "marvell,orion-gpio";
  121                                 reg = <0x18140 0x40>;
  122                                 status = "disabled";
  123                         };
  124 
  125                         gpio2: gpio@18180 { /* rework some properties */
  126                                 compatible = "marvell,orion-gpio";
  127                                 reg = <0x18180 0x40>;
  128                                 ngpios = <1>; /* only gpio #32 */
  129                                 gpio-controller;
  130                                 #gpio-cells = <2>;
  131                                 interrupt-controller;
  132                                 #interrupt-cells = <2>;
  133                                 interrupts = <87>;
  134                         };
  135 
  136                         systemc: system-controller@18200 {
  137                                 compatible = "marvell,armada-370-xp-system-controller";
  138                                 reg = <0x18200 0x500>;
  139                         };
  140 
  141                         gateclk: clock-gating-control@18220 {
  142                                 compatible = "marvell,mv98dx3236-gating-clock";
  143                                 reg = <0x18220 0x4>;
  144                                 clocks = <&coreclk 0>;
  145                                 #clock-cells = <1>;
  146                         };
  147 
  148                         cpuclk: clock-complex@18700 {
  149                                 #clock-cells = <1>;
  150                                 compatible = "marvell,mv98dx3236-cpu-clock";
  151                                 reg = <0x18700 0x24>, <0x1c054 0x10>;
  152                                 clocks = <&coreclk 1>;
  153                         };
  154 
  155                         corediv-clock@18740 {
  156                                 status = "disabled";
  157                         };
  158 
  159                         cpu-config@21000 {
  160                                 compatible = "marvell,armada-xp-cpu-config";
  161                                 reg = <0x21000 0x8>;
  162                         };
  163 
  164                         ethernet@70000 {
  165                                 compatible = "marvell,armada-xp-neta";
  166                         };
  167 
  168                         ethernet@74000 {
  169                                 compatible = "marvell,armada-xp-neta";
  170                         };
  171 
  172                         xor1: xor@f0800 {
  173                                 compatible = "marvell,orion-xor";
  174                                 reg = <0xf0800 0x100
  175                                        0xf0a00 0x100>;
  176                                 clocks = <&gateclk 22>;
  177                                 status = "okay";
  178 
  179                                 xor10 {
  180                                         interrupts = <51>;
  181                                         dmacap,memcpy;
  182                                         dmacap,xor;
  183                                 };
  184                                 xor11 {
  185                                         interrupts = <52>;
  186                                         dmacap,memcpy;
  187                                         dmacap,xor;
  188                                         dmacap,memset;
  189                                 };
  190                         };
  191 
  192                         nand_controller: nand-controller@d0000 {
  193                                 clocks = <&dfx_coredivclk 0>;
  194                         };
  195 
  196                         xor0: xor@f0900 {
  197                                 compatible = "marvell,orion-xor";
  198                                 reg = <0xF0900 0x100
  199                                        0xF0B00 0x100>;
  200                                 clocks = <&gateclk 28>;
  201                                 status = "okay";
  202 
  203                                 xor00 {
  204                                         interrupts = <94>;
  205                                         dmacap,memcpy;
  206                                         dmacap,xor;
  207                                 };
  208                                 xor01 {
  209                                         interrupts = <95>;
  210                                         dmacap,memcpy;
  211                                         dmacap,xor;
  212                                         dmacap,memset;
  213                                 };
  214                         };
  215                 };
  216 
  217                 dfx: dfx-server@ac000000 {
  218                         compatible = "marvell,dfx-server", "simple-bus";
  219                         #address-cells = <1>;
  220                         #size-cells = <1>;
  221                         ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
  222                         reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
  223 
  224                         coreclk: mvebu-sar@f8204 {
  225                                 compatible = "marvell,mv98dx3236-core-clock";
  226                                 reg = <0xf8204 0x4>;
  227                                 #clock-cells = <1>;
  228                         };
  229 
  230                         dfx_coredivclk: corediv-clock@f8268 {
  231                                 compatible = "marvell,mv98dx3236-corediv-clock";
  232                                 reg = <0xf8268 0xc>;
  233                                 #clock-cells = <1>;
  234                                 clocks = <&mainpll>;
  235                                 clock-output-names = "nand";
  236                         };
  237                 };
  238 
  239                 switch: switch@a8000000 {
  240                         compatible = "simple-bus";
  241                         #address-cells = <1>;
  242                         #size-cells = <1>;
  243                         ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
  244 
  245                         pp0: packet-processor@0 {
  246                                 compatible = "marvell,prestera-98dx3236", "marvell,prestera";
  247                                 reg = <0 0x4000000>;
  248                                 interrupts = <33>, <34>, <35>;
  249                                 dfx = <&dfx>;
  250                         };
  251                 };
  252         };
  253 
  254         clocks {
  255                 /* 25 MHz reference crystal */
  256                 refclk: oscillator {
  257                         compatible = "fixed-clock";
  258                         #clock-cells = <0>;
  259                         clock-frequency = <25000000>;
  260                 };
  261         };
  262 };
  263 
  264 &i2c0 {
  265         compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
  266         reg = <0x11000 0x100>;
  267         pinctrl-names = "default";
  268         pinctrl-0 = <&i2c0_pins>;
  269 };
  270 
  271 &mpic {
  272         reg = <0x20a00 0x2d0>, <0x21070 0x58>;
  273 };
  274 
  275 &rtc {
  276         status = "disabled";
  277 };
  278 
  279 &timer {
  280         compatible = "marvell,armada-xp-timer";
  281         clocks = <&coreclk 2>, <&refclk>;
  282         clock-names = "nbclk", "fixed";
  283 };
  284 
  285 &watchdog {
  286         compatible = "marvell,armada-xp-wdt";
  287         clocks = <&coreclk 2>, <&refclk>;
  288         clock-names = "nbclk", "fixed";
  289 };
  290 
  291 &cpurst {
  292         reg = <0x20800 0x20>;
  293 };
  294 
  295 &usb0 {
  296         clocks = <&gateclk 18>;
  297 };
  298 
  299 &usb1 {
  300         clocks = <&gateclk 19>;
  301 };
  302 
  303 &pinctrl {
  304         compatible = "marvell,98dx3236-pinctrl";
  305 
  306         nand_pins: nand-pins {
  307                 marvell,pins = "mpp20", "mpp21", "mpp22",
  308                                "mpp23", "mpp24", "mpp25",
  309                                "mpp26", "mpp27", "mpp28",
  310                                "mpp29", "mpp30";
  311                 marvell,function = "dev";
  312         };
  313 
  314         nand_rb: nand-rb {
  315                 marvell,pins = "mpp19";
  316                 marvell,function = "nand";
  317         };
  318 
  319         spi0_pins: spi0-pins {
  320                 marvell,pins = "mpp0", "mpp1",
  321                                "mpp2", "mpp3";
  322                 marvell,function = "spi0";
  323         };
  324 
  325         i2c0_pins: i2c-pins-0 {
  326                 marvell,pins = "mpp14", "mpp15";
  327                 marvell,function = "i2c0";
  328         };
  329 };
  330 
  331 &spi0 {
  332         compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
  333         pinctrl-0 = <&spi0_pins>;
  334         pinctrl-names = "default";
  335 };
  336 
  337 &sdio {
  338         status = "disabled";
  339 };
  340 
  341 &uart0 {
  342         compatible = "marvell,armada-38x-uart";
  343 };
  344 
  345 &uart1 {
  346         compatible = "marvell,armada-38x-uart";
  347 };
  348
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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm/armada-xp-98dx3236.dtsi

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sys/contrib/device-tree/src/arm/armada-xp-98dx3236.dtsi
