Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/armada-xp-mv78460.dtsi
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1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Device Tree Include file for Marvell Armada XP family SoC 4 * 5 * Copyright (C) 2012 Marvell 6 * 7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8 * 9 * Contains definitions specific to the Armada XP MV78460 SoC that are not 10 * common to all Armada XP SoCs. 11 */ 12 13 #include "armada-xp.dtsi" 14 15 / { 16 model = "Marvell Armada XP MV78460 SoC"; 17 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; 18 19 aliases { 20 gpio0 = &gpio0; 21 gpio1 = &gpio1; 22 gpio2 = &gpio2; 23 }; 24 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 enable-method = "marvell,armada-xp-smp"; 30 31 cpu@0 { 32 device_type = "cpu"; 33 compatible = "marvell,sheeva-v7"; 34 reg = <0>; 35 clocks = <&cpuclk 0>; 36 clock-latency = <1000000>; 37 }; 38 39 cpu@1 { 40 device_type = "cpu"; 41 compatible = "marvell,sheeva-v7"; 42 reg = <1>; 43 clocks = <&cpuclk 1>; 44 clock-latency = <1000000>; 45 }; 46 47 cpu@2 { 48 device_type = "cpu"; 49 compatible = "marvell,sheeva-v7"; 50 reg = <2>; 51 clocks = <&cpuclk 2>; 52 clock-latency = <1000000>; 53 }; 54 55 cpu@3 { 56 device_type = "cpu"; 57 compatible = "marvell,sheeva-v7"; 58 reg = <3>; 59 clocks = <&cpuclk 3>; 60 clock-latency = <1000000>; 61 }; 62 }; 63 64 soc { 65 /* 66 * MV78460 has 4 PCIe units Gen2.0: Two units can be 67 * configured as x4 or quad x1 lanes. Two units are 68 * x4/x1. 69 */ 70 pciec: pcie@82000000 { 71 compatible = "marvell,armada-xp-pcie"; 72 status = "disabled"; 73 device_type = "pci"; 74 75 #address-cells = <3>; 76 #size-cells = <2>; 77 78 msi-parent = <&mpic>; 79 bus-range = <0x00 0xff>; 80 81 ranges = 82 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 83 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ 84 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 85 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ 86 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ 87 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ 88 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */ 89 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ 90 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ 91 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ 92 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 93 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 94 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ 95 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ 96 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ 97 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ 98 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ 99 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ 100 101 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ 102 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ 103 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ 104 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ 105 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ 106 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ 107 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ 108 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ 109 110 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ 111 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */ 112 113 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ 114 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; 115 116 pcie1: pcie@1,0 { 117 device_type = "pci"; 118 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 119 reg = <0x0800 0 0 0 0>; 120 #address-cells = <3>; 121 #size-cells = <2>; 122 #interrupt-cells = <1>; 123 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 124 0x81000000 0 0 0x81000000 0x1 0 1 0>; 125 bus-range = <0x00 0xff>; 126 interrupt-map-mask = <0 0 0 0>; 127 interrupt-map = <0 0 0 0 &mpic 58>; 128 marvell,pcie-port = <0>; 129 marvell,pcie-lane = <0>; 130 clocks = <&gateclk 5>; 131 status = "disabled"; 132 }; 133 134 pcie2: pcie@2,0 { 135 device_type = "pci"; 136 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; 137 reg = <0x1000 0 0 0 0>; 138 #address-cells = <3>; 139 #size-cells = <2>; 140 #interrupt-cells = <1>; 141 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 142 0x81000000 0 0 0x81000000 0x2 0 1 0>; 143 bus-range = <0x00 0xff>; 144 interrupt-map-mask = <0 0 0 0>; 145 interrupt-map = <0 0 0 0 &mpic 59>; 146 marvell,pcie-port = <0>; 147 marvell,pcie-lane = <1>; 148 clocks = <&gateclk 6>; 149 status = "disabled"; 150 }; 151 152 pcie3: pcie@3,0 { 153 device_type = "pci"; 154 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; 155 reg = <0x1800 0 0 0 0>; 156 #address-cells = <3>; 157 #size-cells = <2>; 158 #interrupt-cells = <1>; 159 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 160 0x81000000 0 0 0x81000000 0x3 0 1 0>; 161 bus-range = <0x00 0xff>; 162 interrupt-map-mask = <0 0 0 0>; 163 interrupt-map = <0 0 0 0 &mpic 60>; 164 marvell,pcie-port = <0>; 165 marvell,pcie-lane = <2>; 166 clocks = <&gateclk 7>; 167 status = "disabled"; 168 }; 169 170 pcie4: pcie@4,0 { 171 device_type = "pci"; 172 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; 173 reg = <0x2000 0 0 0 0>; 174 #address-cells = <3>; 175 #size-cells = <2>; 176 #interrupt-cells = <1>; 177 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 178 0x81000000 0 0 0x81000000 0x4 0 1 0>; 179 bus-range = <0x00 0xff>; 180 interrupt-map-mask = <0 0 0 0>; 181 interrupt-map = <0 0 0 0 &mpic 61>; 182 marvell,pcie-port = <0>; 183 marvell,pcie-lane = <3>; 184 clocks = <&gateclk 8>; 185 status = "disabled"; 186 }; 187 188 pcie5: pcie@5,0 { 189 device_type = "pci"; 190 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; 191 reg = <0x2800 0 0 0 0>; 192 #address-cells = <3>; 193 #size-cells = <2>; 194 #interrupt-cells = <1>; 195 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 196 0x81000000 0 0 0x81000000 0x5 0 1 0>; 197 bus-range = <0x00 0xff>; 198 interrupt-map-mask = <0 0 0 0>; 199 interrupt-map = <0 0 0 0 &mpic 62>; 200 marvell,pcie-port = <1>; 201 marvell,pcie-lane = <0>; 202 clocks = <&gateclk 9>; 203 status = "disabled"; 204 }; 205 206 pcie6: pcie@6,0 { 207 device_type = "pci"; 208 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; 209 reg = <0x3000 0 0 0 0>; 210 #address-cells = <3>; 211 #size-cells = <2>; 212 #interrupt-cells = <1>; 213 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 214 0x81000000 0 0 0x81000000 0x6 0 1 0>; 215 bus-range = <0x00 0xff>; 216 interrupt-map-mask = <0 0 0 0>; 217 interrupt-map = <0 0 0 0 &mpic 63>; 218 marvell,pcie-port = <1>; 219 marvell,pcie-lane = <1>; 220 clocks = <&gateclk 10>; 221 status = "disabled"; 222 }; 223 224 pcie7: pcie@7,0 { 225 device_type = "pci"; 226 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; 227 reg = <0x3800 0 0 0 0>; 228 #address-cells = <3>; 229 #size-cells = <2>; 230 #interrupt-cells = <1>; 231 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 232 0x81000000 0 0 0x81000000 0x7 0 1 0>; 233 bus-range = <0x00 0xff>; 234 interrupt-map-mask = <0 0 0 0>; 235 interrupt-map = <0 0 0 0 &mpic 64>; 236 marvell,pcie-port = <1>; 237 marvell,pcie-lane = <2>; 238 clocks = <&gateclk 11>; 239 status = "disabled"; 240 }; 241 242 pcie8: pcie@8,0 { 243 device_type = "pci"; 244 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; 245 reg = <0x4000 0 0 0 0>; 246 #address-cells = <3>; 247 #size-cells = <2>; 248 #interrupt-cells = <1>; 249 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 250 0x81000000 0 0 0x81000000 0x8 0 1 0>; 251 bus-range = <0x00 0xff>; 252 interrupt-map-mask = <0 0 0 0>; 253 interrupt-map = <0 0 0 0 &mpic 65>; 254 marvell,pcie-port = <1>; 255 marvell,pcie-lane = <3>; 256 clocks = <&gateclk 12>; 257 status = "disabled"; 258 }; 259 260 pcie9: pcie@9,0 { 261 device_type = "pci"; 262 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; 263 reg = <0x4800 0 0 0 0>; 264 #address-cells = <3>; 265 #size-cells = <2>; 266 #interrupt-cells = <1>; 267 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 268 0x81000000 0 0 0x81000000 0x9 0 1 0>; 269 bus-range = <0x00 0xff>; 270 interrupt-map-mask = <0 0 0 0>; 271 interrupt-map = <0 0 0 0 &mpic 99>; 272 marvell,pcie-port = <2>; 273 marvell,pcie-lane = <0>; 274 clocks = <&gateclk 26>; 275 status = "disabled"; 276 }; 277 278 pcie10: pcie@a,0 { 279 device_type = "pci"; 280 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; 281 reg = <0x5000 0 0 0 0>; 282 #address-cells = <3>; 283 #size-cells = <2>; 284 #interrupt-cells = <1>; 285 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 286 0x81000000 0 0 0x81000000 0xa 0 1 0>; 287 bus-range = <0x00 0xff>; 288 interrupt-map-mask = <0 0 0 0>; 289 interrupt-map = <0 0 0 0 &mpic 103>; 290 marvell,pcie-port = <3>; 291 marvell,pcie-lane = <0>; 292 clocks = <&gateclk 27>; 293 status = "disabled"; 294 }; 295 }; 296 297 internal-regs { 298 gpio0: gpio@18100 { 299 compatible = "marvell,armada-370-gpio", 300 "marvell,orion-gpio"; 301 reg = <0x18100 0x40>, <0x181c0 0x08>; 302 reg-names = "gpio", "pwm"; 303 ngpios = <32>; 304 gpio-controller; 305 #gpio-cells = <2>; 306 #pwm-cells = <2>; 307 interrupt-controller; 308 #interrupt-cells = <2>; 309 interrupts = <82>, <83>, <84>, <85>; 310 clocks = <&coreclk 0>; 311 }; 312 313 gpio1: gpio@18140 { 314 compatible = "marvell,armada-370-gpio", 315 "marvell,orion-gpio"; 316 reg = <0x18140 0x40>, <0x181c8 0x08>; 317 reg-names = "gpio", "pwm"; 318 ngpios = <32>; 319 gpio-controller; 320 #gpio-cells = <2>; 321 #pwm-cells = <2>; 322 interrupt-controller; 323 #interrupt-cells = <2>; 324 interrupts = <87>, <88>, <89>, <90>; 325 clocks = <&coreclk 0>; 326 }; 327 328 gpio2: gpio@18180 { 329 compatible = "marvell,armada-370-gpio", 330 "marvell,orion-gpio"; 331 reg = <0x18180 0x40>; 332 ngpios = <3>; 333 gpio-controller; 334 #gpio-cells = <2>; 335 interrupt-controller; 336 #interrupt-cells = <2>; 337 interrupts = <91>; 338 }; 339 340 eth3: ethernet@34000 { 341 compatible = "marvell,armada-xp-neta"; 342 reg = <0x34000 0x4000>; 343 interrupts = <14>; 344 clocks = <&gateclk 1>; 345 status = "disabled"; 346 }; 347 }; 348 }; 349 }; 350 351 &pinctrl { 352 compatible = "marvell,mv78460-pinctrl"; 353 };
Cache object: 2daaa0c0cafb7099ddb09d4477bfedd6
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