aspeed-g5.dtsi

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    1 // SPDX-License-Identifier: GPL-2.0+
    2 #include <dt-bindings/clock/aspeed-clock.h>
    3 #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
    4 
    5 / {
    6         model = "Aspeed BMC";
    7         compatible = "aspeed,ast2500";
    8         #address-cells = <1>;
    9         #size-cells = <1>;
   10         interrupt-parent = <&vic>;
   11 
   12         aliases {
   13                 i2c0 = &i2c0;
   14                 i2c1 = &i2c1;
   15                 i2c2 = &i2c2;
   16                 i2c3 = &i2c3;
   17                 i2c4 = &i2c4;
   18                 i2c5 = &i2c5;
   19                 i2c6 = &i2c6;
   20                 i2c7 = &i2c7;
   21                 i2c8 = &i2c8;
   22                 i2c9 = &i2c9;
   23                 i2c10 = &i2c10;
   24                 i2c11 = &i2c11;
   25                 i2c12 = &i2c12;
   26                 i2c13 = &i2c13;
   27                 serial0 = &uart1;
   28                 serial1 = &uart2;
   29                 serial2 = &uart3;
   30                 serial3 = &uart4;
   31                 serial4 = &uart5;
   32                 serial5 = &vuart;
   33         };
   34 
   35         cpus {
   36                 #address-cells = <1>;
   37                 #size-cells = <0>;
   38 
   39                 cpu@0 {
   40                         compatible = "arm,arm1176jzf-s";
   41                         device_type = "cpu";
   42                         reg = <0>;
   43                 };
   44         };
   45 
   46         memory@80000000 {
   47                 device_type = "memory";
   48                 reg = <0x80000000 0>;
   49         };
   50 
   51         ahb {
   52                 compatible = "simple-bus";
   53                 #address-cells = <1>;
   54                 #size-cells = <1>;
   55                 ranges;
   56 
   57                 fmc: spi@1e620000 {
   58                         reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
   59                         #address-cells = <1>;
   60                         #size-cells = <0>;
   61                         compatible = "aspeed,ast2500-fmc";
   62                         clocks = <&syscon ASPEED_CLK_AHB>;
   63                         status = "disabled";
   64                         interrupts = <19>;
   65                         flash@0 {
   66                                 reg = < 0 >;
   67                                 compatible = "jedec,spi-nor";
   68                                 spi-max-frequency = <50000000>;
   69                                 spi-rx-bus-width = <2>;
   70                                 status = "disabled";
   71                         };
   72                         flash@1 {
   73                                 reg = < 1 >;
   74                                 compatible = "jedec,spi-nor";
   75                                 spi-max-frequency = <50000000>;
   76                                 spi-rx-bus-width = <2>;
   77                                 status = "disabled";
   78                         };
   79                         flash@2 {
   80                                 reg = < 2 >;
   81                                 compatible = "jedec,spi-nor";
   82                                 spi-max-frequency = <50000000>;
   83                                 spi-rx-bus-width = <2>;
   84                                 status = "disabled";
   85                         };
   86                 };
   87 
   88                 spi1: spi@1e630000 {
   89                         reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>;
   90                         #address-cells = <1>;
   91                         #size-cells = <0>;
   92                         compatible = "aspeed,ast2500-spi";
   93                         clocks = <&syscon ASPEED_CLK_AHB>;
   94                         status = "disabled";
   95                         flash@0 {
   96                                 reg = < 0 >;
   97                                 compatible = "jedec,spi-nor";
   98                                 spi-max-frequency = <50000000>;
   99                                 spi-rx-bus-width = <2>;
  100                                 status = "disabled";
  101                         };
  102                         flash@1 {
  103                                 reg = < 1 >;
  104                                 compatible = "jedec,spi-nor";
  105                                 spi-max-frequency = <50000000>;
  106                                 spi-rx-bus-width = <2>;
  107                                 status = "disabled";
  108                         };
  109                 };
  110 
  111                 spi2: spi@1e631000 {
  112                         reg = <0x1e631000 0xc4>, <0x38000000 0x08000000>;
  113                         #address-cells = <1>;
  114                         #size-cells = <0>;
  115                         compatible = "aspeed,ast2500-spi";
  116                         clocks = <&syscon ASPEED_CLK_AHB>;
  117                         status = "disabled";
  118                         flash@0 {
  119                                 reg = < 0 >;
  120                                 compatible = "jedec,spi-nor";
  121                                 spi-max-frequency = <50000000>;
  122                                 spi-rx-bus-width = <2>;
  123                                 status = "disabled";
  124                         };
  125                         flash@1 {
  126                                 reg = < 1 >;
  127                                 compatible = "jedec,spi-nor";
  128                                 spi-max-frequency = <50000000>;
  129                                 spi-rx-bus-width = <2>;
  130                                 status = "disabled";
  131                         };
  132                 };
  133 
  134                 vic: interrupt-controller@1e6c0080 {
  135                         compatible = "aspeed,ast2400-vic";
  136                         interrupt-controller;
  137                         #interrupt-cells = <1>;
  138                         valid-sources = <0xfefff7ff 0x0807ffff>;
  139                         reg = <0x1e6c0080 0x80>;
  140                 };
  141 
  142                 cvic: copro-interrupt-controller@1e6c2000 {
  143                         compatible = "aspeed,ast2500-cvic", "aspeed-cvic";
  144                         valid-sources = <0xffffffff>;
  145                         copro-sw-interrupts = <1>;
  146                         reg = <0x1e6c2000 0x80>;
  147                 };
  148 
  149                 mac0: ethernet@1e660000 {
  150                         compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
  151                         reg = <0x1e660000 0x180>;
  152                         interrupts = <2>;
  153                         clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
  154                         status = "disabled";
  155                 };
  156 
  157                 mac1: ethernet@1e680000 {
  158                         compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
  159                         reg = <0x1e680000 0x180>;
  160                         interrupts = <3>;
  161                         clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
  162                         status = "disabled";
  163                 };
  164 
  165                 ehci0: usb@1e6a1000 {
  166                         compatible = "aspeed,ast2500-ehci", "generic-ehci";
  167                         reg = <0x1e6a1000 0x100>;
  168                         interrupts = <5>;
  169                         clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
  170                         pinctrl-names = "default";
  171                         pinctrl-0 = <&pinctrl_usb2ah_default>;
  172                         status = "disabled";
  173                 };
  174 
  175                 ehci1: usb@1e6a3000 {
  176                         compatible = "aspeed,ast2500-ehci", "generic-ehci";
  177                         reg = <0x1e6a3000 0x100>;
  178                         interrupts = <13>;
  179                         clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
  180                         pinctrl-names = "default";
  181                         pinctrl-0 = <&pinctrl_usb2bh_default>;
  182                         status = "disabled";
  183                 };
  184 
  185                 uhci: usb@1e6b0000 {
  186                         compatible = "aspeed,ast2500-uhci", "generic-uhci";
  187                         reg = <0x1e6b0000 0x100>;
  188                         interrupts = <14>;
  189                         #ports = <2>;
  190                         clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
  191                         status = "disabled";
  192                         /*
  193                          * No default pinmux, it will follow EHCI, use an explicit pinmux
  194                          * override if you don't enable EHCI
  195                          */
  196                 };
  197 
  198                 vhub: usb-vhub@1e6a0000 {
  199                         compatible = "aspeed,ast2500-usb-vhub";
  200                         reg = <0x1e6a0000 0x300>;
  201                         interrupts = <5>;
  202                         clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
  203                         aspeed,vhub-downstream-ports = <5>;
  204                         aspeed,vhub-generic-endpoints = <15>;
  205                         pinctrl-names = "default";
  206                         pinctrl-0 = <&pinctrl_usb2ad_default>;
  207                         status = "disabled";
  208                 };
  209 
  210                 apb {
  211                         compatible = "simple-bus";
  212                         #address-cells = <1>;
  213                         #size-cells = <1>;
  214                         ranges;
  215 
  216                         edac: memory-controller@1e6e0000 {
  217                                 compatible = "aspeed,ast2500-sdram-edac";
  218                                 reg = <0x1e6e0000 0x174>;
  219                                 interrupts = <0>;
  220                                 status = "disabled";
  221                         };
  222 
  223                         syscon: syscon@1e6e2000 {
  224                                 compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
  225                                 reg = <0x1e6e2000 0x1a8>;
  226                                 #address-cells = <1>;
  227                                 #size-cells = <1>;
  228                                 ranges = <0 0x1e6e2000 0x1000>;
  229                                 #clock-cells = <1>;
  230                                 #reset-cells = <1>;
  231 
  232                                 scu_ic: interrupt-controller@18 {
  233                                         #interrupt-cells = <1>;
  234                                         compatible = "aspeed,ast2500-scu-ic";
  235                                         reg = <0x18 0x4>;
  236                                         interrupts = <21>;
  237                                         interrupt-controller;
  238                                 };
  239 
  240                                 p2a: p2a-control@2c {
  241                                         compatible = "aspeed,ast2500-p2a-ctrl";
  242                                         reg = <0x2c 0x4>;
  243                                         status = "disabled";
  244                                 };
  245 
  246                                 silicon-id@7c {
  247                                         compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id";
  248                                         reg = <0x7c 0x4 0x150 0x8>;
  249                                 };
  250 
  251                                 pinctrl: pinctrl@80 {
  252                                         compatible = "aspeed,ast2500-pinctrl";
  253                                         reg = <0x80 0x18>, <0xa0 0x10>;
  254                                         aspeed,external-nodes = <&gfx>, <&lhc>;
  255                                 };
  256                         };
  257 
  258                         rng: hwrng@1e6e2078 {
  259                                 compatible = "timeriomem_rng";
  260                                 reg = <0x1e6e2078 0x4>;
  261                                 period = <1>;
  262                                 quality = <100>;
  263                         };
  264 
  265                         gfx: display@1e6e6000 {
  266                                 compatible = "aspeed,ast2500-gfx", "syscon";
  267                                 reg = <0x1e6e6000 0x1000>;
  268                                 reg-io-width = <4>;
  269                                 clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
  270                                 resets = <&syscon ASPEED_RESET_CRT1>;
  271                                 syscon = <&syscon>;
  272                                 status = "disabled";
  273                                 interrupts = <0x19>;
  274                         };
  275 
  276                         xdma: xdma@1e6e7000 {
  277                                 compatible = "aspeed,ast2500-xdma";
  278                                 reg = <0x1e6e7000 0x100>;
  279                                 clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
  280                                 resets = <&syscon ASPEED_RESET_XDMA>;
  281                                 interrupts-extended = <&vic 6>, <&scu_ic ASPEED_AST2500_SCU_IC_PCIE_RESET_LO_TO_HI>;
  282                                 aspeed,pcie-device = "bmc";
  283                                 aspeed,scu = <&syscon>;
  284                                 status = "disabled";
  285                         };
  286 
  287                         adc: adc@1e6e9000 {
  288                                 compatible = "aspeed,ast2500-adc";
  289                                 reg = <0x1e6e9000 0xb0>;
  290                                 clocks = <&syscon ASPEED_CLK_APB>;
  291                                 resets = <&syscon ASPEED_RESET_ADC>;
  292                                 #io-channel-cells = <1>;
  293                                 status = "disabled";
  294                         };
  295 
  296                         video: video@1e700000 {
  297                                 compatible = "aspeed,ast2500-video-engine";
  298                                 reg = <0x1e700000 0x1000>;
  299                                 clocks = <&syscon ASPEED_CLK_GATE_VCLK>,
  300                                          <&syscon ASPEED_CLK_GATE_ECLK>;
  301                                 clock-names = "vclk", "eclk";
  302                                 interrupts = <7>;
  303                                 status = "disabled";
  304                         };
  305 
  306                         sram: sram@1e720000 {
  307                                 compatible = "mmio-sram";
  308                                 reg = <0x1e720000 0x9000>;      // 36K
  309                         };
  310 
  311                         sdmmc: sd-controller@1e740000 {
  312                                 compatible = "aspeed,ast2500-sd-controller";
  313                                 reg = <0x1e740000 0x100>;
  314                                 #address-cells = <1>;
  315                                 #size-cells = <1>;
  316                                 ranges = <0 0x1e740000 0x10000>;
  317                                 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
  318                                 status = "disabled";
  319 
  320                                 sdhci0: sdhci@100 {
  321                                         compatible = "aspeed,ast2500-sdhci";
  322                                         reg = <0x100 0x100>;
  323                                         interrupts = <26>;
  324                                         sdhci,auto-cmd12;
  325                                         clocks = <&syscon ASPEED_CLK_SDIO>;
  326                                         status = "disabled";
  327                                 };
  328 
  329                                 sdhci1: sdhci@200 {
  330                                         compatible = "aspeed,ast2500-sdhci";
  331                                         reg = <0x200 0x100>;
  332                                         interrupts = <26>;
  333                                         sdhci,auto-cmd12;
  334                                         clocks = <&syscon ASPEED_CLK_SDIO>;
  335                                         status = "disabled";
  336                                 };
  337                         };
  338 
  339                         gpio: gpio@1e780000 {
  340                                 #gpio-cells = <2>;
  341                                 gpio-controller;
  342                                 compatible = "aspeed,ast2500-gpio";
  343                                 reg = <0x1e780000 0x200>;
  344                                 interrupts = <20>;
  345                                 gpio-ranges = <&pinctrl 0 0 232>;
  346                                 clocks = <&syscon ASPEED_CLK_APB>;
  347                                 interrupt-controller;
  348                                 #interrupt-cells = <2>;
  349                         };
  350 
  351                         sgpio: sgpio@1e780200 {
  352                                 #gpio-cells = <2>;
  353                                 compatible = "aspeed,ast2500-sgpio";
  354                                 gpio-controller;
  355                                 interrupts = <40>;
  356                                 reg = <0x1e780200 0x0100>;
  357                                 clocks = <&syscon ASPEED_CLK_APB>;
  358                                 interrupt-controller;
  359                                 bus-frequency = <12000000>;
  360                                 pinctrl-names = "default";
  361                                 pinctrl-0 = <&pinctrl_sgpm_default>;
  362                                 status = "disabled";
  363                         };
  364 
  365                         rtc: rtc@1e781000 {
  366                                 compatible = "aspeed,ast2500-rtc";
  367                                 reg = <0x1e781000 0x18>;
  368                                 status = "disabled";
  369                         };
  370 
  371                         timer: timer@1e782000 {
  372                                 /* This timer is a Faraday FTTMR010 derivative */
  373                                 compatible = "aspeed,ast2400-timer";
  374                                 reg = <0x1e782000 0x90>;
  375                                 interrupts = <16 17 18 35 36 37 38 39>;
  376                                 clocks = <&syscon ASPEED_CLK_APB>;
  377                                 clock-names = "PCLK";
  378                         };
  379 
  380                         uart1: serial@1e783000 {
  381                                 compatible = "ns16550a";
  382                                 reg = <0x1e783000 0x20>;
  383                                 reg-shift = <2>;
  384                                 interrupts = <9>;
  385                                 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
  386                                 resets = <&lpc_reset 4>;
  387                                 no-loopback-test;
  388                                 status = "disabled";
  389                         };
  390 
  391                         uart5: serial@1e784000 {
  392                                 compatible = "ns16550a";
  393                                 reg = <0x1e784000 0x20>;
  394                                 reg-shift = <2>;
  395                                 interrupts = <10>;
  396                                 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
  397                                 no-loopback-test;
  398                                 status = "disabled";
  399                         };
  400 
  401                         wdt1: watchdog@1e785000 {
  402                                 compatible = "aspeed,ast2500-wdt";
  403                                 reg = <0x1e785000 0x20>;
  404                                 clocks = <&syscon ASPEED_CLK_APB>;
  405                         };
  406 
  407                         wdt2: watchdog@1e785020 {
  408                                 compatible = "aspeed,ast2500-wdt";
  409                                 reg = <0x1e785020 0x20>;
  410                                 clocks = <&syscon ASPEED_CLK_APB>;
  411                         };
  412 
  413                         wdt3: watchdog@1e785040 {
  414                                 compatible = "aspeed,ast2500-wdt";
  415                                 reg = <0x1e785040 0x20>;
  416                                 clocks = <&syscon ASPEED_CLK_APB>;
  417                                 status = "disabled";
  418                         };
  419 
  420                         pwm_tacho: pwm-tacho-controller@1e786000 {
  421                                 compatible = "aspeed,ast2500-pwm-tacho";
  422                                 #address-cells = <1>;
  423                                 #size-cells = <0>;
  424                                 reg = <0x1e786000 0x1000>;
  425                                 clocks = <&syscon ASPEED_CLK_24M>;
  426                                 resets = <&syscon ASPEED_RESET_PWM>;
  427                                 status = "disabled";
  428                         };
  429 
  430                         vuart: serial@1e787000 {
  431                                 compatible = "aspeed,ast2500-vuart";
  432                                 reg = <0x1e787000 0x40>;
  433                                 reg-shift = <2>;
  434                                 interrupts = <8>;
  435                                 clocks = <&syscon ASPEED_CLK_APB>;
  436                                 no-loopback-test;
  437                                 status = "disabled";
  438                         };
  439 
  440                         lpc: lpc@1e789000 {
  441                                 compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon";
  442                                 reg = <0x1e789000 0x1000>;
  443                                 reg-io-width = <4>;
  444 
  445                                 #address-cells = <1>;
  446                                 #size-cells = <1>;
  447                                 ranges = <0x0 0x1e789000 0x1000>;
  448 
  449                                 kcs1: kcs@24 {
  450                                         compatible = "aspeed,ast2500-kcs-bmc-v2";
  451                                         reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
  452                                         interrupts = <8>;
  453                                         clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
  454                                         status = "disabled";
  455                                 };
  456 
  457                                 kcs2: kcs@28 {
  458                                         compatible = "aspeed,ast2500-kcs-bmc-v2";
  459                                         reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
  460                                         interrupts = <8>;
  461                                         clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
  462                                         status = "disabled";
  463                                 };
  464 
  465                                 kcs3: kcs@2c {
  466                                         compatible = "aspeed,ast2500-kcs-bmc-v2";
  467                                         reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
  468                                         interrupts = <8>;
  469                                         clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
  470                                         status = "disabled";
  471                                 };
  472 
  473                                 kcs4: kcs@114 {
  474                                         compatible = "aspeed,ast2500-kcs-bmc-v2";
  475                                         reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>;
  476                                         interrupts = <8>;
  477                                         clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
  478                                         status = "disabled";
  479                                 };
  480 
  481                                 lpc_ctrl: lpc-ctrl@80 {
  482                                         compatible = "aspeed,ast2500-lpc-ctrl";
  483                                         reg = <0x80 0x10>;
  484                                         clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
  485                                         status = "disabled";
  486                                 };
  487 
  488                                 lpc_snoop: lpc-snoop@90 {
  489                                         compatible = "aspeed,ast2500-lpc-snoop";
  490                                         reg = <0x90 0x8>;
  491                                         interrupts = <8>;
  492                                         clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
  493                                         status = "disabled";
  494                                 };
  495 
  496                                 lpc_reset: reset-controller@98 {
  497                                         compatible = "aspeed,ast2500-lpc-reset";
  498                                         reg = <0x98 0x4>;
  499                                         #reset-cells = <1>;
  500                                 };
  501 
  502                                 uart_routing: uart-routing@9c {
  503                                         compatible = "aspeed,ast2500-uart-routing";
  504                                         reg = <0x9c 0x4>;
  505                                         status = "disabled";
  506                                 };
  507 
  508                                 lhc: lhc@a0 {
  509                                         compatible = "aspeed,ast2500-lhc";
  510                                         reg = <0xa0 0x24 0xc8 0x8>;
  511                                 };
  512 
  513 
  514                                 ibt: ibt@140 {
  515                                         compatible = "aspeed,ast2500-ibt-bmc";
  516                                         reg = <0x140 0x18>;
  517                                         interrupts = <8>;
  518                                         clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
  519                                         status = "disabled";
  520                                 };
  521                         };
  522 
  523                         peci0: peci-controller@1e78b000 {
  524                                 compatible = "aspeed,ast2500-peci";
  525                                 reg = <0x1e78b000 0x60>;
  526                                 interrupts = <15>;
  527                                 clocks = <&syscon ASPEED_CLK_GATE_REFCLK>;
  528                                 resets = <&syscon ASPEED_RESET_PECI>;
  529                                 cmd-timeout-ms = <1000>;
  530                                 clock-frequency = <1000000>;
  531                                 status = "disabled";
  532                         };
  533 
  534                         uart2: serial@1e78d000 {
  535                                 compatible = "ns16550a";
  536                                 reg = <0x1e78d000 0x20>;
  537                                 reg-shift = <2>;
  538                                 interrupts = <32>;
  539                                 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
  540                                 resets = <&lpc_reset 5>;
  541                                 no-loopback-test;
  542                                 status = "disabled";
  543                         };
  544 
  545                         uart3: serial@1e78e000 {
  546                                 compatible = "ns16550a";
  547                                 reg = <0x1e78e000 0x20>;
  548                                 reg-shift = <2>;
  549                                 interrupts = <33>;
  550                                 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
  551                                 resets = <&lpc_reset 6>;
  552                                 no-loopback-test;
  553                                 status = "disabled";
  554                         };
  555 
  556                         uart4: serial@1e78f000 {
  557                                 compatible = "ns16550a";
  558                                 reg = <0x1e78f000 0x20>;
  559                                 reg-shift = <2>;
  560                                 interrupts = <34>;
  561                                 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
  562                                 resets = <&lpc_reset 7>;
  563                                 no-loopback-test;
  564                                 status = "disabled";
  565                         };
  566 
  567                         i2c: bus@1e78a000 {
  568                                 compatible = "simple-bus";
  569                                 #address-cells = <1>;
  570                                 #size-cells = <1>;
  571                                 ranges = <0 0x1e78a000 0x1000>;
  572                         };
  573                 };
  574         };
  575 };
  576 
  577 &i2c {
  578         i2c_ic: interrupt-controller@0 {
  579                 #interrupt-cells = <1>;
  580                 compatible = "aspeed,ast2500-i2c-ic";
  581                 reg = <0x0 0x40>;
  582                 interrupts = <12>;
  583                 interrupt-controller;
  584         };
  585 
  586         i2c0: i2c-bus@40 {
  587                 #address-cells = <1>;
  588                 #size-cells = <0>;
  589                 #interrupt-cells = <1>;
  590 
  591                 reg = <0x40 0x40>;
  592                 compatible = "aspeed,ast2500-i2c-bus";
  593                 clocks = <&syscon ASPEED_CLK_APB>;
  594                 resets = <&syscon ASPEED_RESET_I2C>;
  595                 bus-frequency = <100000>;
  596                 interrupts = <0>;
  597                 interrupt-parent = <&i2c_ic>;
  598                 status = "disabled";
  599                 /* Does not need pinctrl properties */
  600         };
  601 
  602         i2c1: i2c-bus@80 {
  603                 #address-cells = <1>;
  604                 #size-cells = <0>;
  605                 #interrupt-cells = <1>;
  606 
  607                 reg = <0x80 0x40>;
  608                 compatible = "aspeed,ast2500-i2c-bus";
  609                 clocks = <&syscon ASPEED_CLK_APB>;
  610                 resets = <&syscon ASPEED_RESET_I2C>;
  611                 bus-frequency = <100000>;
  612                 interrupts = <1>;
  613                 interrupt-parent = <&i2c_ic>;
  614                 status = "disabled";
  615                 /* Does not need pinctrl properties */
  616         };
  617 
  618         i2c2: i2c-bus@c0 {
  619                 #address-cells = <1>;
  620                 #size-cells = <0>;
  621                 #interrupt-cells = <1>;
  622 
  623                 reg = <0xc0 0x40>;
  624                 compatible = "aspeed,ast2500-i2c-bus";
  625                 clocks = <&syscon ASPEED_CLK_APB>;
  626                 resets = <&syscon ASPEED_RESET_I2C>;
  627                 bus-frequency = <100000>;
  628                 interrupts = <2>;
  629                 interrupt-parent = <&i2c_ic>;
  630                 pinctrl-names = "default";
  631                 pinctrl-0 = <&pinctrl_i2c3_default>;
  632                 status = "disabled";
  633         };
  634 
  635         i2c3: i2c-bus@100 {
  636                 #address-cells = <1>;
  637                 #size-cells = <0>;
  638                 #interrupt-cells = <1>;
  639 
  640                 reg = <0x100 0x40>;
  641                 compatible = "aspeed,ast2500-i2c-bus";
  642                 clocks = <&syscon ASPEED_CLK_APB>;
  643                 resets = <&syscon ASPEED_RESET_I2C>;
  644                 bus-frequency = <100000>;
  645                 interrupts = <3>;
  646                 interrupt-parent = <&i2c_ic>;
  647                 pinctrl-names = "default";
  648                 pinctrl-0 = <&pinctrl_i2c4_default>;
  649                 status = "disabled";
  650         };
  651 
  652         i2c4: i2c-bus@140 {
  653                 #address-cells = <1>;
  654                 #size-cells = <0>;
  655                 #interrupt-cells = <1>;
  656 
  657                 reg = <0x140 0x40>;
  658                 compatible = "aspeed,ast2500-i2c-bus";
  659                 clocks = <&syscon ASPEED_CLK_APB>;
  660                 resets = <&syscon ASPEED_RESET_I2C>;
  661                 bus-frequency = <100000>;
  662                 interrupts = <4>;
  663                 interrupt-parent = <&i2c_ic>;
  664                 pinctrl-names = "default";
  665                 pinctrl-0 = <&pinctrl_i2c5_default>;
  666                 status = "disabled";
  667         };
  668 
  669         i2c5: i2c-bus@180 {
  670                 #address-cells = <1>;
  671                 #size-cells = <0>;
  672                 #interrupt-cells = <1>;
  673 
  674                 reg = <0x180 0x40>;
  675                 compatible = "aspeed,ast2500-i2c-bus";
  676                 clocks = <&syscon ASPEED_CLK_APB>;
  677                 resets = <&syscon ASPEED_RESET_I2C>;
  678                 bus-frequency = <100000>;
  679                 interrupts = <5>;
  680                 interrupt-parent = <&i2c_ic>;
  681                 pinctrl-names = "default";
  682                 pinctrl-0 = <&pinctrl_i2c6_default>;
  683                 status = "disabled";
  684         };
  685 
  686         i2c6: i2c-bus@1c0 {
  687                 #address-cells = <1>;
  688                 #size-cells = <0>;
  689                 #interrupt-cells = <1>;
  690 
  691                 reg = <0x1c0 0x40>;
  692                 compatible = "aspeed,ast2500-i2c-bus";
  693                 clocks = <&syscon ASPEED_CLK_APB>;
  694                 resets = <&syscon ASPEED_RESET_I2C>;
  695                 bus-frequency = <100000>;
  696                 interrupts = <6>;
  697                 interrupt-parent = <&i2c_ic>;
  698                 pinctrl-names = "default";
  699                 pinctrl-0 = <&pinctrl_i2c7_default>;
  700                 status = "disabled";
  701         };
  702 
  703         i2c7: i2c-bus@300 {
  704                 #address-cells = <1>;
  705                 #size-cells = <0>;
  706                 #interrupt-cells = <1>;
  707 
  708                 reg = <0x300 0x40>;
  709                 compatible = "aspeed,ast2500-i2c-bus";
  710                 clocks = <&syscon ASPEED_CLK_APB>;
  711                 resets = <&syscon ASPEED_RESET_I2C>;
  712                 bus-frequency = <100000>;
  713                 interrupts = <7>;
  714                 interrupt-parent = <&i2c_ic>;
  715                 pinctrl-names = "default";
  716                 pinctrl-0 = <&pinctrl_i2c8_default>;
  717                 status = "disabled";
  718         };
  719 
  720         i2c8: i2c-bus@340 {
  721                 #address-cells = <1>;
  722                 #size-cells = <0>;
  723                 #interrupt-cells = <1>;
  724 
  725                 reg = <0x340 0x40>;
  726                 compatible = "aspeed,ast2500-i2c-bus";
  727                 clocks = <&syscon ASPEED_CLK_APB>;
  728                 resets = <&syscon ASPEED_RESET_I2C>;
  729                 bus-frequency = <100000>;
  730                 interrupts = <8>;
  731                 interrupt-parent = <&i2c_ic>;
  732                 pinctrl-names = "default";
  733                 pinctrl-0 = <&pinctrl_i2c9_default>;
  734                 status = "disabled";
  735         };
  736 
  737         i2c9: i2c-bus@380 {
  738                 #address-cells = <1>;
  739                 #size-cells = <0>;
  740                 #interrupt-cells = <1>;
  741 
  742                 reg = <0x380 0x40>;
  743                 compatible = "aspeed,ast2500-i2c-bus";
  744                 clocks = <&syscon ASPEED_CLK_APB>;
  745                 resets = <&syscon ASPEED_RESET_I2C>;
  746                 bus-frequency = <100000>;
  747                 interrupts = <9>;
  748                 interrupt-parent = <&i2c_ic>;
  749                 pinctrl-names = "default";
  750                 pinctrl-0 = <&pinctrl_i2c10_default>;
  751                 status = "disabled";
  752         };
  753 
  754         i2c10: i2c-bus@3c0 {
  755                 #address-cells = <1>;
  756                 #size-cells = <0>;
  757                 #interrupt-cells = <1>;
  758 
  759                 reg = <0x3c0 0x40>;
  760                 compatible = "aspeed,ast2500-i2c-bus";
  761                 clocks = <&syscon ASPEED_CLK_APB>;
  762                 resets = <&syscon ASPEED_RESET_I2C>;
  763                 bus-frequency = <100000>;
  764                 interrupts = <10>;
  765                 interrupt-parent = <&i2c_ic>;
  766                 pinctrl-names = "default";
  767                 pinctrl-0 = <&pinctrl_i2c11_default>;
  768                 status = "disabled";
  769         };
  770 
  771         i2c11: i2c-bus@400 {
  772                 #address-cells = <1>;
  773                 #size-cells = <0>;
  774                 #interrupt-cells = <1>;
  775 
  776                 reg = <0x400 0x40>;
  777                 compatible = "aspeed,ast2500-i2c-bus";
  778                 clocks = <&syscon ASPEED_CLK_APB>;
  779                 resets = <&syscon ASPEED_RESET_I2C>;
  780                 bus-frequency = <100000>;
  781                 interrupts = <11>;
  782                 interrupt-parent = <&i2c_ic>;
  783                 pinctrl-names = "default";
  784                 pinctrl-0 = <&pinctrl_i2c12_default>;
  785                 status = "disabled";
  786         };
  787 
  788         i2c12: i2c-bus@440 {
  789                 #address-cells = <1>;
  790                 #size-cells = <0>;
  791                 #interrupt-cells = <1>;
  792 
  793                 reg = <0x440 0x40>;
  794                 compatible = "aspeed,ast2500-i2c-bus";
  795                 clocks = <&syscon ASPEED_CLK_APB>;
  796                 resets = <&syscon ASPEED_RESET_I2C>;
  797                 bus-frequency = <100000>;
  798                 interrupts = <12>;
  799                 interrupt-parent = <&i2c_ic>;
  800                 pinctrl-names = "default";
  801                 pinctrl-0 = <&pinctrl_i2c13_default>;
  802                 status = "disabled";
  803         };
  804 
  805         i2c13: i2c-bus@480 {
  806                 #address-cells = <1>;
  807                 #size-cells = <0>;
  808                 #interrupt-cells = <1>;
  809 
  810                 reg = <0x480 0x40>;
  811                 compatible = "aspeed,ast2500-i2c-bus";
  812                 clocks = <&syscon ASPEED_CLK_APB>;
  813                 resets = <&syscon ASPEED_RESET_I2C>;
  814                 bus-frequency = <100000>;
  815                 interrupts = <13>;
  816                 interrupt-parent = <&i2c_ic>;
  817                 pinctrl-names = "default";
  818                 pinctrl-0 = <&pinctrl_i2c14_default>;
  819                 status = "disabled";
  820         };
  821 };
  822 
  823 &pinctrl {
  824         pinctrl_acpi_default: acpi_default {
  825                 function = "ACPI";
  826                 groups = "ACPI";
  827         };
  828 
  829         pinctrl_adc0_default: adc0_default {
  830                 function = "ADC0";
  831                 groups = "ADC0";
  832         };
  833 
  834         pinctrl_adc1_default: adc1_default {
  835                 function = "ADC1";
  836                 groups = "ADC1";
  837         };
  838 
  839         pinctrl_adc10_default: adc10_default {
  840                 function = "ADC10";
  841                 groups = "ADC10";
  842         };
  843 
  844         pinctrl_adc11_default: adc11_default {
  845                 function = "ADC11";
  846                 groups = "ADC11";
  847         };
  848 
  849         pinctrl_adc12_default: adc12_default {
  850                 function = "ADC12";
  851                 groups = "ADC12";
  852         };
  853 
  854         pinctrl_adc13_default: adc13_default {
  855                 function = "ADC13";
  856                 groups = "ADC13";
  857         };
  858 
  859         pinctrl_adc14_default: adc14_default {
  860                 function = "ADC14";
  861                 groups = "ADC14";
  862         };
  863 
  864         pinctrl_adc15_default: adc15_default {
  865                 function = "ADC15";
  866                 groups = "ADC15";
  867         };
  868 
  869         pinctrl_adc2_default: adc2_default {
  870                 function = "ADC2";
  871                 groups = "ADC2";
  872         };
  873 
  874         pinctrl_adc3_default: adc3_default {
  875                 function = "ADC3";
  876                 groups = "ADC3";
  877         };
  878 
  879         pinctrl_adc4_default: adc4_default {
  880                 function = "ADC4";
  881                 groups = "ADC4";
  882         };
  883 
  884         pinctrl_adc5_default: adc5_default {
  885                 function = "ADC5";
  886                 groups = "ADC5";
  887         };
  888 
  889         pinctrl_adc6_default: adc6_default {
  890                 function = "ADC6";
  891                 groups = "ADC6";
  892         };
  893 
  894         pinctrl_adc7_default: adc7_default {
  895                 function = "ADC7";
  896                 groups = "ADC7";
  897         };
  898 
  899         pinctrl_adc8_default: adc8_default {
  900                 function = "ADC8";
  901                 groups = "ADC8";
  902         };
  903 
  904         pinctrl_adc9_default: adc9_default {
  905                 function = "ADC9";
  906                 groups = "ADC9";
  907         };
  908 
  909         pinctrl_bmcint_default: bmcint_default {
  910                 function = "BMCINT";
  911                 groups = "BMCINT";
  912         };
  913 
  914         pinctrl_ddcclk_default: ddcclk_default {
  915                 function = "DDCCLK";
  916                 groups = "DDCCLK";
  917         };
  918 
  919         pinctrl_ddcdat_default: ddcdat_default {
  920                 function = "DDCDAT";
  921                 groups = "DDCDAT";
  922         };
  923 
  924         pinctrl_espi_default: espi_default {
  925                 function = "ESPI";
  926                 groups = "ESPI";
  927         };
  928 
  929         pinctrl_fwspics1_default: fwspics1_default {
  930                 function = "FWSPICS1";
  931                 groups = "FWSPICS1";
  932         };
  933 
  934         pinctrl_fwspics2_default: fwspics2_default {
  935                 function = "FWSPICS2";
  936                 groups = "FWSPICS2";
  937         };
  938 
  939         pinctrl_gpid0_default: gpid0_default {
  940                 function = "GPID0";
  941                 groups = "GPID0";
  942         };
  943 
  944         pinctrl_gpid2_default: gpid2_default {
  945                 function = "GPID2";
  946                 groups = "GPID2";
  947         };
  948 
  949         pinctrl_gpid4_default: gpid4_default {
  950                 function = "GPID4";
  951                 groups = "GPID4";
  952         };
  953 
  954         pinctrl_gpid6_default: gpid6_default {
  955                 function = "GPID6";
  956                 groups = "GPID6";
  957         };
  958 
  959         pinctrl_gpie0_default: gpie0_default {
  960                 function = "GPIE0";
  961                 groups = "GPIE0";
  962         };
  963 
  964         pinctrl_gpie2_default: gpie2_default {
  965                 function = "GPIE2";
  966                 groups = "GPIE2";
  967         };
  968 
  969         pinctrl_gpie4_default: gpie4_default {
  970                 function = "GPIE4";
  971                 groups = "GPIE4";
  972         };
  973 
  974         pinctrl_gpie6_default: gpie6_default {
  975                 function = "GPIE6";
  976                 groups = "GPIE6";
  977         };
  978 
  979         pinctrl_i2c10_default: i2c10_default {
  980                 function = "I2C10";
  981                 groups = "I2C10";
  982         };
  983 
  984         pinctrl_i2c11_default: i2c11_default {
  985                 function = "I2C11";
  986                 groups = "I2C11";
  987         };
  988 
  989         pinctrl_i2c12_default: i2c12_default {
  990                 function = "I2C12";
  991                 groups = "I2C12";
  992         };
  993 
  994         pinctrl_i2c13_default: i2c13_default {
  995                 function = "I2C13";
  996                 groups = "I2C13";
  997         };
  998 
  999         pinctrl_i2c14_default: i2c14_default {
 1000                 function = "I2C14";
 1001                 groups = "I2C14";
 1002         };
 1003 
 1004         pinctrl_i2c3_default: i2c3_default {
 1005                 function = "I2C3";
 1006                 groups = "I2C3";
 1007         };
 1008 
 1009         pinctrl_i2c4_default: i2c4_default {
 1010                 function = "I2C4";
 1011                 groups = "I2C4";
 1012         };
 1013 
 1014         pinctrl_i2c5_default: i2c5_default {
 1015                 function = "I2C5";
 1016                 groups = "I2C5";
 1017         };
 1018 
 1019         pinctrl_i2c6_default: i2c6_default {
 1020                 function = "I2C6";
 1021                 groups = "I2C6";
 1022         };
 1023 
 1024         pinctrl_i2c7_default: i2c7_default {
 1025                 function = "I2C7";
 1026                 groups = "I2C7";
 1027         };
 1028 
 1029         pinctrl_i2c8_default: i2c8_default {
 1030                 function = "I2C8";
 1031                 groups = "I2C8";
 1032         };
 1033 
 1034         pinctrl_i2c9_default: i2c9_default {
 1035                 function = "I2C9";
 1036                 groups = "I2C9";
 1037         };
 1038 
 1039         pinctrl_lad0_default: lad0_default {
 1040                 function = "LAD0";
 1041                 groups = "LAD0";
 1042         };
 1043 
 1044         pinctrl_lad1_default: lad1_default {
 1045                 function = "LAD1";
 1046                 groups = "LAD1";
 1047         };
 1048 
 1049         pinctrl_lad2_default: lad2_default {
 1050                 function = "LAD2";
 1051                 groups = "LAD2";
 1052         };
 1053 
 1054         pinctrl_lad3_default: lad3_default {
 1055                 function = "LAD3";
 1056                 groups = "LAD3";
 1057         };
 1058 
 1059         pinctrl_lclk_default: lclk_default {
 1060                 function = "LCLK";
 1061                 groups = "LCLK";
 1062         };
 1063 
 1064         pinctrl_lframe_default: lframe_default {
 1065                 function = "LFRAME";
 1066                 groups = "LFRAME";
 1067         };
 1068 
 1069         pinctrl_lpchc_default: lpchc_default {
 1070                 function = "LPCHC";
 1071                 groups = "LPCHC";
 1072         };
 1073 
 1074         pinctrl_lpcpd_default: lpcpd_default {
 1075                 function = "LPCPD";
 1076                 groups = "LPCPD";
 1077         };
 1078 
 1079         pinctrl_lpcplus_default: lpcplus_default {
 1080                 function = "LPCPLUS";
 1081                 groups = "LPCPLUS";
 1082         };
 1083 
 1084         pinctrl_lpcpme_default: lpcpme_default {
 1085                 function = "LPCPME";
 1086                 groups = "LPCPME";
 1087         };
 1088 
 1089         pinctrl_lpcrst_default: lpcrst_default {
 1090                 function = "LPCRST";
 1091                 groups = "LPCRST";
 1092         };
 1093 
 1094         pinctrl_lpcsmi_default: lpcsmi_default {
 1095                 function = "LPCSMI";
 1096                 groups = "LPCSMI";
 1097         };
 1098 
 1099         pinctrl_lsirq_default: lsirq_default {
 1100                 function = "LSIRQ";
 1101                 groups = "LSIRQ";
 1102         };
 1103 
 1104         pinctrl_mac1link_default: mac1link_default {
 1105                 function = "MAC1LINK";
 1106                 groups = "MAC1LINK";
 1107         };
 1108 
 1109         pinctrl_mac2link_default: mac2link_default {
 1110                 function = "MAC2LINK";
 1111                 groups = "MAC2LINK";
 1112         };
 1113 
 1114         pinctrl_mdio1_default: mdio1_default {
 1115                 function = "MDIO1";
 1116                 groups = "MDIO1";
 1117         };
 1118 
 1119         pinctrl_mdio2_default: mdio2_default {
 1120                 function = "MDIO2";
 1121                 groups = "MDIO2";
 1122         };
 1123 
 1124         pinctrl_ncts1_default: ncts1_default {
 1125                 function = "NCTS1";
 1126                 groups = "NCTS1";
 1127         };
 1128 
 1129         pinctrl_ncts2_default: ncts2_default {
 1130                 function = "NCTS2";
 1131                 groups = "NCTS2";
 1132         };
 1133 
 1134         pinctrl_ncts3_default: ncts3_default {
 1135                 function = "NCTS3";
 1136                 groups = "NCTS3";
 1137         };
 1138 
 1139         pinctrl_ncts4_default: ncts4_default {
 1140                 function = "NCTS4";
 1141                 groups = "NCTS4";
 1142         };
 1143 
 1144         pinctrl_ndcd1_default: ndcd1_default {
 1145                 function = "NDCD1";
 1146                 groups = "NDCD1";
 1147         };
 1148 
 1149         pinctrl_ndcd2_default: ndcd2_default {
 1150                 function = "NDCD2";
 1151                 groups = "NDCD2";
 1152         };
 1153 
 1154         pinctrl_ndcd3_default: ndcd3_default {
 1155                 function = "NDCD3";
 1156                 groups = "NDCD3";
 1157         };
 1158 
 1159         pinctrl_ndcd4_default: ndcd4_default {
 1160                 function = "NDCD4";
 1161                 groups = "NDCD4";
 1162         };
 1163 
 1164         pinctrl_ndsr1_default: ndsr1_default {
 1165                 function = "NDSR1";
 1166                 groups = "NDSR1";
 1167         };
 1168 
 1169         pinctrl_ndsr2_default: ndsr2_default {
 1170                 function = "NDSR2";
 1171                 groups = "NDSR2";
 1172         };
 1173 
 1174         pinctrl_ndsr3_default: ndsr3_default {
 1175                 function = "NDSR3";
 1176                 groups = "NDSR3";
 1177         };
 1178 
 1179         pinctrl_ndsr4_default: ndsr4_default {
 1180                 function = "NDSR4";
 1181                 groups = "NDSR4";
 1182         };
 1183 
 1184         pinctrl_ndtr1_default: ndtr1_default {
 1185                 function = "NDTR1";
 1186                 groups = "NDTR1";
 1187         };
 1188 
 1189         pinctrl_ndtr2_default: ndtr2_default {
 1190                 function = "NDTR2";
 1191                 groups = "NDTR2";
 1192         };
 1193 
 1194         pinctrl_ndtr3_default: ndtr3_default {
 1195                 function = "NDTR3";
 1196                 groups = "NDTR3";
 1197         };
 1198 
 1199         pinctrl_ndtr4_default: ndtr4_default {
 1200                 function = "NDTR4";
 1201                 groups = "NDTR4";
 1202         };
 1203 
 1204         pinctrl_nri1_default: nri1_default {
 1205                 function = "NRI1";
 1206                 groups = "NRI1";
 1207         };
 1208 
 1209         pinctrl_nri2_default: nri2_default {
 1210                 function = "NRI2";
 1211                 groups = "NRI2";
 1212         };
 1213 
 1214         pinctrl_nri3_default: nri3_default {
 1215                 function = "NRI3";
 1216                 groups = "NRI3";
 1217         };
 1218 
 1219         pinctrl_nri4_default: nri4_default {
 1220                 function = "NRI4";
 1221                 groups = "NRI4";
 1222         };
 1223 
 1224         pinctrl_nrts1_default: nrts1_default {
 1225                 function = "NRTS1";
 1226                 groups = "NRTS1";
 1227         };
 1228 
 1229         pinctrl_nrts2_default: nrts2_default {
 1230                 function = "NRTS2";
 1231                 groups = "NRTS2";
 1232         };
 1233 
 1234         pinctrl_nrts3_default: nrts3_default {
 1235                 function = "NRTS3";
 1236                 groups = "NRTS3";
 1237         };
 1238 
 1239         pinctrl_nrts4_default: nrts4_default {
 1240                 function = "NRTS4";
 1241                 groups = "NRTS4";
 1242         };
 1243 
 1244         pinctrl_oscclk_default: oscclk_default {
 1245                 function = "OSCCLK";
 1246                 groups = "OSCCLK";
 1247         };
 1248 
 1249         pinctrl_pewake_default: pewake_default {
 1250                 function = "PEWAKE";
 1251                 groups = "PEWAKE";
 1252         };
 1253 
 1254         pinctrl_pnor_default: pnor_default {
 1255                 function = "PNOR";
 1256                 groups = "PNOR";
 1257         };
 1258 
 1259         pinctrl_pwm0_default: pwm0_default {
 1260                 function = "PWM0";
 1261                 groups = "PWM0";
 1262         };
 1263 
 1264         pinctrl_pwm1_default: pwm1_default {
 1265                 function = "PWM1";
 1266                 groups = "PWM1";
 1267         };
 1268 
 1269         pinctrl_pwm2_default: pwm2_default {
 1270                 function = "PWM2";
 1271                 groups = "PWM2";
 1272         };
 1273 
 1274         pinctrl_pwm3_default: pwm3_default {
 1275                 function = "PWM3";
 1276                 groups = "PWM3";
 1277         };
 1278 
 1279         pinctrl_pwm4_default: pwm4_default {
 1280                 function = "PWM4";
 1281                 groups = "PWM4";
 1282         };
 1283 
 1284         pinctrl_pwm5_default: pwm5_default {
 1285                 function = "PWM5";
 1286                 groups = "PWM5";
 1287         };
 1288 
 1289         pinctrl_pwm6_default: pwm6_default {
 1290                 function = "PWM6";
 1291                 groups = "PWM6";
 1292         };
 1293 
 1294         pinctrl_pwm7_default: pwm7_default {
 1295                 function = "PWM7";
 1296                 groups = "PWM7";
 1297         };
 1298 
 1299         pinctrl_rgmii1_default: rgmii1_default {
 1300                 function = "RGMII1";
 1301                 groups = "RGMII1";
 1302         };
 1303 
 1304         pinctrl_rgmii2_default: rgmii2_default {
 1305                 function = "RGMII2";
 1306                 groups = "RGMII2";
 1307         };
 1308 
 1309         pinctrl_rmii1_default: rmii1_default {
 1310                 function = "RMII1";
 1311                 groups = "RMII1";
 1312         };
 1313 
 1314         pinctrl_rmii2_default: rmii2_default {
 1315                 function = "RMII2";
 1316                 groups = "RMII2";
 1317         };
 1318 
 1319         pinctrl_rxd1_default: rxd1_default {
 1320                 function = "RXD1";
 1321                 groups = "RXD1";
 1322         };
 1323 
 1324         pinctrl_rxd2_default: rxd2_default {
 1325                 function = "RXD2";
 1326                 groups = "RXD2";
 1327         };
 1328 
 1329         pinctrl_rxd3_default: rxd3_default {
 1330                 function = "RXD3";
 1331                 groups = "RXD3";
 1332         };
 1333 
 1334         pinctrl_rxd4_default: rxd4_default {
 1335                 function = "RXD4";
 1336                 groups = "RXD4";
 1337         };
 1338 
 1339         pinctrl_salt1_default: salt1_default {
 1340                 function = "SALT1";
 1341                 groups = "SALT1";
 1342         };
 1343 
 1344         pinctrl_salt10_default: salt10_default {
 1345                 function = "SALT10";
 1346                 groups = "SALT10";
 1347         };
 1348 
 1349         pinctrl_salt11_default: salt11_default {
 1350                 function = "SALT11";
 1351                 groups = "SALT11";
 1352         };
 1353 
 1354         pinctrl_salt12_default: salt12_default {
 1355                 function = "SALT12";
 1356                 groups = "SALT12";
 1357         };
 1358 
 1359         pinctrl_salt13_default: salt13_default {
 1360                 function = "SALT13";
 1361                 groups = "SALT13";
 1362         };
 1363 
 1364         pinctrl_salt14_default: salt14_default {
 1365                 function = "SALT14";
 1366                 groups = "SALT14";
 1367         };
 1368 
 1369         pinctrl_salt2_default: salt2_default {
 1370                 function = "SALT2";
 1371                 groups = "SALT2";
 1372         };
 1373 
 1374         pinctrl_salt3_default: salt3_default {
 1375                 function = "SALT3";
 1376                 groups = "SALT3";
 1377         };
 1378 
 1379         pinctrl_salt4_default: salt4_default {
 1380                 function = "SALT4";
 1381                 groups = "SALT4";
 1382         };
 1383 
 1384         pinctrl_salt5_default: salt5_default {
 1385                 function = "SALT5";
 1386                 groups = "SALT5";
 1387         };
 1388 
 1389         pinctrl_salt6_default: salt6_default {
 1390                 function = "SALT6";
 1391                 groups = "SALT6";
 1392         };
 1393 
 1394         pinctrl_salt7_default: salt7_default {
 1395                 function = "SALT7";
 1396                 groups = "SALT7";
 1397         };
 1398 
 1399         pinctrl_salt8_default: salt8_default {
 1400                 function = "SALT8";
 1401                 groups = "SALT8";
 1402         };
 1403 
 1404         pinctrl_salt9_default: salt9_default {
 1405                 function = "SALT9";
 1406                 groups = "SALT9";
 1407         };
 1408 
 1409         pinctrl_scl1_default: scl1_default {
 1410                 function = "SCL1";
 1411                 groups = "SCL1";
 1412         };
 1413 
 1414         pinctrl_scl2_default: scl2_default {
 1415                 function = "SCL2";
 1416                 groups = "SCL2";
 1417         };
 1418 
 1419         pinctrl_sd1_default: sd1_default {
 1420                 function = "SD1";
 1421                 groups = "SD1";
 1422         };
 1423 
 1424         pinctrl_sd2_default: sd2_default {
 1425                 function = "SD2";
 1426                 groups = "SD2";
 1427         };
 1428 
 1429         pinctrl_sda1_default: sda1_default {
 1430                 function = "SDA1";
 1431                 groups = "SDA1";
 1432         };
 1433 
 1434         pinctrl_sda2_default: sda2_default {
 1435                 function = "SDA2";
 1436                 groups = "SDA2";
 1437         };
 1438 
 1439         pinctrl_sgpm_default: sgpm_default {
 1440                 function = "SGPM";
 1441                 groups = "SGPM";
 1442         };
 1443 
 1444         pinctrl_sgps1_default: sgps1_default {
 1445                 function = "SGPS1";
 1446                 groups = "SGPS1";
 1447         };
 1448 
 1449         pinctrl_sgps2_default: sgps2_default {
 1450                 function = "SGPS2";
 1451                 groups = "SGPS2";
 1452         };
 1453 
 1454         pinctrl_sioonctrl_default: sioonctrl_default {
 1455                 function = "SIOONCTRL";
 1456                 groups = "SIOONCTRL";
 1457         };
 1458 
 1459         pinctrl_siopbi_default: siopbi_default {
 1460                 function = "SIOPBI";
 1461                 groups = "SIOPBI";
 1462         };
 1463 
 1464         pinctrl_siopbo_default: siopbo_default {
 1465                 function = "SIOPBO";
 1466                 groups = "SIOPBO";
 1467         };
 1468 
 1469         pinctrl_siopwreq_default: siopwreq_default {
 1470                 function = "SIOPWREQ";
 1471                 groups = "SIOPWREQ";
 1472         };
 1473 
 1474         pinctrl_siopwrgd_default: siopwrgd_default {
 1475                 function = "SIOPWRGD";
 1476                 groups = "SIOPWRGD";
 1477         };
 1478 
 1479         pinctrl_sios3_default: sios3_default {
 1480                 function = "SIOS3";
 1481                 groups = "SIOS3";
 1482         };
 1483 
 1484         pinctrl_sios5_default: sios5_default {
 1485                 function = "SIOS5";
 1486                 groups = "SIOS5";
 1487         };
 1488 
 1489         pinctrl_siosci_default: siosci_default {
 1490                 function = "SIOSCI";
 1491                 groups = "SIOSCI";
 1492         };
 1493 
 1494         pinctrl_spi1_default: spi1_default {
 1495                 function = "SPI1";
 1496                 groups = "SPI1";
 1497         };
 1498 
 1499         pinctrl_spi1cs1_default: spi1cs1_default {
 1500                 function = "SPI1CS1";
 1501                 groups = "SPI1CS1";
 1502         };
 1503 
 1504         pinctrl_spi1debug_default: spi1debug_default {
 1505                 function = "SPI1DEBUG";
 1506                 groups = "SPI1DEBUG";
 1507         };
 1508 
 1509         pinctrl_spi1passthru_default: spi1passthru_default {
 1510                 function = "SPI1PASSTHRU";
 1511                 groups = "SPI1PASSTHRU";
 1512         };
 1513 
 1514         pinctrl_spi2ck_default: spi2ck_default {
 1515                 function = "SPI2CK";
 1516                 groups = "SPI2CK";
 1517         };
 1518 
 1519         pinctrl_spi2cs0_default: spi2cs0_default {
 1520                 function = "SPI2CS0";
 1521                 groups = "SPI2CS0";
 1522         };
 1523 
 1524         pinctrl_spi2cs1_default: spi2cs1_default {
 1525                 function = "SPI2CS1";
 1526                 groups = "SPI2CS1";
 1527         };
 1528 
 1529         pinctrl_spi2miso_default: spi2miso_default {
 1530                 function = "SPI2MISO";
 1531                 groups = "SPI2MISO";
 1532         };
 1533 
 1534         pinctrl_spi2mosi_default: spi2mosi_default {
 1535                 function = "SPI2MOSI";
 1536                 groups = "SPI2MOSI";
 1537         };
 1538 
 1539         pinctrl_timer3_default: timer3_default {
 1540                 function = "TIMER3";
 1541                 groups = "TIMER3";
 1542         };
 1543 
 1544         pinctrl_timer4_default: timer4_default {
 1545                 function = "TIMER4";
 1546                 groups = "TIMER4";
 1547         };
 1548 
 1549         pinctrl_timer5_default: timer5_default {
 1550                 function = "TIMER5";
 1551                 groups = "TIMER5";
 1552         };
 1553 
 1554         pinctrl_timer6_default: timer6_default {
 1555                 function = "TIMER6";
 1556                 groups = "TIMER6";
 1557         };
 1558 
 1559         pinctrl_timer7_default: timer7_default {
 1560                 function = "TIMER7";
 1561                 groups = "TIMER7";
 1562         };
 1563 
 1564         pinctrl_timer8_default: timer8_default {
 1565                 function = "TIMER8";
 1566                 groups = "TIMER8";
 1567         };
 1568 
 1569         pinctrl_txd1_default: txd1_default {
 1570                 function = "TXD1";
 1571                 groups = "TXD1";
 1572         };
 1573 
 1574         pinctrl_txd2_default: txd2_default {
 1575                 function = "TXD2";
 1576                 groups = "TXD2";
 1577         };
 1578 
 1579         pinctrl_txd3_default: txd3_default {
 1580                 function = "TXD3";
 1581                 groups = "TXD3";
 1582         };
 1583 
 1584         pinctrl_txd4_default: txd4_default {
 1585                 function = "TXD4";
 1586                 groups = "TXD4";
 1587         };
 1588 
 1589         pinctrl_uart6_default: uart6_default {
 1590                 function = "UART6";
 1591                 groups = "UART6";
 1592         };
 1593 
 1594         pinctrl_usbcki_default: usbcki_default {
 1595                 function = "USBCKI";
 1596                 groups = "USBCKI";
 1597         };
 1598 
 1599         pinctrl_usb2ah_default: usb2ah_default {
 1600                 function = "USB2AH";
 1601                 groups = "USB2AH";
 1602         };
 1603 
 1604         pinctrl_usb2ad_default: usb2ad_default {
 1605                 function = "USB2AD";
 1606                 groups = "USB2AD";
 1607         };
 1608 
 1609         pinctrl_usb11bhid_default: usb11bhid_default {
 1610                 function = "USB11BHID";
 1611                 groups = "USB11BHID";
 1612         };
 1613 
 1614         pinctrl_usb2bh_default: usb2bh_default {
 1615                 function = "USB2BH";
 1616                 groups = "USB2BH";
 1617         };
 1618 
 1619         pinctrl_vgabiosrom_default: vgabiosrom_default {
 1620                 function = "VGABIOSROM";
 1621                 groups = "VGABIOSROM";
 1622         };
 1623 
 1624         pinctrl_vgahs_default: vgahs_default {
 1625                 function = "VGAHS";
 1626                 groups = "VGAHS";
 1627         };
 1628 
 1629         pinctrl_vgavs_default: vgavs_default {
 1630                 function = "VGAVS";
 1631                 groups = "VGAVS";
 1632         };
 1633 
 1634         pinctrl_vpi24_default: vpi24_default {
 1635                 function = "VPI24";
 1636                 groups = "VPI24";
 1637         };
 1638 
 1639         pinctrl_vpo_default: vpo_default {
 1640                 function = "VPO";
 1641                 groups = "VPO";
 1642         };
 1643 
 1644         pinctrl_wdtrst1_default: wdtrst1_default {
 1645                 function = "WDTRST1";
 1646                 groups = "WDTRST1";
 1647         };
 1648 
 1649         pinctrl_wdtrst2_default: wdtrst2_default {
 1650                 function = "WDTRST2";
 1651                 groups = "WDTRST2";
 1652         };
 1653 };
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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm/aspeed-g5.dtsi

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/aspeed-g5.dtsi
