Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/bcm21664.dtsi
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1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (C) 2014 Broadcom Corporation 3 4 #include <dt-bindings/interrupt-controller/arm-gic.h> 5 #include <dt-bindings/interrupt-controller/irq.h> 6 7 #include "dt-bindings/clock/bcm21664.h" 8 9 / { 10 #address-cells = <1>; 11 #size-cells = <1>; 12 model = "BCM21664 SoC"; 13 compatible = "brcm,bcm21664"; 14 interrupt-parent = <&gic>; 15 16 chosen { 17 bootargs = "console=ttyS0,115200n8"; 18 }; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 device_type = "cpu"; 26 compatible = "arm,cortex-a9"; 27 reg = <0>; 28 }; 29 30 cpu1: cpu@1 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a9"; 33 enable-method = "brcm,bcm11351-cpu-method"; 34 secondary-boot-reg = <0x35004178>; 35 reg = <1>; 36 }; 37 }; 38 39 gic: interrupt-controller@3ff00100 { 40 compatible = "arm,cortex-a9-gic"; 41 #interrupt-cells = <3>; 42 #address-cells = <0>; 43 interrupt-controller; 44 reg = <0x3ff01000 0x1000>, 45 <0x3ff00100 0x100>; 46 }; 47 48 smc@3404e000 { 49 compatible = "brcm,bcm21664-smc", "brcm,kona-smc"; 50 reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */ 51 }; 52 53 uart@3e000000 { 54 compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; 55 status = "disabled"; 56 reg = <0x3e000000 0x118>; 57 clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>; 58 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 59 reg-shift = <2>; 60 reg-io-width = <4>; 61 }; 62 63 uart@3e001000 { 64 compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; 65 status = "disabled"; 66 reg = <0x3e001000 0x118>; 67 clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>; 68 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 69 reg-shift = <2>; 70 reg-io-width = <4>; 71 }; 72 73 uart@3e002000 { 74 compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; 75 status = "disabled"; 76 reg = <0x3e002000 0x118>; 77 clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>; 78 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 79 reg-shift = <2>; 80 reg-io-width = <4>; 81 }; 82 83 L2: cache-controller@3ff20000 { 84 compatible = "arm,pl310-cache"; 85 reg = <0x3ff20000 0x1000>; 86 cache-unified; 87 cache-level = <2>; 88 }; 89 90 brcm,resetmgr@35001f00 { 91 compatible = "brcm,bcm21664-resetmgr"; 92 reg = <0x35001f00 0x24>; 93 }; 94 95 timer@35006000 { 96 compatible = "brcm,kona-timer"; 97 reg = <0x35006000 0x1c>; 98 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 99 clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>; 100 }; 101 102 gpio: gpio@35003000 { 103 compatible = "brcm,bcm21664-gpio", "brcm,kona-gpio"; 104 reg = <0x35003000 0x524>; 105 interrupts = 106 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 107 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 108 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 109 GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 110 #gpio-cells = <2>; 111 #interrupt-cells = <2>; 112 gpio-controller; 113 interrupt-controller; 114 }; 115 116 sdio1: sdio@3f180000 { 117 compatible = "brcm,kona-sdhci"; 118 reg = <0x3f180000 0x801c>; 119 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 120 clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>; 121 status = "disabled"; 122 }; 123 124 sdio2: sdio@3f190000 { 125 compatible = "brcm,kona-sdhci"; 126 reg = <0x3f190000 0x801c>; 127 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 128 clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>; 129 status = "disabled"; 130 }; 131 132 sdio3: sdio@3f1a0000 { 133 compatible = "brcm,kona-sdhci"; 134 reg = <0x3f1a0000 0x801c>; 135 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 136 clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>; 137 status = "disabled"; 138 }; 139 140 sdio4: sdio@3f1b0000 { 141 compatible = "brcm,kona-sdhci"; 142 reg = <0x3f1b0000 0x801c>; 143 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 144 clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>; 145 status = "disabled"; 146 }; 147 148 i2c@3e016000 { 149 compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; 150 reg = <0x3e016000 0x70>; 151 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 152 #address-cells = <1>; 153 #size-cells = <0>; 154 clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>; 155 status = "disabled"; 156 }; 157 158 i2c@3e017000 { 159 compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; 160 reg = <0x3e017000 0x70>; 161 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 162 #address-cells = <1>; 163 #size-cells = <0>; 164 clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>; 165 status = "disabled"; 166 }; 167 168 i2c@3e018000 { 169 compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; 170 reg = <0x3e018000 0x70>; 171 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 172 #address-cells = <1>; 173 #size-cells = <0>; 174 clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>; 175 status = "disabled"; 176 }; 177 178 i2c@3e01c000 { 179 compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; 180 reg = <0x3e01c000 0x70>; 181 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 182 #address-cells = <1>; 183 #size-cells = <0>; 184 clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>; 185 status = "disabled"; 186 }; 187 188 clocks { 189 #address-cells = <1>; 190 #size-cells = <1>; 191 ranges; 192 193 /* 194 * Fixed clocks are defined before CCUs whose 195 * clocks may depend on them. 196 */ 197 198 ref_32k_clk: ref_32k { 199 #clock-cells = <0>; 200 compatible = "fixed-clock"; 201 clock-frequency = <32768>; 202 }; 203 204 bbl_32k_clk: bbl_32k { 205 #clock-cells = <0>; 206 compatible = "fixed-clock"; 207 clock-frequency = <32768>; 208 }; 209 210 ref_13m_clk: ref_13m { 211 #clock-cells = <0>; 212 compatible = "fixed-clock"; 213 clock-frequency = <13000000>; 214 }; 215 216 var_13m_clk: var_13m { 217 #clock-cells = <0>; 218 compatible = "fixed-clock"; 219 clock-frequency = <13000000>; 220 }; 221 222 dft_19_5m_clk: dft_19_5m { 223 #clock-cells = <0>; 224 compatible = "fixed-clock"; 225 clock-frequency = <19500000>; 226 }; 227 228 ref_crystal_clk: ref_crystal { 229 #clock-cells = <0>; 230 compatible = "fixed-clock"; 231 clock-frequency = <26000000>; 232 }; 233 234 ref_52m_clk: ref_52m { 235 #clock-cells = <0>; 236 compatible = "fixed-clock"; 237 clock-frequency = <52000000>; 238 }; 239 240 var_52m_clk: var_52m { 241 #clock-cells = <0>; 242 compatible = "fixed-clock"; 243 clock-frequency = <52000000>; 244 }; 245 246 usb_otg_ahb_clk: usb_otg_ahb { 247 #clock-cells = <0>; 248 compatible = "fixed-clock"; 249 clock-frequency = <52000000>; 250 }; 251 252 ref_96m_clk: ref_96m { 253 #clock-cells = <0>; 254 compatible = "fixed-clock"; 255 clock-frequency = <96000000>; 256 }; 257 258 var_96m_clk: var_96m { 259 #clock-cells = <0>; 260 compatible = "fixed-clock"; 261 clock-frequency = <96000000>; 262 }; 263 264 ref_104m_clk: ref_104m { 265 #clock-cells = <0>; 266 compatible = "fixed-clock"; 267 clock-frequency = <104000000>; 268 }; 269 270 var_104m_clk: var_104m { 271 #clock-cells = <0>; 272 compatible = "fixed-clock"; 273 clock-frequency = <104000000>; 274 }; 275 276 ref_156m_clk: ref_156m { 277 #clock-cells = <0>; 278 compatible = "fixed-clock"; 279 clock-frequency = <156000000>; 280 }; 281 282 var_156m_clk: var_156m { 283 #clock-cells = <0>; 284 compatible = "fixed-clock"; 285 clock-frequency = <156000000>; 286 }; 287 288 root_ccu: root_ccu@35001000 { 289 compatible = BCM21664_DT_ROOT_CCU_COMPAT; 290 reg = <0x35001000 0x0f00>; 291 #clock-cells = <1>; 292 clock-output-names = "frac_1m"; 293 }; 294 295 aon_ccu: aon_ccu@35002000 { 296 compatible = BCM21664_DT_AON_CCU_COMPAT; 297 reg = <0x35002000 0x0f00>; 298 #clock-cells = <1>; 299 clock-output-names = "hub_timer"; 300 }; 301 302 master_ccu: master_ccu@3f001000 { 303 compatible = BCM21664_DT_MASTER_CCU_COMPAT; 304 reg = <0x3f001000 0x0f00>; 305 #clock-cells = <1>; 306 clock-output-names = "sdio1", 307 "sdio2", 308 "sdio3", 309 "sdio4", 310 "sdio1_sleep", 311 "sdio2_sleep", 312 "sdio3_sleep", 313 "sdio4_sleep"; 314 }; 315 316 slave_ccu: slave_ccu@3e011000 { 317 compatible = BCM21664_DT_SLAVE_CCU_COMPAT; 318 reg = <0x3e011000 0x0f00>; 319 #clock-cells = <1>; 320 clock-output-names = "uartb", 321 "uartb2", 322 "uartb3", 323 "bsc1", 324 "bsc2", 325 "bsc3", 326 "bsc4"; 327 }; 328 }; 329 330 usbotg: usb@3f120000 { 331 compatible = "snps,dwc2"; 332 reg = <0x3f120000 0x10000>; 333 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&usb_otg_ahb_clk>; 335 clock-names = "otg"; 336 phys = <&usbphy>; 337 phy-names = "usb2-phy"; 338 status = "disabled"; 339 }; 340 341 usbphy: usb-phy@3f130000 { 342 compatible = "brcm,kona-usb2-phy"; 343 reg = <0x3f130000 0x28>; 344 #phy-cells = <0>; 345 status = "disabled"; 346 }; 347 };
Cache object: dc895f6632753040d13a7ced35bc7c23
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