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1 // SPDX-License-Identifier: GPL-2.0 2 #include "bcm283x.dtsi" 3 4 #include <dt-bindings/interrupt-controller/arm-gic.h> 5 #include <dt-bindings/soc/bcm2835-pm.h> 6 7 / { 8 compatible = "brcm,bcm2711"; 9 10 #address-cells = <2>; 11 #size-cells = <1>; 12 13 interrupt-parent = <&gicv2>; 14 15 vc4: gpu { 16 compatible = "brcm,bcm2711-vc5"; 17 status = "disabled"; 18 }; 19 20 clk_27MHz: clk-27M { 21 #clock-cells = <0>; 22 compatible = "fixed-clock"; 23 clock-frequency = <27000000>; 24 clock-output-names = "27MHz-clock"; 25 }; 26 27 clk_108MHz: clk-108M { 28 #clock-cells = <0>; 29 compatible = "fixed-clock"; 30 clock-frequency = <108000000>; 31 clock-output-names = "108MHz-clock"; 32 }; 33 34 soc { 35 /* 36 * Defined ranges: 37 * Common BCM283x peripherals 38 * BCM2711-specific peripherals 39 * ARM-local peripherals 40 */ 41 ranges = <0x7e000000 0x0 0xfe000000 0x01800000>, 42 <0x7c000000 0x0 0xfc000000 0x02000000>, 43 <0x40000000 0x0 0xff800000 0x00800000>; 44 /* Emulate a contiguous 30-bit address range for DMA */ 45 dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>; 46 47 /* 48 * This node is the provider for the enable-method for 49 * bringing up secondary cores. 50 */ 51 local_intc: local_intc@40000000 { 52 compatible = "brcm,bcm2836-l1-intc"; 53 reg = <0x40000000 0x100>; 54 }; 55 56 gicv2: interrupt-controller@40041000 { 57 interrupt-controller; 58 #interrupt-cells = <3>; 59 compatible = "arm,gic-400"; 60 reg = <0x40041000 0x1000>, 61 <0x40042000 0x2000>, 62 <0x40044000 0x2000>, 63 <0x40046000 0x2000>; 64 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 65 IRQ_TYPE_LEVEL_HIGH)>; 66 }; 67 68 avs_monitor: avs-monitor@7d5d2000 { 69 compatible = "brcm,bcm2711-avs-monitor", 70 "syscon", "simple-mfd"; 71 reg = <0x7d5d2000 0xf00>; 72 73 thermal: thermal { 74 compatible = "brcm,bcm2711-thermal"; 75 #thermal-sensor-cells = <0>; 76 }; 77 }; 78 79 dma: dma@7e007000 { 80 compatible = "brcm,bcm2835-dma"; 81 reg = <0x7e007000 0xb00>; 82 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 89 /* DMA lite 7 - 10 */ 90 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 94 interrupt-names = "dma0", 95 "dma1", 96 "dma2", 97 "dma3", 98 "dma4", 99 "dma5", 100 "dma6", 101 "dma7", 102 "dma8", 103 "dma9", 104 "dma10"; 105 #dma-cells = <1>; 106 brcm,dma-channel-mask = <0x07f5>; 107 }; 108 109 pm: watchdog@7e100000 { 110 compatible = "brcm,bcm2711-pm", "brcm,bcm2835-pm-wdt"; 111 #power-domain-cells = <1>; 112 #reset-cells = <1>; 113 reg = <0x7e100000 0x114>, 114 <0x7e00a000 0x24>, 115 <0x7ec11000 0x20>; 116 reg-names = "pm", "asb", "rpivid_asb"; 117 clocks = <&clocks BCM2835_CLOCK_V3D>, 118 <&clocks BCM2835_CLOCK_PERI_IMAGE>, 119 <&clocks BCM2835_CLOCK_H264>, 120 <&clocks BCM2835_CLOCK_ISP>; 121 clock-names = "v3d", "peri_image", "h264", "isp"; 122 system-power-controller; 123 }; 124 125 rng@7e104000 { 126 compatible = "brcm,bcm2711-rng200"; 127 reg = <0x7e104000 0x28>; 128 }; 129 130 uart2: serial@7e201400 { 131 compatible = "arm,pl011", "arm,primecell"; 132 reg = <0x7e201400 0x200>; 133 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 134 clocks = <&clocks BCM2835_CLOCK_UART>, 135 <&clocks BCM2835_CLOCK_VPU>; 136 clock-names = "uartclk", "apb_pclk"; 137 arm,primecell-periphid = <0x00241011>; 138 status = "disabled"; 139 }; 140 141 uart3: serial@7e201600 { 142 compatible = "arm,pl011", "arm,primecell"; 143 reg = <0x7e201600 0x200>; 144 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 145 clocks = <&clocks BCM2835_CLOCK_UART>, 146 <&clocks BCM2835_CLOCK_VPU>; 147 clock-names = "uartclk", "apb_pclk"; 148 arm,primecell-periphid = <0x00241011>; 149 status = "disabled"; 150 }; 151 152 uart4: serial@7e201800 { 153 compatible = "arm,pl011", "arm,primecell"; 154 reg = <0x7e201800 0x200>; 155 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 156 clocks = <&clocks BCM2835_CLOCK_UART>, 157 <&clocks BCM2835_CLOCK_VPU>; 158 clock-names = "uartclk", "apb_pclk"; 159 arm,primecell-periphid = <0x00241011>; 160 status = "disabled"; 161 }; 162 163 uart5: serial@7e201a00 { 164 compatible = "arm,pl011", "arm,primecell"; 165 reg = <0x7e201a00 0x200>; 166 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 167 clocks = <&clocks BCM2835_CLOCK_UART>, 168 <&clocks BCM2835_CLOCK_VPU>; 169 clock-names = "uartclk", "apb_pclk"; 170 arm,primecell-periphid = <0x00241011>; 171 status = "disabled"; 172 }; 173 174 spi3: spi@7e204600 { 175 compatible = "brcm,bcm2835-spi"; 176 reg = <0x7e204600 0x0200>; 177 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 178 clocks = <&clocks BCM2835_CLOCK_VPU>; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 status = "disabled"; 182 }; 183 184 spi4: spi@7e204800 { 185 compatible = "brcm,bcm2835-spi"; 186 reg = <0x7e204800 0x0200>; 187 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 188 clocks = <&clocks BCM2835_CLOCK_VPU>; 189 #address-cells = <1>; 190 #size-cells = <0>; 191 status = "disabled"; 192 }; 193 194 spi5: spi@7e204a00 { 195 compatible = "brcm,bcm2835-spi"; 196 reg = <0x7e204a00 0x0200>; 197 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 198 clocks = <&clocks BCM2835_CLOCK_VPU>; 199 #address-cells = <1>; 200 #size-cells = <0>; 201 status = "disabled"; 202 }; 203 204 spi6: spi@7e204c00 { 205 compatible = "brcm,bcm2835-spi"; 206 reg = <0x7e204c00 0x0200>; 207 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&clocks BCM2835_CLOCK_VPU>; 209 #address-cells = <1>; 210 #size-cells = <0>; 211 status = "disabled"; 212 }; 213 214 i2c3: i2c@7e205600 { 215 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 216 reg = <0x7e205600 0x200>; 217 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&clocks BCM2835_CLOCK_VPU>; 219 #address-cells = <1>; 220 #size-cells = <0>; 221 status = "disabled"; 222 }; 223 224 i2c4: i2c@7e205800 { 225 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 226 reg = <0x7e205800 0x200>; 227 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&clocks BCM2835_CLOCK_VPU>; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 status = "disabled"; 232 }; 233 234 i2c5: i2c@7e205a00 { 235 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 236 reg = <0x7e205a00 0x200>; 237 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&clocks BCM2835_CLOCK_VPU>; 239 #address-cells = <1>; 240 #size-cells = <0>; 241 status = "disabled"; 242 }; 243 244 i2c6: i2c@7e205c00 { 245 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 246 reg = <0x7e205c00 0x200>; 247 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&clocks BCM2835_CLOCK_VPU>; 249 #address-cells = <1>; 250 #size-cells = <0>; 251 status = "disabled"; 252 }; 253 254 pixelvalve0: pixelvalve@7e206000 { 255 compatible = "brcm,bcm2711-pixelvalve0"; 256 reg = <0x7e206000 0x100>; 257 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 258 status = "disabled"; 259 }; 260 261 pixelvalve1: pixelvalve@7e207000 { 262 compatible = "brcm,bcm2711-pixelvalve1"; 263 reg = <0x7e207000 0x100>; 264 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 265 status = "disabled"; 266 }; 267 268 pixelvalve2: pixelvalve@7e20a000 { 269 compatible = "brcm,bcm2711-pixelvalve2"; 270 reg = <0x7e20a000 0x100>; 271 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 272 status = "disabled"; 273 }; 274 275 pwm1: pwm@7e20c800 { 276 compatible = "brcm,bcm2835-pwm"; 277 reg = <0x7e20c800 0x28>; 278 clocks = <&clocks BCM2835_CLOCK_PWM>; 279 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>; 280 assigned-clock-rates = <10000000>; 281 #pwm-cells = <2>; 282 status = "disabled"; 283 }; 284 285 pixelvalve4: pixelvalve@7e216000 { 286 compatible = "brcm,bcm2711-pixelvalve4"; 287 reg = <0x7e216000 0x100>; 288 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 289 status = "disabled"; 290 }; 291 292 hvs: hvs@7e400000 { 293 compatible = "brcm,bcm2711-hvs"; 294 reg = <0x7e400000 0x8000>; 295 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 296 }; 297 298 pixelvalve3: pixelvalve@7ec12000 { 299 compatible = "brcm,bcm2711-pixelvalve3"; 300 reg = <0x7ec12000 0x100>; 301 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 302 status = "disabled"; 303 }; 304 305 vec: vec@7ec13000 { 306 compatible = "brcm,bcm2711-vec"; 307 reg = <0x7ec13000 0x1000>; 308 clocks = <&clocks BCM2835_CLOCK_VEC>; 309 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 310 status = "disabled"; 311 }; 312 313 dvp: clock@7ef00000 { 314 compatible = "brcm,brcm2711-dvp"; 315 reg = <0x7ef00000 0x10>; 316 clocks = <&clk_108MHz>; 317 #clock-cells = <1>; 318 #reset-cells = <1>; 319 }; 320 321 aon_intr: interrupt-controller@7ef00100 { 322 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc"; 323 reg = <0x7ef00100 0x30>; 324 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 325 interrupt-controller; 326 #interrupt-cells = <1>; 327 }; 328 329 hdmi0: hdmi@7ef00700 { 330 compatible = "brcm,bcm2711-hdmi0"; 331 reg = <0x7ef00700 0x300>, 332 <0x7ef00300 0x200>, 333 <0x7ef00f00 0x80>, 334 <0x7ef00f80 0x80>, 335 <0x7ef01b00 0x200>, 336 <0x7ef01f00 0x400>, 337 <0x7ef00200 0x80>, 338 <0x7ef04300 0x100>, 339 <0x7ef20000 0x100>; 340 reg-names = "hdmi", 341 "dvp", 342 "phy", 343 "rm", 344 "packet", 345 "metadata", 346 "csc", 347 "cec", 348 "hd"; 349 clock-names = "hdmi", "bvb", "audio", "cec"; 350 resets = <&dvp 0>; 351 interrupt-parent = <&aon_intr>; 352 interrupts = <0>, <1>, <2>, 353 <3>, <4>, <5>; 354 interrupt-names = "cec-tx", "cec-rx", "cec-low", 355 "wakeup", "hpd-connected", "hpd-removed"; 356 ddc = <&ddc0>; 357 dmas = <&dma 10>; 358 dma-names = "audio-rx"; 359 status = "disabled"; 360 }; 361 362 ddc0: i2c@7ef04500 { 363 compatible = "brcm,bcm2711-hdmi-i2c"; 364 reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>; 365 reg-names = "bsc", "auto-i2c"; 366 clock-frequency = <97500>; 367 status = "disabled"; 368 }; 369 370 hdmi1: hdmi@7ef05700 { 371 compatible = "brcm,bcm2711-hdmi1"; 372 reg = <0x7ef05700 0x300>, 373 <0x7ef05300 0x200>, 374 <0x7ef05f00 0x80>, 375 <0x7ef05f80 0x80>, 376 <0x7ef06b00 0x200>, 377 <0x7ef06f00 0x400>, 378 <0x7ef00280 0x80>, 379 <0x7ef09300 0x100>, 380 <0x7ef20000 0x100>; 381 reg-names = "hdmi", 382 "dvp", 383 "phy", 384 "rm", 385 "packet", 386 "metadata", 387 "csc", 388 "cec", 389 "hd"; 390 ddc = <&ddc1>; 391 clock-names = "hdmi", "bvb", "audio", "cec"; 392 resets = <&dvp 1>; 393 interrupt-parent = <&aon_intr>; 394 interrupts = <8>, <7>, <6>, 395 <9>, <10>, <11>; 396 interrupt-names = "cec-tx", "cec-rx", "cec-low", 397 "wakeup", "hpd-connected", "hpd-removed"; 398 dmas = <&dma 17>; 399 dma-names = "audio-rx"; 400 status = "disabled"; 401 }; 402 403 ddc1: i2c@7ef09500 { 404 compatible = "brcm,bcm2711-hdmi-i2c"; 405 reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>; 406 reg-names = "bsc", "auto-i2c"; 407 clock-frequency = <97500>; 408 status = "disabled"; 409 }; 410 }; 411 412 /* 413 * emmc2 has different DMA constraints based on SoC revisions. It was 414 * moved into its own bus, so as for RPi4's firmware to update them. 415 * The firmware will find whether the emmc2bus alias is defined, and if 416 * so, it'll edit the dma-ranges property below accordingly. 417 */ 418 emmc2bus: emmc2bus { 419 compatible = "simple-bus"; 420 #address-cells = <2>; 421 #size-cells = <1>; 422 423 ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>; 424 dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>; 425 426 emmc2: mmc@7e340000 { 427 compatible = "brcm,bcm2711-emmc2"; 428 reg = <0x0 0x7e340000 0x100>; 429 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&clocks BCM2711_CLOCK_EMMC2>; 431 status = "disabled"; 432 }; 433 }; 434 435 arm-pmu { 436 compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3"; 437 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 441 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 442 }; 443 444 timer { 445 compatible = "arm,armv8-timer"; 446 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 447 IRQ_TYPE_LEVEL_LOW)>, 448 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 449 IRQ_TYPE_LEVEL_LOW)>, 450 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 451 IRQ_TYPE_LEVEL_LOW)>, 452 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 453 IRQ_TYPE_LEVEL_LOW)>; 454 /* This only applies to the ARMv7 stub */ 455 arm,cpu-registers-not-fw-configured; 456 }; 457 458 cpus: cpus { 459 #address-cells = <1>; 460 #size-cells = <0>; 461 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit 462 463 /* Source for d/i-cache-line-size and d/i-cache-sets 464 * https://developer.arm.com/documentation/100095/0003 465 * /Level-1-Memory-System/About-the-L1-memory-system?lang=en 466 * Source for d/i-cache-size 467 * https://www.raspberrypi.com/documentation/computers 468 * /processors.html#bcm2711 469 */ 470 cpu0: cpu@0 { 471 device_type = "cpu"; 472 compatible = "arm,cortex-a72"; 473 reg = <0>; 474 enable-method = "spin-table"; 475 cpu-release-addr = <0x0 0x000000d8>; 476 d-cache-size = <0x8000>; 477 d-cache-line-size = <64>; 478 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 479 i-cache-size = <0xc000>; 480 i-cache-line-size = <64>; 481 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set 482 next-level-cache = <&l2>; 483 }; 484 485 cpu1: cpu@1 { 486 device_type = "cpu"; 487 compatible = "arm,cortex-a72"; 488 reg = <1>; 489 enable-method = "spin-table"; 490 cpu-release-addr = <0x0 0x000000e0>; 491 d-cache-size = <0x8000>; 492 d-cache-line-size = <64>; 493 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 494 i-cache-size = <0xc000>; 495 i-cache-line-size = <64>; 496 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set 497 next-level-cache = <&l2>; 498 }; 499 500 cpu2: cpu@2 { 501 device_type = "cpu"; 502 compatible = "arm,cortex-a72"; 503 reg = <2>; 504 enable-method = "spin-table"; 505 cpu-release-addr = <0x0 0x000000e8>; 506 d-cache-size = <0x8000>; 507 d-cache-line-size = <64>; 508 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 509 i-cache-size = <0xc000>; 510 i-cache-line-size = <64>; 511 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set 512 next-level-cache = <&l2>; 513 }; 514 515 cpu3: cpu@3 { 516 device_type = "cpu"; 517 compatible = "arm,cortex-a72"; 518 reg = <3>; 519 enable-method = "spin-table"; 520 cpu-release-addr = <0x0 0x000000f0>; 521 d-cache-size = <0x8000>; 522 d-cache-line-size = <64>; 523 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 524 i-cache-size = <0xc000>; 525 i-cache-line-size = <64>; 526 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set 527 next-level-cache = <&l2>; 528 }; 529 530 /* Source for d/i-cache-line-size and d/i-cache-sets 531 * https://developer.arm.com/documentation/100095/0003 532 * /Level-2-Memory-System/About-the-L2-memory-system?lang=en 533 * Source for d/i-cache-size 534 * https://www.raspberrypi.com/documentation/computers 535 * /processors.html#bcm2711 536 */ 537 l2: l2-cache0 { 538 compatible = "cache"; 539 cache-size = <0x100000>; 540 cache-line-size = <64>; 541 cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set 542 cache-level = <2>; 543 }; 544 }; 545 546 scb { 547 compatible = "simple-bus"; 548 #address-cells = <2>; 549 #size-cells = <1>; 550 551 ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>, 552 <0x6 0x00000000 0x6 0x00000000 0x40000000>; 553 554 pcie0: pcie@7d500000 { 555 compatible = "brcm,bcm2711-pcie"; 556 reg = <0x0 0x7d500000 0x9310>; 557 device_type = "pci"; 558 #address-cells = <3>; 559 #interrupt-cells = <1>; 560 #size-cells = <2>; 561 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 563 interrupt-names = "pcie", "msi"; 564 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 565 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 566 IRQ_TYPE_LEVEL_HIGH>, 567 <0 0 0 2 &gicv2 GIC_SPI 144 568 IRQ_TYPE_LEVEL_HIGH>, 569 <0 0 0 3 &gicv2 GIC_SPI 145 570 IRQ_TYPE_LEVEL_HIGH>, 571 <0 0 0 4 &gicv2 GIC_SPI 146 572 IRQ_TYPE_LEVEL_HIGH>; 573 msi-controller; 574 msi-parent = <&pcie0>; 575 576 ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 577 0x0 0x04000000>; 578 /* 579 * The wrapper around the PCIe block has a bug 580 * preventing it from accessing beyond the first 3GB of 581 * memory. 582 */ 583 dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 584 0x0 0xc0000000>; 585 brcm,enable-ssc; 586 }; 587 588 genet: ethernet@7d580000 { 589 compatible = "brcm,bcm2711-genet-v5"; 590 reg = <0x0 0x7d580000 0x10000>; 591 #address-cells = <0x1>; 592 #size-cells = <0x1>; 593 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 595 status = "disabled"; 596 597 genet_mdio: mdio@e14 { 598 compatible = "brcm,genet-mdio-v5"; 599 reg = <0xe14 0x8>; 600 reg-names = "mdio"; 601 #address-cells = <0x1>; 602 #size-cells = <0x0>; 603 }; 604 }; 605 606 v3d: gpu@7ec00000 { 607 compatible = "brcm,2711-v3d"; 608 reg = <0x0 0x7ec00000 0x4000>, 609 <0x0 0x7ec04000 0x4000>; 610 reg-names = "hub", "core0"; 611 612 power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>; 613 resets = <&pm BCM2835_RESET_V3D>; 614 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 615 }; 616 }; 617 }; 618 619 &clk_osc { 620 clock-frequency = <54000000>; 621 }; 622 623 &clocks { 624 compatible = "brcm,bcm2711-cprman"; 625 }; 626 627 &cpu_thermal { 628 coefficients = <(-487) 410040>; 629 thermal-sensors = <&thermal>; 630 }; 631 632 &dsi0 { 633 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 634 }; 635 636 &dsi1 { 637 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 638 compatible = "brcm,bcm2711-dsi1"; 639 }; 640 641 &gpio { 642 compatible = "brcm,bcm2711-gpio"; 643 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 647 648 gpio-ranges = <&gpio 0 0 58>; 649 650 gpclk0_gpio49: gpclk0_gpio49 { 651 pin-gpclk { 652 pins = "gpio49"; 653 function = "alt1"; 654 bias-disable; 655 }; 656 }; 657 gpclk1_gpio50: gpclk1_gpio50 { 658 pin-gpclk { 659 pins = "gpio50"; 660 function = "alt1"; 661 bias-disable; 662 }; 663 }; 664 gpclk2_gpio51: gpclk2_gpio51 { 665 pin-gpclk { 666 pins = "gpio51"; 667 function = "alt1"; 668 bias-disable; 669 }; 670 }; 671 672 i2c0_gpio46: i2c0_gpio46 { 673 pin-sda { 674 function = "alt0"; 675 pins = "gpio46"; 676 bias-pull-up; 677 }; 678 pin-scl { 679 function = "alt0"; 680 pins = "gpio47"; 681 bias-disable; 682 }; 683 }; 684 i2c1_gpio46: i2c1_gpio46 { 685 pin-sda { 686 function = "alt1"; 687 pins = "gpio46"; 688 bias-pull-up; 689 }; 690 pin-scl { 691 function = "alt1"; 692 pins = "gpio47"; 693 bias-disable; 694 }; 695 }; 696 i2c3_gpio2: i2c3_gpio2 { 697 pin-sda { 698 function = "alt5"; 699 pins = "gpio2"; 700 bias-pull-up; 701 }; 702 pin-scl { 703 function = "alt5"; 704 pins = "gpio3"; 705 bias-disable; 706 }; 707 }; 708 i2c3_gpio4: i2c3_gpio4 { 709 pin-sda { 710 function = "alt5"; 711 pins = "gpio4"; 712 bias-pull-up; 713 }; 714 pin-scl { 715 function = "alt5"; 716 pins = "gpio5"; 717 bias-disable; 718 }; 719 }; 720 i2c4_gpio6: i2c4_gpio6 { 721 pin-sda { 722 function = "alt5"; 723 pins = "gpio6"; 724 bias-pull-up; 725 }; 726 pin-scl { 727 function = "alt5"; 728 pins = "gpio7"; 729 bias-disable; 730 }; 731 }; 732 i2c4_gpio8: i2c4_gpio8 { 733 pin-sda { 734 function = "alt5"; 735 pins = "gpio8"; 736 bias-pull-up; 737 }; 738 pin-scl { 739 function = "alt5"; 740 pins = "gpio9"; 741 bias-disable; 742 }; 743 }; 744 i2c5_gpio10: i2c5_gpio10 { 745 pin-sda { 746 function = "alt5"; 747 pins = "gpio10"; 748 bias-pull-up; 749 }; 750 pin-scl { 751 function = "alt5"; 752 pins = "gpio11"; 753 bias-disable; 754 }; 755 }; 756 i2c5_gpio12: i2c5_gpio12 { 757 pin-sda { 758 function = "alt5"; 759 pins = "gpio12"; 760 bias-pull-up; 761 }; 762 pin-scl { 763 function = "alt5"; 764 pins = "gpio13"; 765 bias-disable; 766 }; 767 }; 768 i2c6_gpio0: i2c6_gpio0 { 769 pin-sda { 770 function = "alt5"; 771 pins = "gpio0"; 772 bias-pull-up; 773 }; 774 pin-scl { 775 function = "alt5"; 776 pins = "gpio1"; 777 bias-disable; 778 }; 779 }; 780 i2c6_gpio22: i2c6_gpio22 { 781 pin-sda { 782 function = "alt5"; 783 pins = "gpio22"; 784 bias-pull-up; 785 }; 786 pin-scl { 787 function = "alt5"; 788 pins = "gpio23"; 789 bias-disable; 790 }; 791 }; 792 i2c_slave_gpio8: i2c_slave_gpio8 { 793 pins-i2c-slave { 794 pins = "gpio8", 795 "gpio9", 796 "gpio10", 797 "gpio11"; 798 function = "alt3"; 799 }; 800 }; 801 802 jtag_gpio48: jtag_gpio48 { 803 pins-jtag { 804 pins = "gpio48", 805 "gpio49", 806 "gpio50", 807 "gpio51", 808 "gpio52", 809 "gpio53"; 810 function = "alt4"; 811 }; 812 }; 813 814 mii_gpio28: mii_gpio28 { 815 pins-mii { 816 pins = "gpio28", 817 "gpio29", 818 "gpio30", 819 "gpio31"; 820 function = "alt4"; 821 }; 822 }; 823 mii_gpio36: mii_gpio36 { 824 pins-mii { 825 pins = "gpio36", 826 "gpio37", 827 "gpio38", 828 "gpio39"; 829 function = "alt5"; 830 }; 831 }; 832 833 pcm_gpio50: pcm_gpio50 { 834 pins-pcm { 835 pins = "gpio50", 836 "gpio51", 837 "gpio52", 838 "gpio53"; 839 function = "alt2"; 840 }; 841 }; 842 843 pwm0_0_gpio12: pwm0_0_gpio12 { 844 pin-pwm { 845 pins = "gpio12"; 846 function = "alt0"; 847 bias-disable; 848 }; 849 }; 850 pwm0_0_gpio18: pwm0_0_gpio18 { 851 pin-pwm { 852 pins = "gpio18"; 853 function = "alt5"; 854 bias-disable; 855 }; 856 }; 857 pwm1_0_gpio40: pwm1_0_gpio40 { 858 pin-pwm { 859 pins = "gpio40"; 860 function = "alt0"; 861 bias-disable; 862 }; 863 }; 864 pwm0_1_gpio13: pwm0_1_gpio13 { 865 pin-pwm { 866 pins = "gpio13"; 867 function = "alt0"; 868 bias-disable; 869 }; 870 }; 871 pwm0_1_gpio19: pwm0_1_gpio19 { 872 pin-pwm { 873 pins = "gpio19"; 874 function = "alt5"; 875 bias-disable; 876 }; 877 }; 878 pwm1_1_gpio41: pwm1_1_gpio41 { 879 pin-pwm { 880 pins = "gpio41"; 881 function = "alt0"; 882 bias-disable; 883 }; 884 }; 885 pwm0_1_gpio45: pwm0_1_gpio45 { 886 pin-pwm { 887 pins = "gpio45"; 888 function = "alt0"; 889 bias-disable; 890 }; 891 }; 892 pwm0_0_gpio52: pwm0_0_gpio52 { 893 pin-pwm { 894 pins = "gpio52"; 895 function = "alt1"; 896 bias-disable; 897 }; 898 }; 899 pwm0_1_gpio53: pwm0_1_gpio53 { 900 pin-pwm { 901 pins = "gpio53"; 902 function = "alt1"; 903 bias-disable; 904 }; 905 }; 906 907 rgmii_gpio35: rgmii_gpio35 { 908 pin-start-stop { 909 pins = "gpio35"; 910 function = "alt4"; 911 }; 912 pin-rx-ok { 913 pins = "gpio36"; 914 function = "alt4"; 915 }; 916 }; 917 rgmii_irq_gpio34: rgmii_irq_gpio34 { 918 pin-irq { 919 pins = "gpio34"; 920 function = "alt5"; 921 }; 922 }; 923 rgmii_irq_gpio39: rgmii_irq_gpio39 { 924 pin-irq { 925 pins = "gpio39"; 926 function = "alt4"; 927 }; 928 }; 929 rgmii_mdio_gpio28: rgmii_mdio_gpio28 { 930 pins-mdio { 931 pins = "gpio28", 932 "gpio29"; 933 function = "alt5"; 934 }; 935 }; 936 rgmii_mdio_gpio37: rgmii_mdio_gpio37 { 937 pins-mdio { 938 pins = "gpio37", 939 "gpio38"; 940 function = "alt4"; 941 }; 942 }; 943 944 spi0_gpio46: spi0_gpio46 { 945 pins-spi { 946 pins = "gpio46", 947 "gpio47", 948 "gpio48", 949 "gpio49"; 950 function = "alt2"; 951 }; 952 }; 953 spi2_gpio46: spi2_gpio46 { 954 pins-spi { 955 pins = "gpio46", 956 "gpio47", 957 "gpio48", 958 "gpio49", 959 "gpio50"; 960 function = "alt5"; 961 }; 962 }; 963 spi3_gpio0: spi3_gpio0 { 964 pins-spi { 965 pins = "gpio0", 966 "gpio1", 967 "gpio2", 968 "gpio3"; 969 function = "alt3"; 970 }; 971 }; 972 spi4_gpio4: spi4_gpio4 { 973 pins-spi { 974 pins = "gpio4", 975 "gpio5", 976 "gpio6", 977 "gpio7"; 978 function = "alt3"; 979 }; 980 }; 981 spi5_gpio12: spi5_gpio12 { 982 pins-spi { 983 pins = "gpio12", 984 "gpio13", 985 "gpio14", 986 "gpio15"; 987 function = "alt3"; 988 }; 989 }; 990 spi6_gpio18: spi6_gpio18 { 991 pins-spi { 992 pins = "gpio18", 993 "gpio19", 994 "gpio20", 995 "gpio21"; 996 function = "alt3"; 997 }; 998 }; 999 1000 uart2_gpio0: uart2_gpio0 { 1001 pin-tx { 1002 pins = "gpio0"; 1003 function = "alt4"; 1004 bias-disable; 1005 }; 1006 pin-rx { 1007 pins = "gpio1"; 1008 function = "alt4"; 1009 bias-pull-up; 1010 }; 1011 }; 1012 uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 { 1013 pin-cts { 1014 pins = "gpio2"; 1015 function = "alt4"; 1016 bias-pull-up; 1017 }; 1018 pin-rts { 1019 pins = "gpio3"; 1020 function = "alt4"; 1021 bias-disable; 1022 }; 1023 }; 1024 uart3_gpio4: uart3_gpio4 { 1025 pin-tx { 1026 pins = "gpio4"; 1027 function = "alt4"; 1028 bias-disable; 1029 }; 1030 pin-rx { 1031 pins = "gpio5"; 1032 function = "alt4"; 1033 bias-pull-up; 1034 }; 1035 }; 1036 uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 { 1037 pin-cts { 1038 pins = "gpio6"; 1039 function = "alt4"; 1040 bias-pull-up; 1041 }; 1042 pin-rts { 1043 pins = "gpio7"; 1044 function = "alt4"; 1045 bias-disable; 1046 }; 1047 }; 1048 uart4_gpio8: uart4_gpio8 { 1049 pin-tx { 1050 pins = "gpio8"; 1051 function = "alt4"; 1052 bias-disable; 1053 }; 1054 pin-rx { 1055 pins = "gpio9"; 1056 function = "alt4"; 1057 bias-pull-up; 1058 }; 1059 }; 1060 uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 { 1061 pin-cts { 1062 pins = "gpio10"; 1063 function = "alt4"; 1064 bias-pull-up; 1065 }; 1066 pin-rts { 1067 pins = "gpio11"; 1068 function = "alt4"; 1069 bias-disable; 1070 }; 1071 }; 1072 uart5_gpio12: uart5_gpio12 { 1073 pin-tx { 1074 pins = "gpio12"; 1075 function = "alt4"; 1076 bias-disable; 1077 }; 1078 pin-rx { 1079 pins = "gpio13"; 1080 function = "alt4"; 1081 bias-pull-up; 1082 }; 1083 }; 1084 uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 { 1085 pin-cts { 1086 pins = "gpio14"; 1087 function = "alt4"; 1088 bias-pull-up; 1089 }; 1090 pin-rts { 1091 pins = "gpio15"; 1092 function = "alt4"; 1093 bias-disable; 1094 }; 1095 }; 1096 }; 1097 1098 &rmem { 1099 #address-cells = <2>; 1100 }; 1101 1102 &cma { 1103 /* 1104 * arm64 reserves the CMA by default somewhere in ZONE_DMA32, 1105 * that's not good enough for the BCM2711 as some devices can 1106 * only address the lower 1G of memory (ZONE_DMA). 1107 */ 1108 alloc-ranges = <0x0 0x00000000 0x40000000>; 1109 }; 1110 1111 &i2c0 { 1112 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 1113 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1114 }; 1115 1116 &i2c1 { 1117 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 1118 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1119 }; 1120 1121 &mailbox { 1122 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1123 }; 1124 1125 &sdhci { 1126 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1127 }; 1128 1129 &sdhost { 1130 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1131 }; 1132 1133 &spi { 1134 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1135 }; 1136 1137 &spi1 { 1138 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1139 }; 1140 1141 &spi2 { 1142 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1143 }; 1144 1145 &system_timer { 1146 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 1147 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 1149 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1150 }; 1151 1152 &txp { 1153 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1154 }; 1155 1156 &uart0 { 1157 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1158 }; 1159 1160 &uart1 { 1161 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1162 }; 1163 1164 &usb { 1165 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1166 }; 1167 1168 &vec { 1169 compatible = "brcm,bcm2711-vec"; 1170 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1171 };
Cache object: 2ba22091c538b5d3b455fbe6ab627e0e
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