bcm63148.dtsi

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    1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
    2 /*
    3  * Copyright 2022 Broadcom Ltd.
    4  */
    5 
    6 #include <dt-bindings/interrupt-controller/arm-gic.h>
    7 #include <dt-bindings/interrupt-controller/irq.h>
    8 
    9 / {
   10         compatible = "brcm,bcm63148", "brcm,bcmbca";
   11         #address-cells = <1>;
   12         #size-cells = <1>;
   13 
   14         interrupt-parent = <&gic>;
   15 
   16         cpus {
   17                 #address-cells = <1>;
   18                 #size-cells = <0>;
   19 
   20                 B15_0: cpu@0 {
   21                         device_type = "cpu";
   22                         compatible = "brcm,brahma-b15";
   23                         reg = <0x0>;
   24                         next-level-cache = <&L2_0>;
   25                         enable-method = "psci";
   26                 };
   27 
   28                 B15_1: cpu@1 {
   29                         device_type = "cpu";
   30                         compatible = "brcm,brahma-b15";
   31                         reg = <0x1>;
   32                         next-level-cache = <&L2_0>;
   33                         enable-method = "psci";
   34                 };
   35 
   36                 L2_0: l2-cache0 {
   37                         compatible = "cache";
   38                 };
   39         };
   40 
   41         timer {
   42                 compatible = "arm,armv7-timer";
   43                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
   44                         <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
   45                         <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
   46                         <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
   47         };
   48 
   49         pmu: pmu {
   50                 compatible = "arm,cortex-a15-pmu";
   51                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
   52                         <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
   53                 interrupt-affinity = <&B15_0>, <&B15_1>;
   54         };
   55 
   56         clocks: clocks {
   57                 periph_clk: periph-clk {
   58                         compatible = "fixed-clock";
   59                         #clock-cells = <0>;
   60                         clock-frequency = <50000000>;
   61                 };
   62         };
   63 
   64         psci {
   65                 compatible = "arm,psci-0.2";
   66                 method = "smc";
   67         };
   68 
   69         axi@80030000 {
   70                 compatible = "simple-bus";
   71                 #address-cells = <1>;
   72                 #size-cells = <1>;
   73                 ranges = <0 0x80030000 0x8000>;
   74 
   75                 gic: interrupt-controller@1000 {
   76                         compatible = "arm,cortex-a15-gic";
   77                         #interrupt-cells = <3>;
   78                         interrupt-controller;
   79                         reg = <0x1000 0x1000>,
   80                                 <0x2000 0x2000>,
   81                                 <0x4000 0x2000>,
   82                                 <0x6000 0x2000>;
   83                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
   84                                         IRQ_TYPE_LEVEL_HIGH)>;
   85                 };
   86         };
   87 
   88         bus@ff800000 {
   89                 compatible = "simple-bus";
   90                 #address-cells = <1>;
   91                 #size-cells = <1>;
   92                 ranges = <0 0xfffe8000 0x8000>;
   93 
   94                 uart0: serial@600 {
   95                         compatible = "brcm,bcm6345-uart";
   96                         reg = <0x600 0x20>;
   97                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
   98                         clocks = <&periph_clk>;
   99                         clock-names = "refclk";
  100                         status = "disabled";
  101                 };
  102         };
  103 };

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