dra7-l4.dtsi

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    1 &l4_cfg {                                               /* 0x4a000000 */
    2         compatible = "ti,dra7-l4-cfg", "simple-pm-bus";
    3         power-domains = <&prm_coreaon>;
    4         clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;
    5         clock-names = "fck";
    6         reg = <0x4a000000 0x800>,
    7               <0x4a000800 0x800>,
    8               <0x4a001000 0x1000>;
    9         reg-names = "ap", "la", "ia0";
   10         #address-cells = <1>;
   11         #size-cells = <1>;
   12         ranges = <0x00000000 0x4a000000 0x100000>,      /* segment 0 */
   13                  <0x00100000 0x4a100000 0x100000>,      /* segment 1 */
   14                  <0x00200000 0x4a200000 0x100000>;      /* segment 2 */
   15 
   16         segment@0 {                                     /* 0x4a000000 */
   17                 compatible = "simple-pm-bus";
   18                 #address-cells = <1>;
   19                 #size-cells = <1>;
   20                 ranges = <0x00000000 0x00000000 0x000800>,      /* ap 0 */
   21                          <0x00000800 0x00000800 0x000800>,      /* ap 1 */
   22                          <0x00001000 0x00001000 0x001000>,      /* ap 2 */
   23                          <0x00002000 0x00002000 0x002000>,      /* ap 3 */
   24                          <0x00004000 0x00004000 0x001000>,      /* ap 4 */
   25                          <0x00005000 0x00005000 0x001000>,      /* ap 5 */
   26                          <0x00006000 0x00006000 0x001000>,      /* ap 6 */
   27                          <0x00008000 0x00008000 0x002000>,      /* ap 7 */
   28                          <0x0000a000 0x0000a000 0x001000>,      /* ap 8 */
   29                          <0x00056000 0x00056000 0x001000>,      /* ap 9 */
   30                          <0x00057000 0x00057000 0x001000>,      /* ap 10 */
   31                          <0x0005e000 0x0005e000 0x002000>,      /* ap 11 */
   32                          <0x00060000 0x00060000 0x001000>,      /* ap 12 */
   33                          <0x00080000 0x00080000 0x008000>,      /* ap 13 */
   34                          <0x00088000 0x00088000 0x001000>,      /* ap 14 */
   35                          <0x000a0000 0x000a0000 0x008000>,      /* ap 15 */
   36                          <0x000a8000 0x000a8000 0x001000>,      /* ap 16 */
   37                          <0x000d9000 0x000d9000 0x001000>,      /* ap 17 */
   38                          <0x000da000 0x000da000 0x001000>,      /* ap 18 */
   39                          <0x000dd000 0x000dd000 0x001000>,      /* ap 19 */
   40                          <0x000de000 0x000de000 0x001000>,      /* ap 20 */
   41                          <0x000e0000 0x000e0000 0x001000>,      /* ap 21 */
   42                          <0x000e1000 0x000e1000 0x001000>,      /* ap 22 */
   43                          <0x000f4000 0x000f4000 0x001000>,      /* ap 23 */
   44                          <0x000f5000 0x000f5000 0x001000>,      /* ap 24 */
   45                          <0x000f6000 0x000f6000 0x001000>,      /* ap 25 */
   46                          <0x000f7000 0x000f7000 0x001000>,      /* ap 26 */
   47                          <0x00090000 0x00090000 0x008000>,      /* ap 59 */
   48                          <0x00098000 0x00098000 0x001000>;      /* ap 60 */
   49 
   50                 target-module@2000 {                    /* 0x4a002000, ap 3 08.0 */
   51                         compatible = "ti,sysc-omap4", "ti,sysc";
   52                         reg = <0x2000 0x4>;
   53                         reg-names = "rev";
   54                         #address-cells = <1>;
   55                         #size-cells = <1>;
   56                         ranges = <0x0 0x2000 0x2000>;
   57 
   58                         scm: scm@0 {
   59                                 compatible = "ti,dra7-scm-core", "simple-bus";
   60                                 reg = <0 0x2000>;
   61                                 #address-cells = <1>;
   62                                 #size-cells = <1>;
   63                                 ranges = <0 0 0x2000>;
   64 
   65                                 scm_conf: scm_conf@0 {
   66                                         compatible = "syscon", "simple-bus";
   67                                         reg = <0x0 0x1400>;
   68                                         #address-cells = <1>;
   69                                         #size-cells = <1>;
   70                                         ranges = <0 0x0 0x1400>;
   71 
   72                                         pbias_regulator: pbias_regulator@e00 {
   73                                                 compatible = "ti,pbias-dra7", "ti,pbias-omap";
   74                                                 reg = <0xe00 0x4>;
   75                                                 syscon = <&scm_conf>;
   76                                                 pbias_mmc_reg: pbias_mmc_omap5 {
   77                                                         regulator-name = "pbias_mmc_omap5";
   78                                                         regulator-min-microvolt = <1800000>;
   79                                                         regulator-max-microvolt = <3300000>;
   80                                                 };
   81                                         };
   82 
   83                                         phy_gmii_sel: phy-gmii-sel {
   84                                                 compatible = "ti,dra7xx-phy-gmii-sel";
   85                                                 reg = <0x554 0x4>;
   86                                                 #phy-cells = <1>;
   87                                         };
   88 
   89                                         scm_conf_clocks: clocks {
   90                                                 #address-cells = <1>;
   91                                                 #size-cells = <0>;
   92                                         };
   93                                 };
   94 
   95                                 dra7_pmx_core: pinmux@1400 {
   96                                         compatible = "ti,dra7-padconf",
   97                                                      "pinctrl-single";
   98                                         reg = <0x1400 0x0468>;
   99                                         #address-cells = <1>;
  100                                         #size-cells = <0>;
  101                                         #pinctrl-cells = <1>;
  102                                         #interrupt-cells = <1>;
  103                                         interrupt-controller;
  104                                         pinctrl-single,register-width = <32>;
  105                                         pinctrl-single,function-mask = <0x3fffffff>;
  106                                 };
  107 
  108                                 scm_conf1: scm_conf@1c04 {
  109                                         compatible = "syscon";
  110                                         reg = <0x1c04 0x0020>;
  111                                         #syscon-cells = <2>;
  112                                 };
  113 
  114                                 scm_conf_pcie: scm_conf@1c24 {
  115                                         compatible = "syscon";
  116                                         reg = <0x1c24 0x0024>;
  117                                 };
  118 
  119                                 sdma_xbar: dma-router@b78 {
  120                                         compatible = "ti,dra7-dma-crossbar";
  121                                         reg = <0xb78 0xfc>;
  122                                         #dma-cells = <1>;
  123                                         dma-requests = <205>;
  124                                         ti,dma-safe-map = <0>;
  125                                         dma-masters = <&sdma>;
  126                                 };
  127 
  128                                 edma_xbar: dma-router@c78 {
  129                                         compatible = "ti,dra7-dma-crossbar";
  130                                         reg = <0xc78 0x7c>;
  131                                         #dma-cells = <2>;
  132                                         dma-requests = <204>;
  133                                         ti,dma-safe-map = <0>;
  134                                         dma-masters = <&edma>;
  135                                 };
  136                         };
  137                 };
  138 
  139                 target-module@5000 {                    /* 0x4a005000, ap 5 10.0 */
  140                         compatible = "ti,sysc-omap4", "ti,sysc";
  141                         reg = <0x5000 0x4>;
  142                         reg-names = "rev";
  143                         #address-cells = <1>;
  144                         #size-cells = <1>;
  145                         ranges = <0x0 0x5000 0x1000>;
  146 
  147                         cm_core_aon: cm_core_aon@0 {
  148                                 compatible = "ti,dra7-cm-core-aon",
  149                                               "simple-bus";
  150                                 #address-cells = <1>;
  151                                 #size-cells = <1>;
  152                                 reg = <0 0x2000>;
  153                                 ranges = <0 0 0x2000>;
  154 
  155                                 cm_core_aon_clocks: clocks {
  156                                         #address-cells = <1>;
  157                                         #size-cells = <0>;
  158                                 };
  159 
  160                                 cm_core_aon_clockdomains: clockdomains {
  161                                 };
  162                         };
  163                 };
  164 
  165                 target-module@8000 {                    /* 0x4a008000, ap 7 0e.0 */
  166                         compatible = "ti,sysc-omap4", "ti,sysc";
  167                         reg = <0x8000 0x4>;
  168                         reg-names = "rev";
  169                         #address-cells = <1>;
  170                         #size-cells = <1>;
  171                         ranges = <0x0 0x8000 0x2000>;
  172 
  173                         cm_core: cm_core@0 {
  174                                 compatible = "ti,dra7-cm-core", "simple-bus";
  175                                 #address-cells = <1>;
  176                                 #size-cells = <1>;
  177                                 reg = <0 0x3000>;
  178                                 ranges = <0 0 0x3000>;
  179 
  180                                 cm_core_clocks: clocks {
  181                                         #address-cells = <1>;
  182                                         #size-cells = <0>;
  183                                 };
  184 
  185                                 cm_core_clockdomains: clockdomains {
  186                                 };
  187                         };
  188                 };
  189 
  190                 target-module@56000 {                   /* 0x4a056000, ap 9 02.0 */
  191                         compatible = "ti,sysc-omap2", "ti,sysc";
  192                         reg = <0x56000 0x4>,
  193                               <0x5602c 0x4>,
  194                               <0x56028 0x4>;
  195                         reg-names = "rev", "sysc", "syss";
  196                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  197                                          SYSC_OMAP2_EMUFREE |
  198                                          SYSC_OMAP2_SOFTRESET |
  199                                          SYSC_OMAP2_AUTOIDLE)>;
  200                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
  201                                         <SYSC_IDLE_NO>,
  202                                         <SYSC_IDLE_SMART>,
  203                                         <SYSC_IDLE_SMART_WKUP>;
  204                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  205                                         <SYSC_IDLE_NO>,
  206                                         <SYSC_IDLE_SMART>,
  207                                         <SYSC_IDLE_SMART_WKUP>;
  208                         ti,syss-mask = <1>;
  209                         /* Domains (P, C): core_pwrdm, dma_clkdm */
  210                         clocks = <&dma_clkctrl DRA7_DMA_DMA_SYSTEM_CLKCTRL 0>;
  211                         clock-names = "fck";
  212                         #address-cells = <1>;
  213                         #size-cells = <1>;
  214                         ranges = <0x0 0x56000 0x1000>;
  215 
  216                         sdma: dma-controller@0 {
  217                                 compatible = "ti,omap4430-sdma", "ti,omap-sdma";
  218                                 reg = <0x0 0x1000>;
  219                                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
  220                                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
  221                                              <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
  222                                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
  223                                 #dma-cells = <1>;
  224                                 dma-channels = <32>;
  225                                 dma-requests = <127>;
  226                         };
  227                 };
  228 
  229                 target-module@5e000 {                   /* 0x4a05e000, ap 11 1a.0 */
  230                         compatible = "ti,sysc";
  231                         status = "disabled";
  232                         #address-cells = <1>;
  233                         #size-cells = <1>;
  234                         ranges = <0x0 0x5e000 0x2000>;
  235                 };
  236 
  237                 target-module@80000 {                   /* 0x4a080000, ap 13 20.0 */
  238                         compatible = "ti,sysc-omap2", "ti,sysc";
  239                         reg = <0x80000 0x4>,
  240                               <0x80010 0x4>,
  241                               <0x80014 0x4>;
  242                         reg-names = "rev", "sysc", "syss";
  243                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
  244                                          SYSC_OMAP2_AUTOIDLE)>;
  245                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  246                                         <SYSC_IDLE_NO>,
  247                                         <SYSC_IDLE_SMART>;
  248                         ti,syss-mask = <1>;
  249                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
  250                         clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP1_CLKCTRL 0>;
  251                         clock-names = "fck";
  252                         #address-cells = <1>;
  253                         #size-cells = <1>;
  254                         ranges = <0x0 0x80000 0x8000>;
  255 
  256                         ocp2scp@0 {
  257                                 compatible = "ti,omap-ocp2scp";
  258                                 #address-cells = <1>;
  259                                 #size-cells = <1>;
  260                                 ranges = <0 0 0x8000>;
  261                                 reg = <0x0 0x20>;
  262 
  263                                 usb2_phy1: phy@4000 {
  264                                         compatible = "ti,dra7x-usb2", "ti,omap-usb2";
  265                                         reg = <0x4000 0x400>;
  266                                         syscon-phy-power = <&scm_conf 0x300>;
  267                                         clocks = <&usb_phy1_always_on_clk32k>,
  268                                                  <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>;
  269                                         clock-names =   "wkupclk",
  270                                                         "refclk";
  271                                         #phy-cells = <0>;
  272                                 };
  273 
  274                                 usb2_phy2: phy@5000 {
  275                                         compatible = "ti,dra7x-usb2-phy2",
  276                                                      "ti,omap-usb2";
  277                                         reg = <0x5000 0x400>;
  278                                         syscon-phy-power = <&scm_conf 0xe74>;
  279                                         clocks = <&usb_phy2_always_on_clk32k>,
  280                                                  <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 8>;
  281                                         clock-names =   "wkupclk",
  282                                                         "refclk";
  283                                         #phy-cells = <0>;
  284                                 };
  285 
  286                                 usb3_phy1: phy@4400 {
  287                                         compatible = "ti,omap-usb3";
  288                                         reg = <0x4400 0x80>,
  289                                               <0x4800 0x64>,
  290                                               <0x4c00 0x40>;
  291                                         reg-names = "phy_rx", "phy_tx", "pll_ctrl";
  292                                         syscon-phy-power = <&scm_conf 0x370>;
  293                                         clocks = <&usb_phy3_always_on_clk32k>,
  294                                                  <&sys_clkin1>,
  295                                                  <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>;
  296                                         clock-names =   "wkupclk",
  297                                                         "sysclk",
  298                                                         "refclk";
  299                                         #phy-cells = <0>;
  300                                 };
  301                         };
  302                 };
  303 
  304                 target-module@90000 {                   /* 0x4a090000, ap 59 42.0 */
  305                         compatible = "ti,sysc-omap2", "ti,sysc";
  306                         reg = <0x90000 0x4>,
  307                               <0x90010 0x4>,
  308                               <0x90014 0x4>;
  309                         reg-names = "rev", "sysc", "syss";
  310                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
  311                                          SYSC_OMAP2_AUTOIDLE)>;
  312                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  313                                         <SYSC_IDLE_NO>,
  314                                         <SYSC_IDLE_SMART>;
  315                         ti,syss-mask = <1>;
  316                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
  317                         clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP3_CLKCTRL 0>;
  318                         clock-names = "fck";
  319                         #address-cells = <1>;
  320                         #size-cells = <1>;
  321                         ranges = <0x0 0x90000 0x8000>;
  322 
  323                         ocp2scp@0 {
  324                                 compatible = "ti,omap-ocp2scp";
  325                                 #address-cells = <1>;
  326                                 #size-cells = <1>;
  327                                 ranges = <0 0 0x8000>;
  328                                 reg = <0x0 0x20>;
  329 
  330                                 pcie1_phy: pciephy@4000 {
  331                                         compatible = "ti,phy-pipe3-pcie";
  332                                         reg = <0x4000 0x80>, /* phy_rx */
  333                                               <0x4400 0x64>; /* phy_tx */
  334                                         reg-names = "phy_rx", "phy_tx";
  335                                         syscon-phy-power = <&scm_conf_pcie 0x1c>;
  336                                         syscon-pcs = <&scm_conf_pcie 0x10>;
  337                                         clocks = <&dpll_pcie_ref_ck>,
  338                                                  <&dpll_pcie_ref_m2ldo_ck>,
  339                                                  <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 8>,
  340                                                  <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>,
  341                                                  <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>,
  342                                                  <&optfclk_pciephy_div>,
  343                                                  <&sys_clkin1>;
  344                                         clock-names = "dpll_ref", "dpll_ref_m2",
  345                                                       "wkupclk", "refclk",
  346                                                       "div-clk", "phy-div", "sysclk";
  347                                         #phy-cells = <0>;
  348                                 };
  349 
  350                                 pcie2_phy: pciephy@5000 {
  351                                         compatible = "ti,phy-pipe3-pcie";
  352                                         reg = <0x5000 0x80>, /* phy_rx */
  353                                               <0x5400 0x64>; /* phy_tx */
  354                                         reg-names = "phy_rx", "phy_tx";
  355                                         syscon-phy-power = <&scm_conf_pcie 0x20>;
  356                                         syscon-pcs = <&scm_conf_pcie 0x10>;
  357                                         clocks = <&dpll_pcie_ref_ck>,
  358                                                  <&dpll_pcie_ref_m2ldo_ck>,
  359                                                  <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 8>,
  360                                                  <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>,
  361                                                  <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>,
  362                                                  <&optfclk_pciephy_div>,
  363                                                  <&sys_clkin1>;
  364                                         clock-names = "dpll_ref", "dpll_ref_m2",
  365                                                       "wkupclk", "refclk",
  366                                                       "div-clk", "phy-div", "sysclk";
  367                                         #phy-cells = <0>;
  368                                         status = "disabled";
  369                                 };
  370 
  371                                 sata_phy: phy@6000 {
  372                                         compatible = "ti,phy-pipe3-sata";
  373                                         reg = <0x6000 0x80>, /* phy_rx */
  374                                               <0x6400 0x64>, /* phy_tx */
  375                                               <0x6800 0x40>; /* pll_ctrl */
  376                                         reg-names = "phy_rx", "phy_tx", "pll_ctrl";
  377                                         syscon-phy-power = <&scm_conf 0x374>;
  378                                         clocks = <&sys_clkin1>,
  379                                                  <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
  380                                         clock-names = "sysclk", "refclk";
  381                                         syscon-pllreset = <&scm_conf 0x3fc>;
  382                                         #phy-cells = <0>;
  383                                 };
  384                         };
  385                 };
  386 
  387                 target-module@a0000 {                   /* 0x4a0a0000, ap 15 40.0 */
  388                         compatible = "ti,sysc";
  389                         status = "disabled";
  390                         #address-cells = <1>;
  391                         #size-cells = <1>;
  392                         ranges = <0x0 0xa0000 0x8000>;
  393                 };
  394 
  395                 target-module@d9000 {                   /* 0x4a0d9000, ap 17 72.0 */
  396                         compatible = "ti,sysc-omap4-sr", "ti,sysc";
  397                         reg = <0xd9038 0x4>;
  398                         reg-names = "sysc";
  399                         ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
  400                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  401                                         <SYSC_IDLE_NO>,
  402                                         <SYSC_IDLE_SMART>,
  403                                         <SYSC_IDLE_SMART_WKUP>;
  404                         /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */
  405                         clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL 0>;
  406                         clock-names = "fck";
  407                         #address-cells = <1>;
  408                         #size-cells = <1>;
  409                         ranges = <0x0 0xd9000 0x1000>;
  410 
  411                         /* SmartReflex child device marked reserved in TRM */
  412                 };
  413 
  414                 target-module@dd000 {                   /* 0x4a0dd000, ap 19 18.0 */
  415                         compatible = "ti,sysc-omap4-sr", "ti,sysc";
  416                         reg = <0xdd038 0x4>;
  417                         reg-names = "sysc";
  418                         ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
  419                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  420                                         <SYSC_IDLE_NO>,
  421                                         <SYSC_IDLE_SMART>,
  422                                         <SYSC_IDLE_SMART_WKUP>;
  423                         /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */
  424                         clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL 0>;
  425                         clock-names = "fck";
  426                         #address-cells = <1>;
  427                         #size-cells = <1>;
  428                         ranges = <0x0 0xdd000 0x1000>;
  429 
  430                         /* SmartReflex child device marked reserved in TRM */
  431                 };
  432 
  433                 target-module@e0000 {                   /* 0x4a0e0000, ap 21 28.0 */
  434                         compatible = "ti,sysc";
  435                         status = "disabled";
  436                         #address-cells = <1>;
  437                         #size-cells = <1>;
  438                         ranges = <0x0 0xe0000 0x1000>;
  439                 };
  440 
  441                 target-module@f4000 {                   /* 0x4a0f4000, ap 23 04.0 */
  442                         compatible = "ti,sysc-omap4", "ti,sysc";
  443                         reg = <0xf4000 0x4>,
  444                               <0xf4010 0x4>;
  445                         reg-names = "rev", "sysc";
  446                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
  447                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  448                                         <SYSC_IDLE_NO>,
  449                                         <SYSC_IDLE_SMART>;
  450                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
  451                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX1_CLKCTRL 0>;
  452                         clock-names = "fck";
  453                         #address-cells = <1>;
  454                         #size-cells = <1>;
  455                         ranges = <0x0 0xf4000 0x1000>;
  456 
  457                         mailbox1: mailbox@0 {
  458                                 compatible = "ti,omap4-mailbox";
  459                                 reg = <0x0 0x200>;
  460                                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
  461                                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
  462                                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
  463                                 #mbox-cells = <1>;
  464                                 ti,mbox-num-users = <3>;
  465                                 ti,mbox-num-fifos = <8>;
  466                                 status = "disabled";
  467                         };
  468                 };
  469 
  470                 target-module@f6000 {                   /* 0x4a0f6000, ap 25 78.0 */
  471                         compatible = "ti,sysc-omap2", "ti,sysc";
  472                         reg = <0xf6000 0x4>,
  473                               <0xf6010 0x4>,
  474                               <0xf6014 0x4>;
  475                         reg-names = "rev", "sysc", "syss";
  476                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
  477                                          SYSC_OMAP2_SOFTRESET |
  478                                          SYSC_OMAP2_AUTOIDLE)>;
  479                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  480                                         <SYSC_IDLE_NO>,
  481                                         <SYSC_IDLE_SMART>;
  482                         ti,syss-mask = <1>;
  483                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
  484                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_SPINLOCK_CLKCTRL 0>;
  485                         clock-names = "fck";
  486                         #address-cells = <1>;
  487                         #size-cells = <1>;
  488                         ranges = <0x0 0xf6000 0x1000>;
  489 
  490                         hwspinlock: spinlock@0 {
  491                                 compatible = "ti,omap4-hwspinlock";
  492                                 reg = <0x0 0x1000>;
  493                                 #hwlock-cells = <1>;
  494                         };
  495                 };
  496         };
  497 
  498         segment@100000 {                                        /* 0x4a100000 */
  499                 compatible = "simple-pm-bus";
  500                 #address-cells = <1>;
  501                 #size-cells = <1>;
  502                 ranges = <0x00002000 0x00102000 0x001000>,      /* ap 27 */
  503                          <0x00003000 0x00103000 0x001000>,      /* ap 28 */
  504                          <0x00008000 0x00108000 0x001000>,      /* ap 29 */
  505                          <0x00009000 0x00109000 0x001000>,      /* ap 30 */
  506                          <0x00040000 0x00140000 0x010000>,      /* ap 31 */
  507                          <0x00050000 0x00150000 0x001000>,      /* ap 32 */
  508                          <0x00051000 0x00151000 0x001000>,      /* ap 33 */
  509                          <0x00052000 0x00152000 0x001000>,      /* ap 34 */
  510                          <0x00053000 0x00153000 0x001000>,      /* ap 35 */
  511                          <0x00054000 0x00154000 0x001000>,      /* ap 36 */
  512                          <0x00055000 0x00155000 0x001000>,      /* ap 37 */
  513                          <0x00056000 0x00156000 0x001000>,      /* ap 38 */
  514                          <0x00057000 0x00157000 0x001000>,      /* ap 39 */
  515                          <0x00058000 0x00158000 0x001000>,      /* ap 40 */
  516                          <0x0005b000 0x0015b000 0x001000>,      /* ap 41 */
  517                          <0x0005c000 0x0015c000 0x001000>,      /* ap 42 */
  518                          <0x0005d000 0x0015d000 0x001000>,      /* ap 45 */
  519                          <0x0005e000 0x0015e000 0x001000>,      /* ap 46 */
  520                          <0x0005f000 0x0015f000 0x001000>,      /* ap 47 */
  521                          <0x00060000 0x00160000 0x001000>,      /* ap 48 */
  522                          <0x00061000 0x00161000 0x001000>,      /* ap 49 */
  523                          <0x00062000 0x00162000 0x001000>,      /* ap 50 */
  524                          <0x00063000 0x00163000 0x001000>,      /* ap 51 */
  525                          <0x00064000 0x00164000 0x001000>,      /* ap 52 */
  526                          <0x00065000 0x00165000 0x001000>,      /* ap 53 */
  527                          <0x00066000 0x00166000 0x001000>,      /* ap 54 */
  528                          <0x00067000 0x00167000 0x001000>,      /* ap 55 */
  529                          <0x00068000 0x00168000 0x001000>,      /* ap 56 */
  530                          <0x0006d000 0x0016d000 0x001000>,      /* ap 57 */
  531                          <0x0006e000 0x0016e000 0x001000>,      /* ap 58 */
  532                          <0x00071000 0x00171000 0x001000>,      /* ap 61 */
  533                          <0x00072000 0x00172000 0x001000>,      /* ap 62 */
  534                          <0x00073000 0x00173000 0x001000>,      /* ap 63 */
  535                          <0x00074000 0x00174000 0x001000>,      /* ap 64 */
  536                          <0x00075000 0x00175000 0x001000>,      /* ap 65 */
  537                          <0x00076000 0x00176000 0x001000>,      /* ap 66 */
  538                          <0x00077000 0x00177000 0x001000>,      /* ap 67 */
  539                          <0x00078000 0x00178000 0x001000>,      /* ap 68 */
  540                          <0x00081000 0x00181000 0x001000>,      /* ap 69 */
  541                          <0x00082000 0x00182000 0x001000>,      /* ap 70 */
  542                          <0x00083000 0x00183000 0x001000>,      /* ap 71 */
  543                          <0x00084000 0x00184000 0x001000>,      /* ap 72 */
  544                          <0x00085000 0x00185000 0x001000>,      /* ap 73 */
  545                          <0x00086000 0x00186000 0x001000>,      /* ap 74 */
  546                          <0x00087000 0x00187000 0x001000>,      /* ap 75 */
  547                          <0x00088000 0x00188000 0x001000>,      /* ap 76 */
  548                          <0x00069000 0x00169000 0x001000>,      /* ap 103 */
  549                          <0x0006a000 0x0016a000 0x001000>,      /* ap 104 */
  550                          <0x00079000 0x00179000 0x001000>,      /* ap 105 */
  551                          <0x0007a000 0x0017a000 0x001000>,      /* ap 106 */
  552                          <0x0006b000 0x0016b000 0x001000>,      /* ap 107 */
  553                          <0x0006c000 0x0016c000 0x001000>,      /* ap 108 */
  554                          <0x0007b000 0x0017b000 0x001000>,      /* ap 121 */
  555                          <0x0007c000 0x0017c000 0x001000>,      /* ap 122 */
  556                          <0x0007d000 0x0017d000 0x001000>,      /* ap 123 */
  557                          <0x0007e000 0x0017e000 0x001000>,      /* ap 124 */
  558                          <0x00059000 0x00159000 0x001000>,      /* ap 125 */
  559                          <0x0005a000 0x0015a000 0x001000>;      /* ap 126 */
  560 
  561                 target-module@2000 {                    /* 0x4a102000, ap 27 3c.0 */
  562                         compatible = "ti,sysc";
  563                         status = "disabled";
  564                         #address-cells = <1>;
  565                         #size-cells = <1>;
  566                         ranges = <0x0 0x2000 0x1000>;
  567                 };
  568 
  569                 target-module@8000 {                    /* 0x4a108000, ap 29 1e.0 */
  570                         compatible = "ti,sysc";
  571                         status = "disabled";
  572                         #address-cells = <1>;
  573                         #size-cells = <1>;
  574                         ranges = <0x0 0x8000 0x1000>;
  575                 };
  576 
  577                 target-module@40000 {                   /* 0x4a140000, ap 31 06.0 */
  578                         compatible = "ti,sysc-omap4", "ti,sysc";
  579                         reg = <0x400fc 4>,
  580                               <0x41100 4>;
  581                         reg-names = "rev", "sysc";
  582                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
  583                                         <SYSC_IDLE_NO>,
  584                                         <SYSC_IDLE_SMART>;
  585                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  586                                         <SYSC_IDLE_NO>,
  587                                         <SYSC_IDLE_SMART>,
  588                                         <SYSC_IDLE_SMART_WKUP>;
  589                         power-domains = <&prm_l3init>;
  590                         clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 0>;
  591                         clock-names = "fck";
  592                         #size-cells = <1>;
  593                         #address-cells = <1>;
  594                         ranges = <0x0 0x40000 0x10000>;
  595 
  596                         sata: sata@0 {
  597                                 compatible = "snps,dwc-ahci";
  598                                 reg = <0 0x1100>, <0x1100 0x8>;
  599                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
  600                                 phys = <&sata_phy>;
  601                                 phy-names = "sata-phy";
  602                                 clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
  603                                 ports-implemented = <0x1>;
  604                         };
  605                 };
  606 
  607                 target-module@51000 {                   /* 0x4a151000, ap 33 50.0 */
  608                         compatible = "ti,sysc";
  609                         status = "disabled";
  610                         #address-cells = <1>;
  611                         #size-cells = <1>;
  612                         ranges = <0x0 0x51000 0x1000>;
  613                 };
  614 
  615                 target-module@53000 {                   /* 0x4a153000, ap 35 54.0 */
  616                         compatible = "ti,sysc";
  617                         status = "disabled";
  618                         #address-cells = <1>;
  619                         #size-cells = <1>;
  620                         ranges = <0x0 0x53000 0x1000>;
  621                 };
  622 
  623                 target-module@55000 {                   /* 0x4a155000, ap 37 46.0 */
  624                         compatible = "ti,sysc";
  625                         status = "disabled";
  626                         #address-cells = <1>;
  627                         #size-cells = <1>;
  628                         ranges = <0x0 0x55000 0x1000>;
  629                 };
  630 
  631                 target-module@57000 {                   /* 0x4a157000, ap 39 58.0 */
  632                         compatible = "ti,sysc";
  633                         status = "disabled";
  634                         #address-cells = <1>;
  635                         #size-cells = <1>;
  636                         ranges = <0x0 0x57000 0x1000>;
  637                 };
  638 
  639                 target-module@59000 {                   /* 0x4a159000, ap 125 6a.0 */
  640                         compatible = "ti,sysc";
  641                         status = "disabled";
  642                         #address-cells = <1>;
  643                         #size-cells = <1>;
  644                         ranges = <0x0 0x59000 0x1000>;
  645                 };
  646 
  647                 target-module@5b000 {                   /* 0x4a15b000, ap 41 60.0 */
  648                         compatible = "ti,sysc";
  649                         status = "disabled";
  650                         #address-cells = <1>;
  651                         #size-cells = <1>;
  652                         ranges = <0x0 0x5b000 0x1000>;
  653                 };
  654 
  655                 target-module@5d000 {                   /* 0x4a15d000, ap 45 3a.0 */
  656                         compatible = "ti,sysc";
  657                         status = "disabled";
  658                         #address-cells = <1>;
  659                         #size-cells = <1>;
  660                         ranges = <0x0 0x5d000 0x1000>;
  661                 };
  662 
  663                 target-module@5f000 {                   /* 0x4a15f000, ap 47 56.0 */
  664                         compatible = "ti,sysc";
  665                         status = "disabled";
  666                         #address-cells = <1>;
  667                         #size-cells = <1>;
  668                         ranges = <0x0 0x5f000 0x1000>;
  669                 };
  670 
  671                 target-module@61000 {                   /* 0x4a161000, ap 49 32.0 */
  672                         compatible = "ti,sysc";
  673                         status = "disabled";
  674                         #address-cells = <1>;
  675                         #size-cells = <1>;
  676                         ranges = <0x0 0x61000 0x1000>;
  677                 };
  678 
  679                 target-module@63000 {                   /* 0x4a163000, ap 51 5c.0 */
  680                         compatible = "ti,sysc";
  681                         status = "disabled";
  682                         #address-cells = <1>;
  683                         #size-cells = <1>;
  684                         ranges = <0x0 0x63000 0x1000>;
  685                 };
  686 
  687                 target-module@65000 {                   /* 0x4a165000, ap 53 4e.0 */
  688                         compatible = "ti,sysc";
  689                         status = "disabled";
  690                         #address-cells = <1>;
  691                         #size-cells = <1>;
  692                         ranges = <0x0 0x65000 0x1000>;
  693                 };
  694 
  695                 target-module@67000 {                   /* 0x4a167000, ap 55 5e.0 */
  696                         compatible = "ti,sysc";
  697                         status = "disabled";
  698                         #address-cells = <1>;
  699                         #size-cells = <1>;
  700                         ranges = <0x0 0x67000 0x1000>;
  701                 };
  702 
  703                 target-module@69000 {                   /* 0x4a169000, ap 103 4a.0 */
  704                         compatible = "ti,sysc";
  705                         status = "disabled";
  706                         #address-cells = <1>;
  707                         #size-cells = <1>;
  708                         ranges = <0x0 0x69000 0x1000>;
  709                 };
  710 
  711                 target-module@6b000 {                   /* 0x4a16b000, ap 107 52.0 */
  712                         compatible = "ti,sysc";
  713                         status = "disabled";
  714                         #address-cells = <1>;
  715                         #size-cells = <1>;
  716                         ranges = <0x0 0x6b000 0x1000>;
  717                 };
  718 
  719                 target-module@6d000 {                   /* 0x4a16d000, ap 57 68.0 */
  720                         compatible = "ti,sysc";
  721                         status = "disabled";
  722                         #address-cells = <1>;
  723                         #size-cells = <1>;
  724                         ranges = <0x0 0x6d000 0x1000>;
  725                 };
  726 
  727                 target-module@71000 {                   /* 0x4a171000, ap 61 48.0 */
  728                         compatible = "ti,sysc";
  729                         status = "disabled";
  730                         #address-cells = <1>;
  731                         #size-cells = <1>;
  732                         ranges = <0x0 0x71000 0x1000>;
  733                 };
  734 
  735                 target-module@73000 {                   /* 0x4a173000, ap 63 2a.0 */
  736                         compatible = "ti,sysc";
  737                         status = "disabled";
  738                         #address-cells = <1>;
  739                         #size-cells = <1>;
  740                         ranges = <0x0 0x73000 0x1000>;
  741                 };
  742 
  743                 target-module@75000 {                   /* 0x4a175000, ap 65 64.0 */
  744                         compatible = "ti,sysc";
  745                         status = "disabled";
  746                         #address-cells = <1>;
  747                         #size-cells = <1>;
  748                         ranges = <0x0 0x75000 0x1000>;
  749                 };
  750 
  751                 target-module@77000 {                   /* 0x4a177000, ap 67 66.0 */
  752                         compatible = "ti,sysc";
  753                         status = "disabled";
  754                         #address-cells = <1>;
  755                         #size-cells = <1>;
  756                         ranges = <0x0 0x77000 0x1000>;
  757                 };
  758 
  759                 target-module@79000 {                   /* 0x4a179000, ap 105 34.0 */
  760                         compatible = "ti,sysc";
  761                         status = "disabled";
  762                         #address-cells = <1>;
  763                         #size-cells = <1>;
  764                         ranges = <0x0 0x79000 0x1000>;
  765                 };
  766 
  767                 target-module@7b000 {                   /* 0x4a17b000, ap 121 7c.0 */
  768                         compatible = "ti,sysc";
  769                         status = "disabled";
  770                         #address-cells = <1>;
  771                         #size-cells = <1>;
  772                         ranges = <0x0 0x7b000 0x1000>;
  773                 };
  774 
  775                 target-module@7d000 {                   /* 0x4a17d000, ap 123 7e.0 */
  776                         compatible = "ti,sysc";
  777                         status = "disabled";
  778                         #address-cells = <1>;
  779                         #size-cells = <1>;
  780                         ranges = <0x0 0x7d000 0x1000>;
  781                 };
  782 
  783                 target-module@81000 {                   /* 0x4a181000, ap 69 26.0 */
  784                         compatible = "ti,sysc";
  785                         status = "disabled";
  786                         #address-cells = <1>;
  787                         #size-cells = <1>;
  788                         ranges = <0x0 0x81000 0x1000>;
  789                 };
  790 
  791                 target-module@83000 {                   /* 0x4a183000, ap 71 2e.0 */
  792                         compatible = "ti,sysc";
  793                         status = "disabled";
  794                         #address-cells = <1>;
  795                         #size-cells = <1>;
  796                         ranges = <0x0 0x83000 0x1000>;
  797                 };
  798 
  799                 target-module@85000 {                   /* 0x4a185000, ap 73 36.0 */
  800                         compatible = "ti,sysc";
  801                         status = "disabled";
  802                         #address-cells = <1>;
  803                         #size-cells = <1>;
  804                         ranges = <0x0 0x85000 0x1000>;
  805                 };
  806 
  807                 target-module@87000 {                   /* 0x4a187000, ap 75 74.0 */
  808                         compatible = "ti,sysc";
  809                         status = "disabled";
  810                         #address-cells = <1>;
  811                         #size-cells = <1>;
  812                         ranges = <0x0 0x87000 0x1000>;
  813                 };
  814         };
  815 
  816         segment@200000 {                                        /* 0x4a200000 */
  817                 compatible = "simple-pm-bus";
  818                 #address-cells = <1>;
  819                 #size-cells = <1>;
  820                 ranges = <0x00018000 0x00218000 0x001000>,      /* ap 43 */
  821                          <0x00019000 0x00219000 0x001000>,      /* ap 44 */
  822                          <0x00000000 0x00200000 0x001000>,      /* ap 77 */
  823                          <0x00001000 0x00201000 0x001000>,      /* ap 78 */
  824                          <0x0000a000 0x0020a000 0x001000>,      /* ap 79 */
  825                          <0x0000b000 0x0020b000 0x001000>,      /* ap 80 */
  826                          <0x0000c000 0x0020c000 0x001000>,      /* ap 81 */
  827                          <0x0000d000 0x0020d000 0x001000>,      /* ap 82 */
  828                          <0x0000e000 0x0020e000 0x001000>,      /* ap 83 */
  829                          <0x0000f000 0x0020f000 0x001000>,      /* ap 84 */
  830                          <0x00010000 0x00210000 0x001000>,      /* ap 85 */
  831                          <0x00011000 0x00211000 0x001000>,      /* ap 86 */
  832                          <0x00012000 0x00212000 0x001000>,      /* ap 87 */
  833                          <0x00013000 0x00213000 0x001000>,      /* ap 88 */
  834                          <0x00014000 0x00214000 0x001000>,      /* ap 89 */
  835                          <0x00015000 0x00215000 0x001000>,      /* ap 90 */
  836                          <0x0002a000 0x0022a000 0x001000>,      /* ap 91 */
  837                          <0x0002b000 0x0022b000 0x001000>,      /* ap 92 */
  838                          <0x0001c000 0x0021c000 0x001000>,      /* ap 93 */
  839                          <0x0001d000 0x0021d000 0x001000>,      /* ap 94 */
  840                          <0x0001e000 0x0021e000 0x001000>,      /* ap 95 */
  841                          <0x0001f000 0x0021f000 0x001000>,      /* ap 96 */
  842                          <0x00020000 0x00220000 0x001000>,      /* ap 97 */
  843                          <0x00021000 0x00221000 0x001000>,      /* ap 98 */
  844                          <0x00024000 0x00224000 0x001000>,      /* ap 99 */
  845                          <0x00025000 0x00225000 0x001000>,      /* ap 100 */
  846                          <0x00026000 0x00226000 0x001000>,      /* ap 101 */
  847                          <0x00027000 0x00227000 0x001000>,      /* ap 102 */
  848                          <0x0002c000 0x0022c000 0x001000>,      /* ap 109 */
  849                          <0x0002d000 0x0022d000 0x001000>,      /* ap 110 */
  850                          <0x0002e000 0x0022e000 0x001000>,      /* ap 111 */
  851                          <0x0002f000 0x0022f000 0x001000>,      /* ap 112 */
  852                          <0x00030000 0x00230000 0x001000>,      /* ap 113 */
  853                          <0x00031000 0x00231000 0x001000>,      /* ap 114 */
  854                          <0x00032000 0x00232000 0x001000>,      /* ap 115 */
  855                          <0x00033000 0x00233000 0x001000>,      /* ap 116 */
  856                          <0x00034000 0x00234000 0x001000>,      /* ap 117 */
  857                          <0x00035000 0x00235000 0x001000>,      /* ap 118 */
  858                          <0x00036000 0x00236000 0x001000>,      /* ap 119 */
  859                          <0x00037000 0x00237000 0x001000>,      /* ap 120 */
  860                          <0x0001a000 0x0021a000 0x001000>,      /* ap 127 */
  861                          <0x0001b000 0x0021b000 0x001000>;      /* ap 128 */
  862 
  863                 target-module@0 {                       /* 0x4a200000, ap 77 3e.0 */
  864                         compatible = "ti,sysc";
  865                         status = "disabled";
  866                         #address-cells = <1>;
  867                         #size-cells = <1>;
  868                         ranges = <0x0 0x0 0x1000>;
  869                 };
  870 
  871                 target-module@a000 {                    /* 0x4a20a000, ap 79 30.0 */
  872                         compatible = "ti,sysc";
  873                         status = "disabled";
  874                         #address-cells = <1>;
  875                         #size-cells = <1>;
  876                         ranges = <0x0 0xa000 0x1000>;
  877                 };
  878 
  879                 target-module@c000 {                    /* 0x4a20c000, ap 81 0c.0 */
  880                         compatible = "ti,sysc";
  881                         status = "disabled";
  882                         #address-cells = <1>;
  883                         #size-cells = <1>;
  884                         ranges = <0x0 0xc000 0x1000>;
  885                 };
  886 
  887                 target-module@e000 {                    /* 0x4a20e000, ap 83 22.0 */
  888                         compatible = "ti,sysc";
  889                         status = "disabled";
  890                         #address-cells = <1>;
  891                         #size-cells = <1>;
  892                         ranges = <0x0 0xe000 0x1000>;
  893                 };
  894 
  895                 target-module@10000 {                   /* 0x4a210000, ap 85 14.0 */
  896                         compatible = "ti,sysc";
  897                         status = "disabled";
  898                         #address-cells = <1>;
  899                         #size-cells = <1>;
  900                         ranges = <0x0 0x10000 0x1000>;
  901                 };
  902 
  903                 target-module@12000 {                   /* 0x4a212000, ap 87 16.0 */
  904                         compatible = "ti,sysc";
  905                         status = "disabled";
  906                         #address-cells = <1>;
  907                         #size-cells = <1>;
  908                         ranges = <0x0 0x12000 0x1000>;
  909                 };
  910 
  911                 target-module@14000 {                   /* 0x4a214000, ap 89 1c.0 */
  912                         compatible = "ti,sysc";
  913                         status = "disabled";
  914                         #address-cells = <1>;
  915                         #size-cells = <1>;
  916                         ranges = <0x0 0x14000 0x1000>;
  917                 };
  918 
  919                 target-module@18000 {                   /* 0x4a218000, ap 43 12.0 */
  920                         compatible = "ti,sysc";
  921                         status = "disabled";
  922                         #address-cells = <1>;
  923                         #size-cells = <1>;
  924                         ranges = <0x0 0x18000 0x1000>;
  925                 };
  926 
  927                 target-module@1a000 {                   /* 0x4a21a000, ap 127 7a.0 */
  928                         compatible = "ti,sysc";
  929                         status = "disabled";
  930                         #address-cells = <1>;
  931                         #size-cells = <1>;
  932                         ranges = <0x0 0x1a000 0x1000>;
  933                 };
  934 
  935                 target-module@1c000 {                   /* 0x4a21c000, ap 93 38.0 */
  936                         compatible = "ti,sysc";
  937                         status = "disabled";
  938                         #address-cells = <1>;
  939                         #size-cells = <1>;
  940                         ranges = <0x0 0x1c000 0x1000>;
  941                 };
  942 
  943                 target-module@1e000 {                   /* 0x4a21e000, ap 95 0a.0 */
  944                         compatible = "ti,sysc";
  945                         status = "disabled";
  946                         #address-cells = <1>;
  947                         #size-cells = <1>;
  948                         ranges = <0x0 0x1e000 0x1000>;
  949                 };
  950 
  951                 target-module@20000 {                   /* 0x4a220000, ap 97 24.0 */
  952                         compatible = "ti,sysc";
  953                         status = "disabled";
  954                         #address-cells = <1>;
  955                         #size-cells = <1>;
  956                         ranges = <0x0 0x20000 0x1000>;
  957                 };
  958 
  959                 target-module@24000 {                   /* 0x4a224000, ap 99 44.0 */
  960                         compatible = "ti,sysc";
  961                         status = "disabled";
  962                         #address-cells = <1>;
  963                         #size-cells = <1>;
  964                         ranges = <0x0 0x24000 0x1000>;
  965                 };
  966 
  967                 target-module@26000 {                   /* 0x4a226000, ap 101 2c.0 */
  968                         compatible = "ti,sysc";
  969                         status = "disabled";
  970                         #address-cells = <1>;
  971                         #size-cells = <1>;
  972                         ranges = <0x0 0x26000 0x1000>;
  973                 };
  974 
  975                 target-module@2a000 {                   /* 0x4a22a000, ap 91 4c.0 */
  976                         compatible = "ti,sysc";
  977                         status = "disabled";
  978                         #address-cells = <1>;
  979                         #size-cells = <1>;
  980                         ranges = <0x0 0x2a000 0x1000>;
  981                 };
  982 
  983                 target-module@2c000 {                   /* 0x4a22c000, ap 109 6c.0 */
  984                         compatible = "ti,sysc";
  985                         status = "disabled";
  986                         #address-cells = <1>;
  987                         #size-cells = <1>;
  988                         ranges = <0x0 0x2c000 0x1000>;
  989                 };
  990 
  991                 target-module@2e000 {                   /* 0x4a22e000, ap 111 6e.0 */
  992                         compatible = "ti,sysc";
  993                         status = "disabled";
  994                         #address-cells = <1>;
  995                         #size-cells = <1>;
  996                         ranges = <0x0 0x2e000 0x1000>;
  997                 };
  998 
  999                 target-module@30000 {                   /* 0x4a230000, ap 113 70.0 */
 1000                         compatible = "ti,sysc";
 1001                         status = "disabled";
 1002                         #address-cells = <1>;
 1003                         #size-cells = <1>;
 1004                         ranges = <0x0 0x30000 0x1000>;
 1005                 };
 1006 
 1007                 target-module@32000 {                   /* 0x4a232000, ap 115 5a.0 */
 1008                         compatible = "ti,sysc";
 1009                         status = "disabled";
 1010                         #address-cells = <1>;
 1011                         #size-cells = <1>;
 1012                         ranges = <0x0 0x32000 0x1000>;
 1013                 };
 1014 
 1015                 target-module@34000 {                   /* 0x4a234000, ap 117 76.1 */
 1016                         compatible = "ti,sysc";
 1017                         status = "disabled";
 1018                         #address-cells = <1>;
 1019                         #size-cells = <1>;
 1020                         ranges = <0x0 0x34000 0x1000>;
 1021                 };
 1022 
 1023                 target-module@36000 {                   /* 0x4a236000, ap 119 62.0 */
 1024                         compatible = "ti,sysc";
 1025                         status = "disabled";
 1026                         #address-cells = <1>;
 1027                         #size-cells = <1>;
 1028                         ranges = <0x0 0x36000 0x1000>;
 1029                 };
 1030         };
 1031 };
 1032 
 1033 &l4_per1 {                                              /* 0x48000000 */
 1034         compatible = "ti,dra7-l4-per1", "simple-pm-bus";
 1035         power-domains = <&prm_l4per>;
 1036         clocks = <&l4per_clkctrl DRA7_L4PER_L4_PER1_CLKCTRL 0>;
 1037         clock-names = "fck";
 1038         reg = <0x48000000 0x800>,
 1039               <0x48000800 0x800>,
 1040               <0x48001000 0x400>,
 1041               <0x48001400 0x400>,
 1042               <0x48001800 0x400>,
 1043               <0x48001c00 0x400>;
 1044         reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
 1045         #address-cells = <1>;
 1046         #size-cells = <1>;
 1047         ranges = <0x00000000 0x48000000 0x200000>,      /* segment 0 */
 1048                  <0x00200000 0x48200000 0x200000>;      /* segment 1 */
 1049 
 1050         segment@0 {                                     /* 0x48000000 */
 1051                 compatible = "simple-pm-bus";
 1052                 #address-cells = <1>;
 1053                 #size-cells = <1>;
 1054                 ranges = <0x00000000 0x00000000 0x000800>,      /* ap 0 */
 1055                          <0x00001000 0x00001000 0x000400>,      /* ap 1 */
 1056                          <0x00000800 0x00000800 0x000800>,      /* ap 2 */
 1057                          <0x00020000 0x00020000 0x001000>,      /* ap 3 */
 1058                          <0x00021000 0x00021000 0x001000>,      /* ap 4 */
 1059                          <0x00032000 0x00032000 0x001000>,      /* ap 5 */
 1060                          <0x00033000 0x00033000 0x001000>,      /* ap 6 */
 1061                          <0x00034000 0x00034000 0x001000>,      /* ap 7 */
 1062                          <0x00035000 0x00035000 0x001000>,      /* ap 8 */
 1063                          <0x00036000 0x00036000 0x001000>,      /* ap 9 */
 1064                          <0x00037000 0x00037000 0x001000>,      /* ap 10 */
 1065                          <0x0003e000 0x0003e000 0x001000>,      /* ap 11 */
 1066                          <0x0003f000 0x0003f000 0x001000>,      /* ap 12 */
 1067                          <0x00055000 0x00055000 0x001000>,      /* ap 13 */
 1068                          <0x00056000 0x00056000 0x001000>,      /* ap 14 */
 1069                          <0x00057000 0x00057000 0x001000>,      /* ap 15 */
 1070                          <0x00058000 0x00058000 0x001000>,      /* ap 16 */
 1071                          <0x00059000 0x00059000 0x001000>,      /* ap 17 */
 1072                          <0x0005a000 0x0005a000 0x001000>,      /* ap 18 */
 1073                          <0x0005b000 0x0005b000 0x001000>,      /* ap 19 */
 1074                          <0x0005c000 0x0005c000 0x001000>,      /* ap 20 */
 1075                          <0x0005d000 0x0005d000 0x001000>,      /* ap 21 */
 1076                          <0x0005e000 0x0005e000 0x001000>,      /* ap 22 */
 1077                          <0x00060000 0x00060000 0x001000>,      /* ap 23 */
 1078                          <0x0006a000 0x0006a000 0x001000>,      /* ap 24 */
 1079                          <0x0006b000 0x0006b000 0x001000>,      /* ap 25 */
 1080                          <0x0006c000 0x0006c000 0x001000>,      /* ap 26 */
 1081                          <0x0006d000 0x0006d000 0x001000>,      /* ap 27 */
 1082                          <0x0006e000 0x0006e000 0x001000>,      /* ap 28 */
 1083                          <0x0006f000 0x0006f000 0x001000>,      /* ap 29 */
 1084                          <0x00070000 0x00070000 0x001000>,      /* ap 30 */
 1085                          <0x00071000 0x00071000 0x001000>,      /* ap 31 */
 1086                          <0x00072000 0x00072000 0x001000>,      /* ap 32 */
 1087                          <0x00073000 0x00073000 0x001000>,      /* ap 33 */
 1088                          <0x00061000 0x00061000 0x001000>,      /* ap 34 */
 1089                          <0x00053000 0x00053000 0x001000>,      /* ap 35 */
 1090                          <0x00054000 0x00054000 0x001000>,      /* ap 36 */
 1091                          <0x000b2000 0x000b2000 0x001000>,      /* ap 37 */
 1092                          <0x000b3000 0x000b3000 0x001000>,      /* ap 38 */
 1093                          <0x00078000 0x00078000 0x001000>,      /* ap 39 */
 1094                          <0x00079000 0x00079000 0x001000>,      /* ap 40 */
 1095                          <0x00086000 0x00086000 0x001000>,      /* ap 41 */
 1096                          <0x00087000 0x00087000 0x001000>,      /* ap 42 */
 1097                          <0x00088000 0x00088000 0x001000>,      /* ap 43 */
 1098                          <0x00089000 0x00089000 0x001000>,      /* ap 44 */
 1099                          <0x00051000 0x00051000 0x001000>,      /* ap 45 */
 1100                          <0x00052000 0x00052000 0x001000>,      /* ap 46 */
 1101                          <0x00098000 0x00098000 0x001000>,      /* ap 47 */
 1102                          <0x00099000 0x00099000 0x001000>,      /* ap 48 */
 1103                          <0x0009a000 0x0009a000 0x001000>,      /* ap 49 */
 1104                          <0x0009b000 0x0009b000 0x001000>,      /* ap 50 */
 1105                          <0x0009c000 0x0009c000 0x001000>,      /* ap 51 */
 1106                          <0x0009d000 0x0009d000 0x001000>,      /* ap 52 */
 1107                          <0x00068000 0x00068000 0x001000>,      /* ap 53 */
 1108                          <0x00069000 0x00069000 0x001000>,      /* ap 54 */
 1109                          <0x00090000 0x00090000 0x002000>,      /* ap 55 */
 1110                          <0x00092000 0x00092000 0x001000>,      /* ap 56 */
 1111                          <0x000a4000 0x000a4000 0x001000>,      /* ap 57 */
 1112                          <0x000a6000 0x000a6000 0x001000>,      /* ap 58 */
 1113                          <0x000a8000 0x000a8000 0x004000>,      /* ap 59 */
 1114                          <0x000ac000 0x000ac000 0x001000>,      /* ap 60 */
 1115                          <0x000ad000 0x000ad000 0x001000>,      /* ap 61 */
 1116                          <0x000ae000 0x000ae000 0x001000>,      /* ap 62 */
 1117                          <0x00066000 0x00066000 0x001000>,      /* ap 63 */
 1118                          <0x00067000 0x00067000 0x001000>,      /* ap 64 */
 1119                          <0x000b4000 0x000b4000 0x001000>,      /* ap 65 */
 1120                          <0x000b5000 0x000b5000 0x001000>,      /* ap 66 */
 1121                          <0x000b8000 0x000b8000 0x001000>,      /* ap 67 */
 1122                          <0x000b9000 0x000b9000 0x001000>,      /* ap 68 */
 1123                          <0x000ba000 0x000ba000 0x001000>,      /* ap 69 */
 1124                          <0x000bb000 0x000bb000 0x001000>,      /* ap 70 */
 1125                          <0x000d1000 0x000d1000 0x001000>,      /* ap 71 */
 1126                          <0x000d2000 0x000d2000 0x001000>,      /* ap 72 */
 1127                          <0x000d5000 0x000d5000 0x001000>,      /* ap 73 */
 1128                          <0x000d6000 0x000d6000 0x001000>,      /* ap 74 */
 1129                          <0x000a2000 0x000a2000 0x001000>,      /* ap 75 */
 1130                          <0x000a3000 0x000a3000 0x001000>,      /* ap 76 */
 1131                          <0x00001400 0x00001400 0x000400>,      /* ap 77 */
 1132                          <0x00001800 0x00001800 0x000400>,      /* ap 78 */
 1133                          <0x00001c00 0x00001c00 0x000400>,      /* ap 79 */
 1134                          <0x000a5000 0x000a5000 0x001000>,      /* ap 80 */
 1135                          <0x0007a000 0x0007a000 0x001000>,      /* ap 81 */
 1136                          <0x0007b000 0x0007b000 0x001000>,      /* ap 82 */
 1137                          <0x0007c000 0x0007c000 0x001000>,      /* ap 83 */
 1138                          <0x0007d000 0x0007d000 0x001000>;      /* ap 84 */
 1139 
 1140                 target-module@20000 {                   /* 0x48020000, ap 3 04.0 */
 1141                         compatible = "ti,sysc-omap2", "ti,sysc";
 1142                         reg = <0x20050 0x4>,
 1143                               <0x20054 0x4>,
 1144                               <0x20058 0x4>;
 1145                         reg-names = "rev", "sysc", "syss";
 1146                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
 1147                                          SYSC_OMAP2_SOFTRESET |
 1148                                          SYSC_OMAP2_AUTOIDLE)>;
 1149                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 1150                                         <SYSC_IDLE_NO>,
 1151                                         <SYSC_IDLE_SMART>,
 1152                                         <SYSC_IDLE_SMART_WKUP>;
 1153                         ti,syss-mask = <1>;
 1154                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
 1155                         clocks = <&l4per_clkctrl DRA7_L4PER_UART3_CLKCTRL 0>;
 1156                         clock-names = "fck";
 1157                         #address-cells = <1>;
 1158                         #size-cells = <1>;
 1159                         ranges = <0x0 0x20000 0x1000>;
 1160 
 1161                         uart3: serial@0 {
 1162                                 compatible = "ti,dra742-uart";
 1163                                 reg = <0x0 0x100>;
 1164                                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 1165                                 clock-frequency = <48000000>;
 1166                                 status = "disabled";
 1167                                 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
 1168                                 dma-names = "tx", "rx";
 1169                         };
 1170                 };
 1171 
 1172                 target-module@32000 {                   /* 0x48032000, ap 5 3e.0 */
 1173                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 1174                         reg = <0x32000 0x4>,
 1175                               <0x32010 0x4>;
 1176                         reg-names = "rev", "sysc";
 1177                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 1178                                          SYSC_OMAP4_SOFTRESET)>;
 1179                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 1180                                         <SYSC_IDLE_NO>,
 1181                                         <SYSC_IDLE_SMART>,
 1182                                         <SYSC_IDLE_SMART_WKUP>;
 1183                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
 1184                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 0>;
 1185                         clock-names = "fck";
 1186                         #address-cells = <1>;
 1187                         #size-cells = <1>;
 1188                         ranges = <0x0 0x32000 0x1000>;
 1189 
 1190                         timer2: timer@0 {
 1191                                 compatible = "ti,omap5430-timer";
 1192                                 reg = <0x0 0x80>;
 1193                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>, <&timer_sys_clk_div>;
 1194                                 clock-names = "fck", "timer_sys_ck";
 1195                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 1196                         };
 1197                 };
 1198 
 1199                 timer3_target: target-module@34000 {    /* 0x48034000, ap 7 46.0 */
 1200                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 1201                         reg = <0x34000 0x4>,
 1202                               <0x34010 0x4>;
 1203                         reg-names = "rev", "sysc";
 1204                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 1205                                          SYSC_OMAP4_SOFTRESET)>;
 1206                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 1207                                         <SYSC_IDLE_NO>,
 1208                                         <SYSC_IDLE_SMART>,
 1209                                         <SYSC_IDLE_SMART_WKUP>;
 1210                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
 1211                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 0>;
 1212                         clock-names = "fck";
 1213                         #address-cells = <1>;
 1214                         #size-cells = <1>;
 1215                         ranges = <0x0 0x34000 0x1000>;
 1216 
 1217                         timer3: timer@0 {
 1218                                 compatible = "ti,omap5430-timer";
 1219                                 reg = <0x0 0x80>;
 1220                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>, <&timer_sys_clk_div>;
 1221                                 clock-names = "fck", "timer_sys_ck";
 1222                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 1223                         };
 1224                 };
 1225 
 1226                 timer4_target: target-module@36000 {    /* 0x48036000, ap 9 4e.0 */
 1227                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 1228                         reg = <0x36000 0x4>,
 1229                               <0x36010 0x4>;
 1230                         reg-names = "rev", "sysc";
 1231                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 1232                                          SYSC_OMAP4_SOFTRESET)>;
 1233                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 1234                                         <SYSC_IDLE_NO>,
 1235                                         <SYSC_IDLE_SMART>,
 1236                                         <SYSC_IDLE_SMART_WKUP>;
 1237                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
 1238                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>;
 1239                         clock-names = "fck";
 1240                         #address-cells = <1>;
 1241                         #size-cells = <1>;
 1242                         ranges = <0x0 0x36000 0x1000>;
 1243 
 1244                         timer4: timer@0 {
 1245                                 compatible = "ti,omap5430-timer";
 1246                                 reg = <0x0 0x80>;
 1247                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>, <&timer_sys_clk_div>;
 1248                                 clock-names = "fck", "timer_sys_ck";
 1249                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 1250                         };
 1251                 };
 1252 
 1253                 target-module@3e000 {                   /* 0x4803e000, ap 11 56.0 */
 1254                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 1255                         reg = <0x3e000 0x4>,
 1256                               <0x3e010 0x4>;
 1257                         reg-names = "rev", "sysc";
 1258                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 1259                                          SYSC_OMAP4_SOFTRESET)>;
 1260                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 1261                                         <SYSC_IDLE_NO>,
 1262                                         <SYSC_IDLE_SMART>,
 1263                                         <SYSC_IDLE_SMART_WKUP>;
 1264                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
 1265                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 0>;
 1266                         clock-names = "fck";
 1267                         #address-cells = <1>;
 1268                         #size-cells = <1>;
 1269                         ranges = <0x0 0x3e000 0x1000>;
 1270 
 1271                         timer9: timer@0 {
 1272                                 compatible = "ti,omap5430-timer";
 1273                                 reg = <0x0 0x80>;
 1274                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>, <&timer_sys_clk_div>;
 1275                                 clock-names = "fck", "timer_sys_ck";
 1276                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 1277                         };
 1278                 };
 1279 
 1280                 gpio7_target: target-module@51000 {             /* 0x48051000, ap 45 2e.0 */
 1281                         compatible = "ti,sysc-omap2", "ti,sysc";
 1282                         reg = <0x51000 0x4>,
 1283                               <0x51010 0x4>,
 1284                               <0x51114 0x4>;
 1285                         reg-names = "rev", "sysc", "syss";
 1286                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
 1287                                          SYSC_OMAP2_SOFTRESET |
 1288                                          SYSC_OMAP2_AUTOIDLE)>;
 1289                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 1290                                         <SYSC_IDLE_NO>,
 1291                                         <SYSC_IDLE_SMART>,
 1292                                         <SYSC_IDLE_SMART_WKUP>;
 1293                         ti,syss-mask = <1>;
 1294                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
 1295                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 0>,
 1296                                  <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 8>;
 1297                         clock-names = "fck", "dbclk";
 1298                         #address-cells = <1>;
 1299                         #size-cells = <1>;
 1300                         ranges = <0x0 0x51000 0x1000>;
 1301 
 1302                         gpio7: gpio@0 {
 1303                                 compatible = "ti,omap4-gpio";
 1304                                 reg = <0x0 0x200>;
 1305                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 1306                                 gpio-controller;
 1307                                 #gpio-cells = <2>;
 1308                                 interrupt-controller;
 1309                                 #interrupt-cells = <2>;
 1310                         };
 1311                 };
 1312 
 1313                 target-module@53000 {                   /* 0x48053000, ap 35 36.0 */
 1314                         compatible = "ti,sysc-omap2", "ti,sysc";
 1315                         reg = <0x53000 0x4>,
 1316                               <0x53010 0x4>,
 1317                               <0x53114 0x4>;
 1318                         reg-names = "rev", "sysc", "syss";
 1319                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
 1320                                          SYSC_OMAP2_SOFTRESET |
 1321                                          SYSC_OMAP2_AUTOIDLE)>;
 1322                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 1323                                         <SYSC_IDLE_NO>,
 1324                                         <SYSC_IDLE_SMART>,
 1325                                         <SYSC_IDLE_SMART_WKUP>;
 1326                         ti,syss-mask = <1>;
 1327                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
 1328                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 0>,
 1329                                  <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 8>;
 1330                         clock-names = "fck", "dbclk";
 1331                         #address-cells = <1>;
 1332                         #size-cells = <1>;
 1333                         ranges = <0x0 0x53000 0x1000>;
 1334 
 1335                         gpio8: gpio@0 {
 1336                                 compatible = "ti,omap4-gpio";
 1337                                 reg = <0x0 0x200>;
 1338                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 1339                                 gpio-controller;
 1340                                 #gpio-cells = <2>;
 1341                                 interrupt-controller;
 1342                                 #interrupt-cells = <2>;
 1343                         };
 1344                 };
 1345 
 1346                 gpio2_target: target-module@55000 {             /* 0x48055000, ap 13 0e.0 */
 1347                         compatible = "ti,sysc-omap2", "ti,sysc";
 1348                         reg = <0x55000 0x4>,
 1349                               <0x55010 0x4>,
 1350                               <0x55114 0x4>;
 1351                         reg-names = "rev", "sysc", "syss";
 1352                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
 1353                                          SYSC_OMAP2_SOFTRESET |
 1354                                          SYSC_OMAP2_AUTOIDLE)>;
 1355                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 1356                                         <SYSC_IDLE_NO>,
 1357                                         <SYSC_IDLE_SMART>,
 1358                                         <SYSC_IDLE_SMART_WKUP>;
 1359                         ti,syss-mask = <1>;
 1360                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
 1361                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 0>,
 1362                                  <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 8>;
 1363                         clock-names = "fck", "dbclk";
 1364                         #address-cells = <1>;
 1365                         #size-cells = <1>;
 1366                         ranges = <0x0 0x55000 0x1000>;
 1367 
 1368                         gpio2: gpio@0 {
 1369                                 compatible = "ti,omap4-gpio";
 1370                                 reg = <0x0 0x200>;
 1371                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 1372                                 gpio-controller;
 1373                                 #gpio-cells = <2>;
 1374                                 interrupt-controller;
 1375                                 #interrupt-cells = <2>;
 1376                         };
 1377                 };
 1378 
 1379                 gpio3_target: target-module@57000 {             /* 0x48057000, ap 15 06.0 */
 1380                         compatible = "ti,sysc-omap2", "ti,sysc";
 1381                         reg = <0x57000 0x4>,
 1382                               <0x57010 0x4>,
 1383                               <0x57114 0x4>;
 1384                         reg-names = "rev", "sysc", "syss";
 1385                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
 1386                                          SYSC_OMAP2_SOFTRESET |
 1387                                          SYSC_OMAP2_AUTOIDLE)>;
 1388                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 1389                                         <SYSC_IDLE_NO>,
 1390                                         <SYSC_IDLE_SMART>,
 1391                                         <SYSC_IDLE_SMART_WKUP>;
 1392                         ti,syss-mask = <1>;
 1393                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
 1394                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 0>,
 1395                                  <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 8>;
 1396                         clock-names = "fck", "dbclk";
 1397                         #address-cells = <1>;
 1398                         #size-cells = <1>;
 1399                         ranges = <0x0 0x57000 0x1000>;
 1400 
 1401                         gpio3: gpio@0 {
 1402                                 compatible = "ti,omap4-gpio";
 1403                                 reg = <0x0 0x200>;
 1404                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 1405                                 gpio-controller;
 1406                                 #gpio-cells = <2>;
 1407                                 interrupt-controller;
 1408                                 #interrupt-cells = <2>;
 1409                         };
 1410                 };
 1411 
 1412                 target-module@59000 {                   /* 0x48059000, ap 17 16.0 */
 1413                         compatible = "ti,sysc-omap2", "ti,sysc";
 1414                         reg = <0x59000 0x4>,
 1415                               <0x59010 0x4>,
 1416                               <0x59114 0x4>;
 1417                         reg-names = "rev", "sysc", "syss";
 1418                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
 1419                                          SYSC_OMAP2_SOFTRESET |
 1420                                          SYSC_OMAP2_AUTOIDLE)>;
 1421                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 1422                                         <SYSC_IDLE_NO>,
 1423                                         <SYSC_IDLE_SMART>,
 1424                                         <SYSC_IDLE_SMART_WKUP>;
 1425                         ti,syss-mask = <1>;
 1426                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
 1427                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 0>,
 1428                                  <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 8>;
 1429                         clock-names = "fck", "dbclk";
 1430                         #address-cells = <1>;
 1431                         #size-cells = <1>;
 1432                         ranges = <0x0 0x59000 0x1000>;
 1433 
 1434                         gpio4: gpio@0 {
 1435                                 compatible = "ti,omap4-gpio";
 1436                                 reg = <0x0 0x200>;
 1437                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 1438                                 gpio-controller;
 1439                                 #gpio-cells = <2>;
 1440                                 interrupt-controller;
 1441                                 #interrupt-cells = <2>;
 1442                         };
 1443                 };
 1444 
 1445                 target-module@5b000 {                   /* 0x4805b000, ap 19 1e.0 */
 1446                         compatible = "ti,sysc-omap2", "ti,sysc";
 1447                         reg = <0x5b000 0x4>,
 1448                               <0x5b010 0x4>,
 1449                               <0x5b114 0x4>;
 1450                         reg-names = "rev", "sysc", "syss";
 1451                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
 1452                                          SYSC_OMAP2_SOFTRESET |
 1453                                          SYSC_OMAP2_AUTOIDLE)>;
 1454                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 1455                                         <SYSC_IDLE_NO>,
 1456                                         <SYSC_IDLE_SMART>,
 1457                                         <SYSC_IDLE_SMART_WKUP>;
 1458                         ti,syss-mask = <1>;
 1459                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
 1460                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 0>,
 1461                                  <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 8>;
 1462                         clock-names = "fck", "dbclk";
 1463                         #address-cells = <1>;
 1464                         #size-cells = <1>;
 1465                         ranges = <0x0 0x5b000 0x1000>;
 1466 
 1467                         gpio5: gpio@0 {
 1468                                 compatible = "ti,omap4-gpio";
 1469                                 reg = <0x0 0x200>;
 1470                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 1471                                 gpio-controller;
 1472                                 #gpio-cells = <2>;
 1473                                 interrupt-controller;
 1474                                 #interrupt-cells = <2>;
 1475                         };
 1476                 };
 1477 
 1478                 target-module@5d000 {                   /* 0x4805d000, ap 21 26.0 */
 1479                         compatible = "ti,sysc-omap2", "ti,sysc";
 1480                         reg = <0x5d000 0x4>,
 1481                               <0x5d010 0x4>,
 1482                               <0x5d114 0x4>;
 1483                         reg-names = "rev", "sysc", "syss";
 1484                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
 1485                                          SYSC_OMAP2_SOFTRESET |
 1486                                          SYSC_OMAP2_AUTOIDLE)>;
 1487                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 1488                                         <SYSC_IDLE_NO>,
 1489                                         <SYSC_IDLE_SMART>,
 1490                                         <SYSC_IDLE_SMART_WKUP>;
 1491                         ti,syss-mask = <1>;
 1492                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
 1493                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 0>,
 1494                                  <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 8>;
 1495                         clock-names = "fck", "dbclk";
 1496                         #address-cells = <1>;
 1497                         #size-cells = <1>;
 1498                         ranges = <0x0 0x5d000 0x1000>;
 1499 
 1500                         gpio6: gpio@0 {
 1501                                 compatible = "ti,omap4-gpio";
 1502                                 reg = <0x0 0x200>;
 1503                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 1504                                 gpio-controller;
 1505                                 #gpio-cells = <2>;
 1506                                 interrupt-controller;
 1507                                 #interrupt-cells = <2>;
 1508                         };
 1509                 };
 1510 
 1511                 target-module@60000 {                   /* 0x48060000, ap 23 32.0 */
 1512                         compatible = "ti,sysc-omap2", "ti,sysc";
 1513                         reg = <0x60000 0x8>,
 1514                               <0x60010 0x8>,
 1515                               <0x60090 0x8>;
 1516                         reg-names = "rev", "sysc", "syss";
 1517                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 1518                                          SYSC_OMAP2_ENAWAKEUP |
 1519                                          SYSC_OMAP2_SOFTRESET |
 1520                                          SYSC_OMAP2_AUTOIDLE)>;
 1521                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 1522                                         <SYSC_IDLE_NO>,
 1523                                         <SYSC_IDLE_SMART>,
 1524                                         <SYSC_IDLE_SMART_WKUP>;
 1525                         ti,syss-mask = <1>;
 1526                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
 1527                         clocks = <&l4per_clkctrl DRA7_L4PER_I2C3_CLKCTRL 0>;
 1528                         clock-names = "fck";
 1529                         #address-cells = <1>;
 1530                         #size-cells = <1>;
 1531                         ranges = <0x0 0x60000 0x1000>;
 1532 
 1533                         i2c3: i2c@0 {
 1534                                 compatible = "ti,omap4-i2c";
 1535                                 reg = <0x0 0x100>;
 1536                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 1537                                 #address-cells = <1>;
 1538                                 #size-cells = <0>;
 1539                                 status = "disabled";
 1540                         };
 1541                 };
 1542 
 1543                 target-module@66000 {                   /* 0x48066000, ap 63 14.0 */
 1544                         compatible = "ti,sysc-omap2", "ti,sysc";
 1545                         reg = <0x66050 0x4>,
 1546                               <0x66054 0x4>,
 1547                               <0x66058 0x4>;
 1548                         reg-names = "rev", "sysc", "syss";
 1549                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
 1550                                          SYSC_OMAP2_SOFTRESET |
 1551                                          SYSC_OMAP2_AUTOIDLE)>;
 1552                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 1553                                         <SYSC_IDLE_NO>,
 1554                                         <SYSC_IDLE_SMART>,
 1555                                         <SYSC_IDLE_SMART_WKUP>;
 1556                         ti,syss-mask = <1>;
 1557                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
 1558                         clocks = <&l4per_clkctrl DRA7_L4PER_UART5_CLKCTRL 0>;
 1559                         clock-names = "fck";
 1560                         #address-cells = <1>;
 1561                         #size-cells = <1>;
 1562                         ranges = <0x0 0x66000 0x1000>;
 1563 
 1564                         uart5: serial@0 {
 1565                                 compatible = "ti,dra742-uart";
 1566                                 reg = <0x0 0x100>;
 1567                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 1568                                 clock-frequency = <48000000>;
 1569                                 status = "disabled";
 1570                                 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
 1571                                 dma-names = "tx", "rx";
 1572                         };
 1573                 };
 1574 
 1575                 target-module@68000 {                   /* 0x48068000, ap 53 1c.0 */
 1576                         compatible = "ti,sysc-omap2", "ti,sysc";
 1577                         reg = <0x68050 0x4>,
 1578                               <0x68054 0x4>,
 1579                               <0x68058 0x4>;
 1580                         reg-names = "rev", "sysc", "syss";
 1581                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
 1582                                          SYSC_OMAP2_SOFTRESET |
 1583                                          SYSC_OMAP2_AUTOIDLE)>;
 1584                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 1585                                         <SYSC_IDLE_NO>,
 1586                                         <SYSC_IDLE_SMART>,
 1587                                         <SYSC_IDLE_SMART_WKUP>;
 1588                         ti,syss-mask = <1>;
 1589                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
 1590                         clocks = <&ipu_clkctrl DRA7_IPU_UART6_CLKCTRL 0>;
 1591                         clock-names = "fck";
 1592                         #address-cells = <1>;
 1593                         #size-cells = <1>;
 1594                         ranges = <0x0 0x68000 0x1000>;
 1595 
 1596                         uart6: serial@0 {
 1597                                 compatible = "ti,dra742-uart";
 1598                                 reg = <0x0 0x100>;
 1599                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 1600                                 clock-frequency = <48000000>;
 1601                                 status = "disabled";
 1602                                 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
 1603                                 dma-names = "tx", "rx";
 1604                         };
 1605                 };
 1606 
 1607                 target-module@6a000 {                   /* 0x4806a000, ap 24 24.0 */
 1608                         compatible = "ti,sysc-omap2", "ti,sysc";
 1609                         reg = <0x6a050 0x4>,
 1610                               <0x6a054 0x4>,
 1611                               <0x6a058 0x4>;
 1612                         reg-names = "rev", "sysc", "syss";
 1613                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
 1614                                          SYSC_OMAP2_SOFTRESET |
 1615                                          SYSC_OMAP2_AUTOIDLE)>;
 1616                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 1617                                         <SYSC_IDLE_NO>,
 1618                                         <SYSC_IDLE_SMART>,
 1619                                         <SYSC_IDLE_SMART_WKUP>;
 1620                         ti,syss-mask = <1>;
 1621                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
 1622                         clocks = <&l4per_clkctrl DRA7_L4PER_UART1_CLKCTRL 0>;
 1623                         clock-names = "fck";
 1624                         #address-cells = <1>;
 1625                         #size-cells = <1>;
 1626                         ranges = <0x0 0x6a000 0x1000>;
 1627 
 1628                         uart1: serial@0 {
 1629                                 compatible = "ti,dra742-uart";
 1630                                 reg = <0x0 0x100>;
 1631                                 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 1632                                 clock-frequency = <48000000>;
 1633                                 status = "disabled";
 1634                                 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
 1635                                 dma-names = "tx", "rx";
 1636                         };
 1637                 };
 1638 
 1639                 target-module@6c000 {                   /* 0x4806c000, ap 26 2c.0 */
 1640                         compatible = "ti,sysc-omap2", "ti,sysc";
 1641                         reg = <0x6c050 0x4>,
 1642                               <0x6c054 0x4>,
 1643                               <0x6c058 0x4>;
 1644                         reg-names = "rev", "sysc", "syss";
 1645                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
 1646                                          SYSC_OMAP2_SOFTRESET |
 1647                                          SYSC_OMAP2_AUTOIDLE)>;
 1648                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 1649                                         <SYSC_IDLE_NO>,
 1650                                         <SYSC_IDLE_SMART>,
 1651                                         <SYSC_IDLE_SMART_WKUP>;
 1652                         ti,syss-mask = <1>;
 1653                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
 1654                         clocks = <&l4per_clkctrl DRA7_L4PER_UART2_CLKCTRL 0>;
 1655                         clock-names = "fck";
 1656                         #address-cells = <1>;
 1657                         #size-cells = <1>;
 1658                         ranges = <0x0 0x6c000 0x1000>;
 1659 
 1660                         uart2: serial@0 {
 1661                                 compatible = "ti,dra742-uart";
 1662                                 reg = <0x0 0x100>;
 1663                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 1664                                 clock-frequency = <48000000>;
 1665                                 status = "disabled";
 1666                                 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
 1667                                 dma-names = "tx", "rx";
 1668                         };
 1669                 };
 1670 
 1671                 target-module@6e000 {                   /* 0x4806e000, ap 28 0c.1 */
 1672                         compatible = "ti,sysc-omap2", "ti,sysc";
 1673                         reg = <0x6e050 0x4>,
 1674                               <0x6e054 0x4>,
 1675                               <0x6e058 0x4>;
 1676                         reg-names = "rev", "sysc", "syss";
 1677                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
 1678                                          SYSC_OMAP2_SOFTRESET |
 1679                                          SYSC_OMAP2_AUTOIDLE)>;
 1680                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 1681                                         <SYSC_IDLE_NO>,
 1682                                         <SYSC_IDLE_SMART>,
 1683                                         <SYSC_IDLE_SMART_WKUP>;
 1684                         ti,syss-mask = <1>;
 1685                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
 1686                         clocks = <&l4per_clkctrl DRA7_L4PER_UART4_CLKCTRL 0>;
 1687                         clock-names = "fck";
 1688                         #address-cells = <1>;
 1689                         #size-cells = <1>;
 1690                         ranges = <0x0 0x6e000 0x1000>;
 1691 
 1692                         uart4: serial@0 {
 1693                                 compatible = "ti,dra742-uart";
 1694                                 reg = <0x0 0x100>;
 1695                                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 1696                                 clock-frequency = <48000000>;
 1697                                                 status = "disabled";
 1698                                 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
 1699                                 dma-names = "tx", "rx";
 1700                         };
 1701                 };
 1702 
 1703                 target-module@70000 {                   /* 0x48070000, ap 30 22.0 */
 1704                         compatible = "ti,sysc-omap2", "ti,sysc";
 1705                         reg = <0x70000 0x8>,
 1706                               <0x70010 0x8>,
 1707                               <0x70090 0x8>;
 1708                         reg-names = "rev", "sysc", "syss";
 1709                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 1710                                          SYSC_OMAP2_ENAWAKEUP |
 1711                                          SYSC_OMAP2_SOFTRESET |
 1712                                          SYSC_OMAP2_AUTOIDLE)>;
 1713                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 1714                                         <SYSC_IDLE_NO>,
 1715                                         <SYSC_IDLE_SMART>,
 1716                                         <SYSC_IDLE_SMART_WKUP>;
 1717                         ti,syss-mask = <1>;
 1718                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
 1719                         clocks = <&l4per_clkctrl DRA7_L4PER_I2C1_CLKCTRL 0>;
 1720                         clock-names = "fck";
 1721                         #address-cells = <1>;
 1722                         #size-cells = <1>;
 1723                         ranges = <0x0 0x70000 0x1000>;
 1724 
 1725                         i2c1: i2c@0 {
 1726                                 compatible = "ti,omap4-i2c";
 1727                                 reg = <0x0 0x100>;
 1728                                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 1729                                 #address-cells = <1>;
 1730                                 #size-cells = <0>;
 1731                                 status = "disabled";
 1732                         };
 1733                 };
 1734 
 1735                 target-module@72000 {                   /* 0x48072000, ap 32 2a.0 */
 1736                         compatible = "ti,sysc-omap2", "ti,sysc";
 1737                         reg = <0x72000 0x8>,
 1738                               <0x72010 0x8>,
 1739                               <0x72090 0x8>;
 1740                         reg-names = "rev", "sysc", "syss";
 1741                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 1742                                          SYSC_OMAP2_ENAWAKEUP |
 1743                                          SYSC_OMAP2_SOFTRESET |
 1744                                          SYSC_OMAP2_AUTOIDLE)>;
 1745                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 1746                                         <SYSC_IDLE_NO>,
 1747                                         <SYSC_IDLE_SMART>,
 1748                                         <SYSC_IDLE_SMART_WKUP>;
 1749                         ti,syss-mask = <1>;
 1750                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
 1751                         clocks = <&l4per_clkctrl DRA7_L4PER_I2C2_CLKCTRL 0>;
 1752                         clock-names = "fck";
 1753                         #address-cells = <1>;
 1754                         #size-cells = <1>;
 1755                         ranges = <0x0 0x72000 0x1000>;
 1756 
 1757                         i2c2: i2c@0 {
 1758                                 compatible = "ti,omap4-i2c";
 1759                                 reg = <0x0 0x100>;
 1760                                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 1761                                 #address-cells = <1>;
 1762                                 #size-cells = <0>;
 1763                                 status = "disabled";
 1764                         };
 1765                 };
 1766 
 1767                 target-module@78000 {                   /* 0x48078000, ap 39 0a.0 */
 1768                         compatible = "ti,sysc-omap2", "ti,sysc";
 1769                         reg = <0x78000 0x4>,
 1770                               <0x78010 0x4>,
 1771                               <0x78014 0x4>;
 1772                         reg-names = "rev", "sysc", "syss";
 1773                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 1774                                          SYSC_OMAP2_SOFTRESET |
 1775                                          SYSC_OMAP2_AUTOIDLE)>;
 1776                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 1777                                         <SYSC_IDLE_NO>,
 1778                                         <SYSC_IDLE_SMART>,
 1779                                         <SYSC_IDLE_SMART_WKUP>;
 1780                         ti,syss-mask = <1>;
 1781                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
 1782                         clocks = <&l4per_clkctrl DRA7_L4PER_ELM_CLKCTRL 0>;
 1783                         clock-names = "fck";
 1784                         #address-cells = <1>;
 1785                         #size-cells = <1>;
 1786                         ranges = <0x0 0x78000 0x1000>;
 1787 
 1788                         elm: elm@0 {
 1789                                 compatible = "ti,am3352-elm";
 1790                                 reg = <0x0 0xfc0>;      /* device IO registers */
 1791                                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 1792                                 status = "disabled";
 1793                         };
 1794                 };
 1795 
 1796                 target-module@7a000 {                   /* 0x4807a000, ap 81 3a.0 */
 1797                         compatible = "ti,sysc-omap2", "ti,sysc";
 1798                         reg = <0x7a000 0x8>,
 1799                               <0x7a010 0x8>,
 1800                               <0x7a090 0x8>;
 1801                         reg-names = "rev", "sysc", "syss";
 1802                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 1803                                          SYSC_OMAP2_ENAWAKEUP |
 1804                                          SYSC_OMAP2_SOFTRESET |
 1805                                          SYSC_OMAP2_AUTOIDLE)>;
 1806                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 1807                                         <SYSC_IDLE_NO>,
 1808                                         <SYSC_IDLE_SMART>,
 1809                                         <SYSC_IDLE_SMART_WKUP>;
 1810                         ti,syss-mask = <1>;
 1811                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
 1812                         clocks = <&l4per_clkctrl DRA7_L4PER_I2C4_CLKCTRL 0>;
 1813                         clock-names = "fck";
 1814                         #address-cells = <1>;
 1815                         #size-cells = <1>;
 1816                         ranges = <0x0 0x7a000 0x1000>;
 1817 
 1818                         i2c4: i2c@0 {
 1819                                 compatible = "ti,omap4-i2c";
 1820                                 reg = <0x0 0x100>;
 1821                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 1822                                 #address-cells = <1>;
 1823                                 #size-cells = <0>;
 1824                                 status = "disabled";
 1825                         };
 1826                 };
 1827 
 1828                 target-module@7c000 {                   /* 0x4807c000, ap 83 4a.0 */
 1829                         compatible = "ti,sysc-omap2", "ti,sysc";
 1830                         reg = <0x7c000 0x8>,
 1831                               <0x7c010 0x8>,
 1832                               <0x7c090 0x8>;
 1833                         reg-names = "rev", "sysc", "syss";
 1834                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 1835                                          SYSC_OMAP2_ENAWAKEUP |
 1836                                          SYSC_OMAP2_SOFTRESET |
 1837                                          SYSC_OMAP2_AUTOIDLE)>;
 1838                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 1839                                         <SYSC_IDLE_NO>,
 1840                                         <SYSC_IDLE_SMART>,
 1841                                         <SYSC_IDLE_SMART_WKUP>;
 1842                         ti,syss-mask = <1>;
 1843                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
 1844                         clocks = <&ipu_clkctrl DRA7_IPU_I2C5_CLKCTRL 0>;
 1845                         clock-names = "fck";
 1846                         #address-cells = <1>;
 1847                         #size-cells = <1>;
 1848                         ranges = <0x0 0x7c000 0x1000>;
 1849 
 1850                         i2c5: i2c@0 {
 1851                                 compatible = "ti,omap4-i2c";
 1852                                 reg = <0x0 0x100>;
 1853                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 1854                                 #address-cells = <1>;
 1855                                 #size-cells = <0>;
 1856                                 status = "disabled";
 1857                         };
 1858                 };
 1859 
 1860                 target-module@86000 {                   /* 0x48086000, ap 41 5e.0 */
 1861                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 1862                         reg = <0x86000 0x4>,
 1863                               <0x86010 0x4>;
 1864                         reg-names = "rev", "sysc";
 1865                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 1866                                          SYSC_OMAP4_SOFTRESET)>;
 1867                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 1868                                         <SYSC_IDLE_NO>,
 1869                                         <SYSC_IDLE_SMART>,
 1870                                         <SYSC_IDLE_SMART_WKUP>;
 1871                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
 1872                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 0>;
 1873                         clock-names = "fck";
 1874                         #address-cells = <1>;
 1875                         #size-cells = <1>;
 1876                         ranges = <0x0 0x86000 0x1000>;
 1877 
 1878                         timer10: timer@0 {
 1879                                 compatible = "ti,omap5430-timer";
 1880                                 reg = <0x0 0x80>;
 1881                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>, <&timer_sys_clk_div>;
 1882                                 clock-names = "fck", "timer_sys_ck";
 1883                                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 1884                         };
 1885                 };
 1886 
 1887                 target-module@88000 {                   /* 0x48088000, ap 43 66.0 */
 1888                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 1889                         reg = <0x88000 0x4>,
 1890                               <0x88010 0x4>;
 1891                         reg-names = "rev", "sysc";
 1892                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 1893                                          SYSC_OMAP4_SOFTRESET)>;
 1894                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 1895                                         <SYSC_IDLE_NO>,
 1896                                         <SYSC_IDLE_SMART>,
 1897                                         <SYSC_IDLE_SMART_WKUP>;
 1898                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
 1899                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 0>;
 1900                         clock-names = "fck";
 1901                         #address-cells = <1>;
 1902                         #size-cells = <1>;
 1903                         ranges = <0x0 0x88000 0x1000>;
 1904 
 1905                         timer11: timer@0 {
 1906                                 compatible = "ti,omap5430-timer";
 1907                                 reg = <0x0 0x80>;
 1908                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>, <&timer_sys_clk_div>;
 1909                                 clock-names = "fck", "timer_sys_ck";
 1910                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 1911                         };
 1912                 };
 1913 
 1914                 target-module@90000 {                   /* 0x48090000, ap 55 12.0 */
 1915                         compatible = "ti,sysc-omap2", "ti,sysc";
 1916                         reg = <0x91fe0 0x4>,
 1917                               <0x91fe4 0x4>;
 1918                         reg-names = "rev", "sysc";
 1919                         ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>;
 1920                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 1921                                         <SYSC_IDLE_NO>;
 1922                         /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
 1923                         clocks = <&l4sec_clkctrl DRA7_L4SEC_RNG_CLKCTRL 0>;
 1924                         clock-names = "fck";
 1925                         #address-cells = <1>;
 1926                         #size-cells = <1>;
 1927                         ranges = <0x0 0x90000 0x2000>;
 1928 
 1929                         rng: rng@0 {
 1930                                 compatible = "ti,omap4-rng";
 1931                                 reg = <0x0 0x2000>;
 1932                                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 1933                                 clocks = <&l3_iclk_div>;
 1934                                 clock-names = "fck";
 1935                         };
 1936                 };
 1937 
 1938                 target-module@98000 {                   /* 0x48098000, ap 47 08.0 */
 1939                         compatible = "ti,sysc-omap4", "ti,sysc";
 1940                         reg = <0x98000 0x4>,
 1941                               <0x98010 0x4>;
 1942                         reg-names = "rev", "sysc";
 1943                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 1944                                          SYSC_OMAP4_SOFTRESET)>;
 1945                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 1946                                         <SYSC_IDLE_NO>,
 1947                                         <SYSC_IDLE_SMART>,
 1948                                         <SYSC_IDLE_SMART_WKUP>;
 1949                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
 1950                         clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI1_CLKCTRL 0>;
 1951                         clock-names = "fck";
 1952                         #address-cells = <1>;
 1953                         #size-cells = <1>;
 1954                         ranges = <0x0 0x98000 0x1000>;
 1955 
 1956                         mcspi1: spi@0 {
 1957                                 compatible = "ti,omap4-mcspi";
 1958                                 reg = <0x0 0x200>;
 1959                                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 1960                                 #address-cells = <1>;
 1961                                 #size-cells = <0>;
 1962                                 ti,spi-num-cs = <4>;
 1963                                 dmas = <&sdma_xbar 35>,
 1964                                        <&sdma_xbar 36>,
 1965                                        <&sdma_xbar 37>,
 1966                                        <&sdma_xbar 38>,
 1967                                        <&sdma_xbar 39>,
 1968                                        <&sdma_xbar 40>,
 1969                                        <&sdma_xbar 41>,
 1970                                        <&sdma_xbar 42>;
 1971                                 dma-names = "tx0", "rx0", "tx1", "rx1",
 1972                                             "tx2", "rx2", "tx3", "rx3";
 1973                                 status = "disabled";
 1974                         };
 1975                 };
 1976 
 1977                 target-module@9a000 {                   /* 0x4809a000, ap 49 10.0 */
 1978                         compatible = "ti,sysc-omap4", "ti,sysc";
 1979                         reg = <0x9a000 0x4>,
 1980                               <0x9a010 0x4>;
 1981                         reg-names = "rev", "sysc";
 1982                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 1983                                          SYSC_OMAP4_SOFTRESET)>;
 1984                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 1985                                         <SYSC_IDLE_NO>,
 1986                                         <SYSC_IDLE_SMART>,
 1987                                         <SYSC_IDLE_SMART_WKUP>;
 1988                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
 1989                         clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI2_CLKCTRL 0>;
 1990                         clock-names = "fck";
 1991                         #address-cells = <1>;
 1992                         #size-cells = <1>;
 1993                         ranges = <0x0 0x9a000 0x1000>;
 1994 
 1995                         mcspi2: spi@0 {
 1996                                 compatible = "ti,omap4-mcspi";
 1997                                 reg = <0x0 0x200>;
 1998                                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 1999                                 #address-cells = <1>;
 2000                                 #size-cells = <0>;
 2001                                 ti,spi-num-cs = <2>;
 2002                                 dmas = <&sdma_xbar 43>,
 2003                                        <&sdma_xbar 44>,
 2004                                        <&sdma_xbar 45>,
 2005                                        <&sdma_xbar 46>;
 2006                                 dma-names = "tx0", "rx0", "tx1", "rx1";
 2007                                 status = "disabled";
 2008                         };
 2009                 };
 2010 
 2011                 target-module@9c000 {                   /* 0x4809c000, ap 51 38.0 */
 2012                         compatible = "ti,sysc-omap4", "ti,sysc";
 2013                         reg = <0x9c000 0x4>,
 2014                               <0x9c010 0x4>;
 2015                         reg-names = "rev", "sysc";
 2016                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 2017                                          SYSC_OMAP4_SOFTRESET)>;
 2018                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 2019                                         <SYSC_IDLE_NO>,
 2020                                         <SYSC_IDLE_SMART>,
 2021                                         <SYSC_IDLE_SMART_WKUP>;
 2022                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 2023                                         <SYSC_IDLE_NO>,
 2024                                         <SYSC_IDLE_SMART>,
 2025                                         <SYSC_IDLE_SMART_WKUP>;
 2026                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
 2027                         clocks = <&l3init_clkctrl DRA7_L3INIT_MMC1_CLKCTRL 0>;
 2028                         clock-names = "fck";
 2029                         #address-cells = <1>;
 2030                         #size-cells = <1>;
 2031                         ranges = <0x0 0x9c000 0x1000>;
 2032 
 2033                         mmc1: mmc@0 {
 2034                                 compatible = "ti,dra7-sdhci";
 2035                                 reg = <0x0 0x400>;
 2036                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 2037                                 status = "disabled";
 2038                                 pbias-supply = <&pbias_mmc_reg>;
 2039                                 max-frequency = <192000000>;
 2040                                 mmc-ddr-1_8v;
 2041                                 mmc-ddr-3_3v;
 2042                         };
 2043                 };
 2044 
 2045                 target-module@a2000 {                   /* 0x480a2000, ap 75 02.0 */
 2046                         compatible = "ti,sysc";
 2047                         status = "disabled";
 2048                         #address-cells = <1>;
 2049                         #size-cells = <1>;
 2050                         ranges = <0x0 0xa2000 0x1000>;
 2051                 };
 2052 
 2053                 target-module@a4000 {                   /* 0x480a4000, ap 57 42.0 */
 2054                         compatible = "ti,sysc";
 2055                         status = "disabled";
 2056                         #address-cells = <1>;
 2057                         #size-cells = <1>;
 2058                         ranges = <0x00000000 0x000a4000 0x00001000>,
 2059                                  <0x00001000 0x000a5000 0x00001000>;
 2060                 };
 2061 
 2062                 des_target: target-module@a5000 {       /* 0x480a5000 */
 2063                         compatible = "ti,sysc-omap2", "ti,sysc";
 2064                         reg = <0xa5030 0x4>,
 2065                               <0xa5034 0x4>,
 2066                               <0xa5038 0x4>;
 2067                         reg-names = "rev", "sysc", "syss";
 2068                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 2069                                          SYSC_OMAP2_AUTOIDLE)>;
 2070                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 2071                                         <SYSC_IDLE_NO>,
 2072                                         <SYSC_IDLE_SMART>,
 2073                                         <SYSC_IDLE_SMART_WKUP>;
 2074                         ti,syss-mask = <1>;
 2075                         /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
 2076                         clocks = <&l4sec_clkctrl DRA7_L4SEC_DES_CLKCTRL 0>;
 2077                         clock-names = "fck";
 2078                         #address-cells = <1>;
 2079                         #size-cells = <1>;
 2080                         ranges = <0 0xa5000 0x00001000>;
 2081 
 2082                         des: des@0 {
 2083                                 compatible = "ti,omap4-des";
 2084                                 reg = <0 0xa0>;
 2085                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 2086                                 dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
 2087                                 dma-names = "tx", "rx";
 2088                                 clocks = <&l3_iclk_div>;
 2089                                 clock-names = "fck";
 2090                         };
 2091                 };
 2092 
 2093                 target-module@a8000 {                   /* 0x480a8000, ap 59 1a.0 */
 2094                         compatible = "ti,sysc";
 2095                         status = "disabled";
 2096                         #address-cells = <1>;
 2097                         #size-cells = <1>;
 2098                         ranges = <0x0 0xa8000 0x4000>;
 2099                 };
 2100 
 2101                 target-module@ad000 {                   /* 0x480ad000, ap 61 20.0 */
 2102                         compatible = "ti,sysc-omap4", "ti,sysc";
 2103                         reg = <0xad000 0x4>,
 2104                               <0xad010 0x4>;
 2105                         reg-names = "rev", "sysc";
 2106                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 2107                                          SYSC_OMAP4_SOFTRESET)>;
 2108                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 2109                                         <SYSC_IDLE_NO>,
 2110                                         <SYSC_IDLE_SMART>,
 2111                                         <SYSC_IDLE_SMART_WKUP>;
 2112                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 2113                                         <SYSC_IDLE_NO>,
 2114                                         <SYSC_IDLE_SMART>,
 2115                                         <SYSC_IDLE_SMART_WKUP>;
 2116                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
 2117                         clocks = <&l4per_clkctrl DRA7_L4PER_MMC3_CLKCTRL 0>;
 2118                         clock-names = "fck";
 2119                         #address-cells = <1>;
 2120                         #size-cells = <1>;
 2121                         ranges = <0x0 0xad000 0x1000>;
 2122 
 2123                         mmc3: mmc@0 {
 2124                                 compatible = "ti,dra7-sdhci";
 2125                                 reg = <0x0 0x400>;
 2126                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 2127                                 status = "disabled";
 2128                                 /* Errata i887 limits max-frequency of MMC3 to 64 MHz */
 2129                                 max-frequency = <64000000>;
 2130                                 /* SDMA is not supported */
 2131                                 sdhci-caps-mask = <0x0 0x400000>;
 2132                         };
 2133                 };
 2134 
 2135                 target-module@b2000 {                   /* 0x480b2000, ap 37 52.0 */
 2136                         compatible = "ti,sysc-omap2", "ti,sysc";
 2137                         reg = <0xb2000 0x4>,
 2138                               <0xb2014 0x4>,
 2139                               <0xb2018 0x4>;
 2140                         reg-names = "rev", "sysc", "syss";
 2141                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 2142                                          SYSC_OMAP2_AUTOIDLE)>;
 2143                         ti,syss-mask = <1>;
 2144                         ti,no-reset-on-init;
 2145                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
 2146                         clocks = <&l4per_clkctrl DRA7_L4PER_HDQ1W_CLKCTRL 0>;
 2147                         clock-names = "fck";
 2148                         #address-cells = <1>;
 2149                         #size-cells = <1>;
 2150                         ranges = <0x0 0xb2000 0x1000>;
 2151 
 2152                         hdqw1w: 1w@0 {
 2153                                 compatible = "ti,omap3-1w";
 2154                                 reg = <0x0 0x1000>;
 2155                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 2156                         };
 2157                 };
 2158 
 2159                 target-module@b4000 {                   /* 0x480b4000, ap 65 40.0 */
 2160                         compatible = "ti,sysc-omap4", "ti,sysc";
 2161                         reg = <0xb4000 0x4>,
 2162                               <0xb4010 0x4>;
 2163                         reg-names = "rev", "sysc";
 2164                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 2165                                          SYSC_OMAP4_SOFTRESET)>;
 2166                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 2167                                         <SYSC_IDLE_NO>,
 2168                                         <SYSC_IDLE_SMART>,
 2169                                         <SYSC_IDLE_SMART_WKUP>;
 2170                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 2171                                         <SYSC_IDLE_NO>,
 2172                                         <SYSC_IDLE_SMART>,
 2173                                         <SYSC_IDLE_SMART_WKUP>;
 2174                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
 2175                         clocks = <&l3init_clkctrl DRA7_L3INIT_MMC2_CLKCTRL 0>;
 2176                         clock-names = "fck";
 2177                         #address-cells = <1>;
 2178                         #size-cells = <1>;
 2179                         ranges = <0x0 0xb4000 0x1000>;
 2180 
 2181                         mmc2: mmc@0 {
 2182                                 compatible = "ti,dra7-sdhci";
 2183                                 reg = <0x0 0x400>;
 2184                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 2185                                 status = "disabled";
 2186                                 max-frequency = <192000000>;
 2187                                 /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */
 2188                                 sdhci-caps-mask = <0x7 0x0>;
 2189                                 mmc-hs200-1_8v;
 2190                                 mmc-ddr-1_8v;
 2191                                 mmc-ddr-3_3v;
 2192                         };
 2193                 };
 2194 
 2195                 target-module@b8000 {                   /* 0x480b8000, ap 67 48.0 */
 2196                         compatible = "ti,sysc-omap4", "ti,sysc";
 2197                         reg = <0xb8000 0x4>,
 2198                               <0xb8010 0x4>;
 2199                         reg-names = "rev", "sysc";
 2200                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 2201                                          SYSC_OMAP4_SOFTRESET)>;
 2202                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 2203                                         <SYSC_IDLE_NO>,
 2204                                         <SYSC_IDLE_SMART>,
 2205                                         <SYSC_IDLE_SMART_WKUP>;
 2206                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
 2207                         clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI3_CLKCTRL 0>;
 2208                         clock-names = "fck";
 2209                         #address-cells = <1>;
 2210                         #size-cells = <1>;
 2211                         ranges = <0x0 0xb8000 0x1000>;
 2212 
 2213                         mcspi3: spi@0 {
 2214                                 compatible = "ti,omap4-mcspi";
 2215                                 reg = <0x0 0x200>;
 2216                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 2217                                 #address-cells = <1>;
 2218                                 #size-cells = <0>;
 2219                                 ti,spi-num-cs = <2>;
 2220                                 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
 2221                                 dma-names = "tx0", "rx0";
 2222                                 status = "disabled";
 2223                         };
 2224                 };
 2225 
 2226                 target-module@ba000 {                   /* 0x480ba000, ap 69 18.0 */
 2227                         compatible = "ti,sysc-omap4", "ti,sysc";
 2228                         reg = <0xba000 0x4>,
 2229                               <0xba010 0x4>;
 2230                         reg-names = "rev", "sysc";
 2231                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 2232                                          SYSC_OMAP4_SOFTRESET)>;
 2233                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 2234                                         <SYSC_IDLE_NO>,
 2235                                         <SYSC_IDLE_SMART>,
 2236                                         <SYSC_IDLE_SMART_WKUP>;
 2237                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
 2238                         clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI4_CLKCTRL 0>;
 2239                         clock-names = "fck";
 2240                         #address-cells = <1>;
 2241                         #size-cells = <1>;
 2242                         ranges = <0x0 0xba000 0x1000>;
 2243 
 2244                         mcspi4: spi@0 {
 2245                                 compatible = "ti,omap4-mcspi";
 2246                                 reg = <0x0 0x200>;
 2247                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 2248                                 #address-cells = <1>;
 2249                                 #size-cells = <0>;
 2250                                 ti,spi-num-cs = <1>;
 2251                                 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
 2252                                 dma-names = "tx0", "rx0";
 2253                                 status = "disabled";
 2254                         };
 2255                 };
 2256 
 2257                 target-module@d1000 {                   /* 0x480d1000, ap 71 28.0 */
 2258                         compatible = "ti,sysc-omap4", "ti,sysc";
 2259                         reg = <0xd1000 0x4>,
 2260                               <0xd1010 0x4>;
 2261                         reg-names = "rev", "sysc";
 2262                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 2263                                          SYSC_OMAP4_SOFTRESET)>;
 2264                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 2265                                         <SYSC_IDLE_NO>,
 2266                                         <SYSC_IDLE_SMART>,
 2267                                         <SYSC_IDLE_SMART_WKUP>;
 2268                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 2269                                         <SYSC_IDLE_NO>,
 2270                                         <SYSC_IDLE_SMART>,
 2271                                         <SYSC_IDLE_SMART_WKUP>;
 2272                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
 2273                         clocks = <&l4per_clkctrl DRA7_L4PER_MMC4_CLKCTRL 0>;
 2274                         clock-names = "fck";
 2275                         #address-cells = <1>;
 2276                         #size-cells = <1>;
 2277                         ranges = <0x0 0xd1000 0x1000>;
 2278 
 2279                         mmc4: mmc@0 {
 2280                                 compatible = "ti,dra7-sdhci";
 2281                                 reg = <0x0 0x400>;
 2282                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 2283                                 status = "disabled";
 2284                                 max-frequency = <192000000>;
 2285                                 /* SDMA is not supported */
 2286                                 sdhci-caps-mask = <0x0 0x400000>;
 2287                         };
 2288                 };
 2289 
 2290                 target-module@d5000 {                   /* 0x480d5000, ap 73 30.0 */
 2291                         compatible = "ti,sysc";
 2292                         status = "disabled";
 2293                         #address-cells = <1>;
 2294                         #size-cells = <1>;
 2295                         ranges = <0x0 0xd5000 0x1000>;
 2296                 };
 2297         };
 2298 
 2299         segment@200000 {                                        /* 0x48200000 */
 2300                 compatible = "simple-pm-bus";
 2301                 #address-cells = <1>;
 2302                 #size-cells = <1>;
 2303         };
 2304 };
 2305 
 2306 &l4_per2 {                                              /* 0x48400000 */
 2307         compatible = "ti,dra7-l4-per2", "simple-pm-bus";
 2308         power-domains = <&prm_l4per>;
 2309         clocks = <&l4per2_clkctrl DRA7_L4PER2_L4_PER2_CLKCTRL 0>;
 2310         clock-names = "fck";
 2311         reg = <0x48400000 0x800>,
 2312               <0x48400800 0x800>,
 2313               <0x48401000 0x400>,
 2314               <0x48401400 0x400>,
 2315               <0x48401800 0x400>;
 2316         reg-names = "ap", "la", "ia0", "ia1", "ia2";
 2317         #address-cells = <1>;
 2318         #size-cells = <1>;
 2319         ranges = <0x00000000 0x48400000 0x400000>,      /* segment 0 */
 2320                  <0x45800000 0x45800000 0x400000>,      /* L3 data port */
 2321                  <0x45c00000 0x45c00000 0x400000>,      /* L3 data port */
 2322                  <0x46000000 0x46000000 0x400000>,      /* L3 data port */
 2323                  <0x48436000 0x48436000 0x400000>,      /* L3 data port */
 2324                  <0x4843a000 0x4843a000 0x400000>,      /* L3 data port */
 2325                  <0x4844c000 0x4844c000 0x400000>,      /* L3 data port */
 2326                  <0x48450000 0x48450000 0x400000>,      /* L3 data port */
 2327                  <0x48454000 0x48454000 0x400000>;      /* L3 data port */
 2328 
 2329         segment@0 {                                     /* 0x48400000 */
 2330                 compatible = "simple-pm-bus";
 2331                 #address-cells = <1>;
 2332                 #size-cells = <1>;
 2333                 ranges = <0x00000000 0x00000000 0x000800>,      /* ap 0 */
 2334                          <0x00001000 0x00001000 0x000400>,      /* ap 1 */
 2335                          <0x00000800 0x00000800 0x000800>,      /* ap 2 */
 2336                          <0x00084000 0x00084000 0x004000>,      /* ap 3 */
 2337                          <0x00001400 0x00001400 0x000400>,      /* ap 4 */
 2338                          <0x00001800 0x00001800 0x000400>,      /* ap 5 */
 2339                          <0x00088000 0x00088000 0x001000>,      /* ap 6 */
 2340                          <0x0002c000 0x0002c000 0x001000>,      /* ap 7 */
 2341                          <0x0002d000 0x0002d000 0x001000>,      /* ap 8 */
 2342                          <0x00060000 0x00060000 0x002000>,      /* ap 9 */
 2343                          <0x00062000 0x00062000 0x001000>,      /* ap 10 */
 2344                          <0x00064000 0x00064000 0x002000>,      /* ap 11 */
 2345                          <0x00066000 0x00066000 0x001000>,      /* ap 12 */
 2346                          <0x00068000 0x00068000 0x002000>,      /* ap 13 */
 2347                          <0x0006a000 0x0006a000 0x001000>,      /* ap 14 */
 2348                          <0x0006c000 0x0006c000 0x002000>,      /* ap 15 */
 2349                          <0x0006e000 0x0006e000 0x001000>,      /* ap 16 */
 2350                          <0x00036000 0x00036000 0x001000>,      /* ap 17 */
 2351                          <0x00037000 0x00037000 0x001000>,      /* ap 18 */
 2352                          <0x00070000 0x00070000 0x002000>,      /* ap 19 */
 2353                          <0x00072000 0x00072000 0x001000>,      /* ap 20 */
 2354                          <0x0003a000 0x0003a000 0x001000>,      /* ap 21 */
 2355                          <0x0003b000 0x0003b000 0x001000>,      /* ap 22 */
 2356                          <0x0003c000 0x0003c000 0x001000>,      /* ap 23 */
 2357                          <0x0003d000 0x0003d000 0x001000>,      /* ap 24 */
 2358                          <0x0003e000 0x0003e000 0x001000>,      /* ap 25 */
 2359                          <0x0003f000 0x0003f000 0x001000>,      /* ap 26 */
 2360                          <0x00040000 0x00040000 0x001000>,      /* ap 27 */
 2361                          <0x00041000 0x00041000 0x001000>,      /* ap 28 */
 2362                          <0x00042000 0x00042000 0x001000>,      /* ap 29 */
 2363                          <0x00043000 0x00043000 0x001000>,      /* ap 30 */
 2364                          <0x00080000 0x00080000 0x002000>,      /* ap 31 */
 2365                          <0x00082000 0x00082000 0x001000>,      /* ap 32 */
 2366                          <0x0004a000 0x0004a000 0x001000>,      /* ap 33 */
 2367                          <0x0004b000 0x0004b000 0x001000>,      /* ap 34 */
 2368                          <0x00074000 0x00074000 0x002000>,      /* ap 35 */
 2369                          <0x00076000 0x00076000 0x001000>,      /* ap 36 */
 2370                          <0x00050000 0x00050000 0x001000>,      /* ap 37 */
 2371                          <0x00051000 0x00051000 0x001000>,      /* ap 38 */
 2372                          <0x00078000 0x00078000 0x002000>,      /* ap 39 */
 2373                          <0x0007a000 0x0007a000 0x001000>,      /* ap 40 */
 2374                          <0x00054000 0x00054000 0x001000>,      /* ap 41 */
 2375                          <0x00055000 0x00055000 0x001000>,      /* ap 42 */
 2376                          <0x0007c000 0x0007c000 0x002000>,      /* ap 43 */
 2377                          <0x0007e000 0x0007e000 0x001000>,      /* ap 44 */
 2378                          <0x0004c000 0x0004c000 0x001000>,      /* ap 45 */
 2379                          <0x0004d000 0x0004d000 0x001000>,      /* ap 46 */
 2380                          <0x00020000 0x00020000 0x001000>,      /* ap 47 */
 2381                          <0x00021000 0x00021000 0x001000>,      /* ap 48 */
 2382                          <0x00022000 0x00022000 0x001000>,      /* ap 49 */
 2383                          <0x00023000 0x00023000 0x001000>,      /* ap 50 */
 2384                          <0x00024000 0x00024000 0x001000>,      /* ap 51 */
 2385                          <0x00025000 0x00025000 0x001000>,      /* ap 52 */
 2386                          <0x00046000 0x00046000 0x001000>,      /* ap 53 */
 2387                          <0x00047000 0x00047000 0x001000>,      /* ap 54 */
 2388                          <0x00048000 0x00048000 0x001000>,      /* ap 55 */
 2389                          <0x00049000 0x00049000 0x001000>,      /* ap 56 */
 2390                          <0x00058000 0x00058000 0x002000>,      /* ap 57 */
 2391                          <0x0005a000 0x0005a000 0x001000>,      /* ap 58 */
 2392                          <0x0005b000 0x0005b000 0x001000>,      /* ap 59 */
 2393                          <0x0005c000 0x0005c000 0x001000>,      /* ap 60 */
 2394                          <0x0005d000 0x0005d000 0x001000>,      /* ap 61 */
 2395                          <0x0005e000 0x0005e000 0x001000>,      /* ap 62 */
 2396                          <0x45800000 0x45800000 0x400000>,      /* L3 data port */
 2397                          <0x45c00000 0x45c00000 0x400000>,      /* L3 data port */
 2398                          <0x46000000 0x46000000 0x400000>,      /* L3 data port */
 2399                          <0x48436000 0x48436000 0x400000>,      /* L3 data port */
 2400                          <0x4843a000 0x4843a000 0x400000>,      /* L3 data port */
 2401                          <0x4844c000 0x4844c000 0x400000>,      /* L3 data port */
 2402                          <0x48450000 0x48450000 0x400000>,      /* L3 data port */
 2403                          <0x48454000 0x48454000 0x400000>;      /* L3 data port */
 2404 
 2405                 target-module@20000 {                   /* 0x48420000, ap 47 02.0 */
 2406                         compatible = "ti,sysc-omap2", "ti,sysc";
 2407                         reg = <0x20050 0x4>,
 2408                               <0x20054 0x4>,
 2409                               <0x20058 0x4>;
 2410                         reg-names = "rev", "sysc", "syss";
 2411                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
 2412                                          SYSC_OMAP2_SOFTRESET |
 2413                                          SYSC_OMAP2_AUTOIDLE)>;
 2414                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 2415                                         <SYSC_IDLE_NO>,
 2416                                         <SYSC_IDLE_SMART>,
 2417                                         <SYSC_IDLE_SMART_WKUP>;
 2418                         ti,syss-mask = <1>;
 2419                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
 2420                         clocks = <&l4per2_clkctrl DRA7_L4PER2_UART7_CLKCTRL 0>;
 2421                         clock-names = "fck";
 2422                         #address-cells = <1>;
 2423                         #size-cells = <1>;
 2424                         ranges = <0x0 0x20000 0x1000>;
 2425 
 2426                         uart7: serial@0 {
 2427                                 compatible = "ti,dra742-uart";
 2428                                 reg = <0x0 0x100>;
 2429                                 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
 2430                                 clock-frequency = <48000000>;
 2431                                 status = "disabled";
 2432                         };
 2433                 };
 2434 
 2435                 target-module@22000 {                   /* 0x48422000, ap 49 0a.0 */
 2436                         compatible = "ti,sysc-omap2", "ti,sysc";
 2437                         reg = <0x22050 0x4>,
 2438                               <0x22054 0x4>,
 2439                               <0x22058 0x4>;
 2440                         reg-names = "rev", "sysc", "syss";
 2441                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
 2442                                          SYSC_OMAP2_SOFTRESET |
 2443                                          SYSC_OMAP2_AUTOIDLE)>;
 2444                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 2445                                         <SYSC_IDLE_NO>,
 2446                                         <SYSC_IDLE_SMART>,
 2447                                         <SYSC_IDLE_SMART_WKUP>;
 2448                         ti,syss-mask = <1>;
 2449                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
 2450                         clocks = <&l4per2_clkctrl DRA7_L4PER2_UART8_CLKCTRL 0>;
 2451                         clock-names = "fck";
 2452                         #address-cells = <1>;
 2453                         #size-cells = <1>;
 2454                         ranges = <0x0 0x22000 0x1000>;
 2455 
 2456                         uart8: serial@0 {
 2457                                 compatible = "ti,dra742-uart";
 2458                                 reg = <0x0 0x100>;
 2459                                 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
 2460                                 clock-frequency = <48000000>;
 2461                                 status = "disabled";
 2462                         };
 2463                 };
 2464 
 2465                 target-module@24000 {                   /* 0x48424000, ap 51 12.0 */
 2466                         compatible = "ti,sysc-omap2", "ti,sysc";
 2467                         reg = <0x24050 0x4>,
 2468                               <0x24054 0x4>,
 2469                               <0x24058 0x4>;
 2470                         reg-names = "rev", "sysc", "syss";
 2471                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
 2472                                          SYSC_OMAP2_SOFTRESET |
 2473                                          SYSC_OMAP2_AUTOIDLE)>;
 2474                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 2475                                         <SYSC_IDLE_NO>,
 2476                                         <SYSC_IDLE_SMART>,
 2477                                         <SYSC_IDLE_SMART_WKUP>;
 2478                         ti,syss-mask = <1>;
 2479                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
 2480                         clocks = <&l4per2_clkctrl DRA7_L4PER2_UART9_CLKCTRL 0>;
 2481                         clock-names = "fck";
 2482                         #address-cells = <1>;
 2483                         #size-cells = <1>;
 2484                         ranges = <0x0 0x24000 0x1000>;
 2485 
 2486                         uart9: serial@0 {
 2487                                 compatible = "ti,dra742-uart";
 2488                                 reg = <0x0 0x100>;
 2489                                 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 2490                                 clock-frequency = <48000000>;
 2491                                 status = "disabled";
 2492                         };
 2493                 };
 2494 
 2495                 target-module@2c000 {                   /* 0x4842c000, ap 7 18.0 */
 2496                         compatible = "ti,sysc";
 2497                         status = "disabled";
 2498                         #address-cells = <1>;
 2499                         #size-cells = <1>;
 2500                         ranges = <0x0 0x2c000 0x1000>;
 2501                 };
 2502 
 2503                 target-module@36000 {                   /* 0x48436000, ap 17 06.0 */
 2504                         compatible = "ti,sysc";
 2505                         status = "disabled";
 2506                         #address-cells = <1>;
 2507                         #size-cells = <1>;
 2508                         ranges = <0x0 0x36000 0x1000>;
 2509                 };
 2510 
 2511                 target-module@3a000 {                   /* 0x4843a000, ap 21 3e.0 */
 2512                         compatible = "ti,sysc";
 2513                         status = "disabled";
 2514                         #address-cells = <1>;
 2515                         #size-cells = <1>;
 2516                         ranges = <0x0 0x3a000 0x1000>;
 2517                 };
 2518 
 2519                 atl_tm: target-module@3c000 {           /* 0x4843c000, ap 23 08.0 */
 2520                         compatible = "ti,sysc-omap4", "ti,sysc";
 2521                         reg = <0x3c000 0x4>;
 2522                         reg-names = "rev";
 2523                         clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 0>;
 2524                         clock-names = "fck";
 2525                         #address-cells = <1>;
 2526                         #size-cells = <1>;
 2527                         ranges = <0x0 0x3c000 0x1000>;
 2528 
 2529                         atl: atl@0 {
 2530                                 compatible = "ti,dra7-atl";
 2531                                 reg = <0x0 0x3ff>;
 2532                                 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
 2533                                                      <&atl_clkin2_ck>, <&atl_clkin3_ck>;
 2534                                 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
 2535                                 clock-names = "fck";
 2536                                 status = "disabled";
 2537                         };
 2538                 };
 2539 
 2540                 target-module@3e000 {                   /* 0x4843e000, ap 25 30.0 */
 2541                         compatible = "ti,sysc-omap4", "ti,sysc";
 2542                         reg = <0x3e000 0x4>,
 2543                               <0x3e004 0x4>;
 2544                         reg-names = "rev", "sysc";
 2545                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 2546                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 2547                                         <SYSC_IDLE_NO>,
 2548                                         <SYSC_IDLE_SMART>;
 2549                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
 2550                         clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS0_CLKCTRL 0>;
 2551                         clock-names = "fck";
 2552                         #address-cells = <1>;
 2553                         #size-cells = <1>;
 2554                         ranges = <0x0 0x3e000 0x1000>;
 2555 
 2556                         epwmss0: epwmss@0 {
 2557                                 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
 2558                                 reg = <0x0 0x30>;
 2559                                 #address-cells = <1>;
 2560                                 #size-cells = <1>;
 2561                                 status = "disabled";
 2562                                 ranges = <0 0 0x1000>;
 2563 
 2564                                 ecap0: pwm@100 {
 2565                                         compatible = "ti,dra746-ecap",
 2566                                                      "ti,am3352-ecap";
 2567                                         #pwm-cells = <3>;
 2568                                         reg = <0x100 0x80>;
 2569                                         clocks = <&l4_root_clk_div>;
 2570                                         clock-names = "fck";
 2571                                         status = "disabled";
 2572                                 };
 2573 
 2574                                 ehrpwm0: pwm@200 {
 2575                                         compatible = "ti,dra746-ehrpwm",
 2576                                                      "ti,am3352-ehrpwm";
 2577                                         #pwm-cells = <3>;
 2578                                         reg = <0x200 0x80>;
 2579                                         clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
 2580                                         clock-names = "tbclk", "fck";
 2581                                         status = "disabled";
 2582                                 };
 2583                         };
 2584                 };
 2585 
 2586                 target-module@40000 {                   /* 0x48440000, ap 27 38.0 */
 2587                         compatible = "ti,sysc-omap4", "ti,sysc";
 2588                         reg = <0x40000 0x4>,
 2589                               <0x40004 0x4>;
 2590                         reg-names = "rev", "sysc";
 2591                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 2592                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 2593                                         <SYSC_IDLE_NO>,
 2594                                         <SYSC_IDLE_SMART>;
 2595                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
 2596                         clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS1_CLKCTRL 0>;
 2597                         clock-names = "fck";
 2598                         #address-cells = <1>;
 2599                         #size-cells = <1>;
 2600                         ranges = <0x0 0x40000 0x1000>;
 2601 
 2602                         epwmss1: epwmss@0 {
 2603                                 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
 2604                                 reg = <0x0 0x30>;
 2605                                 #address-cells = <1>;
 2606                                 #size-cells = <1>;
 2607                                 status = "disabled";
 2608                                 ranges = <0 0 0x1000>;
 2609 
 2610                                 ecap1: pwm@100 {
 2611                                         compatible = "ti,dra746-ecap",
 2612                                                      "ti,am3352-ecap";
 2613                                         #pwm-cells = <3>;
 2614                                         reg = <0x100 0x80>;
 2615                                         clocks = <&l4_root_clk_div>;
 2616                                         clock-names = "fck";
 2617                                         status = "disabled";
 2618                                 };
 2619 
 2620                                 ehrpwm1: pwm@200 {
 2621                                         compatible = "ti,dra746-ehrpwm",
 2622                                                      "ti,am3352-ehrpwm";
 2623                                         #pwm-cells = <3>;
 2624                                         reg = <0x200 0x80>;
 2625                                         clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
 2626                                         clock-names = "tbclk", "fck";
 2627                                         status = "disabled";
 2628                                 };
 2629                         };
 2630                 };
 2631 
 2632                 target-module@42000 {                   /* 0x48442000, ap 29 20.0 */
 2633                         compatible = "ti,sysc-omap4", "ti,sysc";
 2634                         reg = <0x42000 0x4>,
 2635                               <0x42004 0x4>;
 2636                         reg-names = "rev", "sysc";
 2637                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 2638                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 2639                                         <SYSC_IDLE_NO>,
 2640                                         <SYSC_IDLE_SMART>;
 2641                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
 2642                         clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS2_CLKCTRL 0>;
 2643                         clock-names = "fck";
 2644                         #address-cells = <1>;
 2645                         #size-cells = <1>;
 2646                         ranges = <0x0 0x42000 0x1000>;
 2647 
 2648                         epwmss2: epwmss@0 {
 2649                                 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
 2650                                 reg = <0x0 0x30>;
 2651                                 #address-cells = <1>;
 2652                                 #size-cells = <1>;
 2653                                 status = "disabled";
 2654                                 ranges = <0 0 0x1000>;
 2655 
 2656                                 ecap2: pwm@100 {
 2657                                         compatible = "ti,dra746-ecap",
 2658                                                      "ti,am3352-ecap";
 2659                                         #pwm-cells = <3>;
 2660                                         reg = <0x100 0x80>;
 2661                                         clocks = <&l4_root_clk_div>;
 2662                                         clock-names = "fck";
 2663                                         status = "disabled";
 2664                                 };
 2665 
 2666                                 ehrpwm2: pwm@200 {
 2667                                         compatible = "ti,dra746-ehrpwm",
 2668                                                      "ti,am3352-ehrpwm";
 2669                                         #pwm-cells = <3>;
 2670                                         reg = <0x200 0x80>;
 2671                                         clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
 2672                                         clock-names = "tbclk", "fck";
 2673                                         status = "disabled";
 2674                                 };
 2675                         };
 2676                 };
 2677 
 2678                 target-module@46000 {                   /* 0x48446000, ap 53 40.0 */
 2679                         compatible = "ti,sysc";
 2680                         status = "disabled";
 2681                         #address-cells = <1>;
 2682                         #size-cells = <1>;
 2683                         ranges = <0x0 0x46000 0x1000>;
 2684                 };
 2685 
 2686                 target-module@48000 {                   /* 0x48448000, ap 55 48.0 */
 2687                         compatible = "ti,sysc";
 2688                         status = "disabled";
 2689                         #address-cells = <1>;
 2690                         #size-cells = <1>;
 2691                         ranges = <0x0 0x48000 0x1000>;
 2692                 };
 2693 
 2694                 target-module@4a000 {                   /* 0x4844a000, ap 33 1a.0 */
 2695                         compatible = "ti,sysc";
 2696                         status = "disabled";
 2697                         #address-cells = <1>;
 2698                         #size-cells = <1>;
 2699                         ranges = <0x0 0x4a000 0x1000>;
 2700                 };
 2701 
 2702                 target-module@4c000 {                   /* 0x4844c000, ap 45 1c.0 */
 2703                         compatible = "ti,sysc";
 2704                         status = "disabled";
 2705                         #address-cells = <1>;
 2706                         #size-cells = <1>;
 2707                         ranges = <0x0 0x4c000 0x1000>;
 2708                 };
 2709 
 2710                 target-module@50000 {                   /* 0x48450000, ap 37 24.0 */
 2711                         compatible = "ti,sysc";
 2712                         status = "disabled";
 2713                         #address-cells = <1>;
 2714                         #size-cells = <1>;
 2715                         ranges = <0x0 0x50000 0x1000>;
 2716                 };
 2717 
 2718                 target-module@54000 {                   /* 0x48454000, ap 41 2c.0 */
 2719                         compatible = "ti,sysc";
 2720                         status = "disabled";
 2721                         #address-cells = <1>;
 2722                         #size-cells = <1>;
 2723                         ranges = <0x0 0x54000 0x1000>;
 2724                 };
 2725 
 2726                 target-module@58000 {                   /* 0x48458000, ap 57 28.0 */
 2727                         compatible = "ti,sysc";
 2728                         status = "disabled";
 2729                         #address-cells = <1>;
 2730                         #size-cells = <1>;
 2731                         ranges = <0x0 0x58000 0x2000>;
 2732                 };
 2733 
 2734                 target-module@5b000 {                   /* 0x4845b000, ap 59 46.0 */
 2735                         compatible = "ti,sysc";
 2736                         status = "disabled";
 2737                         #address-cells = <1>;
 2738                         #size-cells = <1>;
 2739                         ranges = <0x0 0x5b000 0x1000>;
 2740                 };
 2741 
 2742                 target-module@5d000 {                   /* 0x4845d000, ap 61 22.0 */
 2743                         compatible = "ti,sysc";
 2744                         status = "disabled";
 2745                         #address-cells = <1>;
 2746                         #size-cells = <1>;
 2747                         ranges = <0x0 0x5d000 0x1000>;
 2748                 };
 2749 
 2750                 target-module@60000 {                   /* 0x48460000, ap 9 0e.0 */
 2751                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
 2752                         reg = <0x60000 0x4>,
 2753                               <0x60004 0x4>;
 2754                         reg-names = "rev", "sysc";
 2755                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 2756                                         <SYSC_IDLE_NO>,
 2757                                         <SYSC_IDLE_SMART>;
 2758                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
 2759                         clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
 2760                                  <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
 2761                                  <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
 2762                         clock-names = "fck", "ahclkx", "ahclkr";
 2763                         #address-cells = <1>;
 2764                         #size-cells = <1>;
 2765                         ranges = <0x0 0x60000 0x2000>,
 2766                                  <0x45800000 0x45800000 0x400000>;
 2767 
 2768                         mcasp1: mcasp@0 {
 2769                                 compatible = "ti,dra7-mcasp-audio";
 2770                                 reg = <0x0 0x2000>,
 2771                                       <0x45800000 0x1000>;      /* L3 data port */
 2772                                 reg-names = "mpu","dat";
 2773                                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 2774                                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 2775                                 interrupt-names = "tx", "rx";
 2776                                 dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
 2777                                 dma-names = "tx", "rx";
 2778                                 clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
 2779                                          <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
 2780                                          <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
 2781                                 clock-names = "fck", "ahclkx", "ahclkr";
 2782                                 status = "disabled";
 2783                         };
 2784                 };
 2785 
 2786                 target-module@64000 {                   /* 0x48464000, ap 11 1e.0 */
 2787                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
 2788                         reg = <0x64000 0x4>,
 2789                               <0x64004 0x4>;
 2790                         reg-names = "rev", "sysc";
 2791                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 2792                                         <SYSC_IDLE_NO>,
 2793                                         <SYSC_IDLE_SMART>;
 2794                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
 2795                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
 2796                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>,
 2797                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
 2798                         clock-names = "fck", "ahclkx", "ahclkr";
 2799                         #address-cells = <1>;
 2800                         #size-cells = <1>;
 2801                         ranges = <0x0 0x64000 0x2000>,
 2802                                  <0x45c00000 0x45c00000 0x400000>;
 2803 
 2804                         mcasp2: mcasp@0 {
 2805                                 compatible = "ti,dra7-mcasp-audio";
 2806                                 reg = <0x0 0x2000>,
 2807                                       <0x45c00000 0x1000>;      /* L3 data port */
 2808                                 reg-names = "mpu","dat";
 2809                                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 2810                                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 2811                                 interrupt-names = "tx", "rx";
 2812                                 dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
 2813                                 dma-names = "tx", "rx";
 2814                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
 2815                                          <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
 2816                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
 2817                                 clock-names = "fck", "ahclkx", "ahclkr";
 2818                                 status = "disabled";
 2819                         };
 2820                 };
 2821 
 2822                 target-module@68000 {                   /* 0x48468000, ap 13 26.0 */
 2823                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
 2824                         reg = <0x68000 0x4>,
 2825                               <0x68004 0x4>;
 2826                         reg-names = "rev", "sysc";
 2827                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 2828                                         <SYSC_IDLE_NO>,
 2829                                         <SYSC_IDLE_SMART>;
 2830                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
 2831                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
 2832                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
 2833                         clock-names = "fck", "ahclkx";
 2834                         #address-cells = <1>;
 2835                         #size-cells = <1>;
 2836                         ranges = <0x0 0x68000 0x2000>,
 2837                                  <0x46000000 0x46000000 0x400000>;
 2838 
 2839                         mcasp3: mcasp@0 {
 2840                                 compatible = "ti,dra7-mcasp-audio";
 2841                                 reg = <0x0 0x2000>,
 2842                                       <0x46000000 0x1000>;      /* L3 data port */
 2843                                 reg-names = "mpu","dat";
 2844                                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
 2845                                              <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 2846                                 interrupt-names = "tx", "rx";
 2847                                 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
 2848                                 dma-names = "tx", "rx";
 2849                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
 2850                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
 2851                                 clock-names = "fck", "ahclkx";
 2852                                 status = "disabled";
 2853                         };
 2854                 };
 2855 
 2856                 target-module@6c000 {                   /* 0x4846c000, ap 15 2e.0 */
 2857                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
 2858                         reg = <0x6c000 0x4>,
 2859                               <0x6c004 0x4>;
 2860                         reg-names = "rev", "sysc";
 2861                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 2862                                         <SYSC_IDLE_NO>,
 2863                                         <SYSC_IDLE_SMART>;
 2864                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
 2865                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
 2866                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
 2867                         clock-names = "fck", "ahclkx";
 2868                         #address-cells = <1>;
 2869                         #size-cells = <1>;
 2870                         ranges = <0x0 0x6c000 0x2000>,
 2871                                  <0x48436000 0x48436000 0x400000>;
 2872 
 2873                         mcasp4: mcasp@0 {
 2874                                 compatible = "ti,dra7-mcasp-audio";
 2875                                 reg = <0x0 0x2000>,
 2876                                       <0x48436000 0x1000>;      /* L3 data port */
 2877                                 reg-names = "mpu","dat";
 2878                                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 2879                                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 2880                                 interrupt-names = "tx", "rx";
 2881                                 dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
 2882                                 dma-names = "tx", "rx";
 2883                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
 2884                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
 2885                                 clock-names = "fck", "ahclkx";
 2886                                 status = "disabled";
 2887                         };
 2888                 };
 2889 
 2890                 target-module@70000 {                   /* 0x48470000, ap 19 36.0 */
 2891                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
 2892                         reg = <0x70000 0x4>,
 2893                               <0x70004 0x4>;
 2894                         reg-names = "rev", "sysc";
 2895                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 2896                                         <SYSC_IDLE_NO>,
 2897                                         <SYSC_IDLE_SMART>;
 2898                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
 2899                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
 2900                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
 2901                         clock-names = "fck", "ahclkx";
 2902                         #address-cells = <1>;
 2903                         #size-cells = <1>;
 2904                         ranges = <0x0 0x70000 0x2000>,
 2905                                  <0x4843a000 0x4843a000 0x400000>;
 2906 
 2907                         mcasp5: mcasp@0 {
 2908                                 compatible = "ti,dra7-mcasp-audio";
 2909                                 reg = <0x0 0x2000>,
 2910                                       <0x4843a000 0x1000>;      /* L3 data port */
 2911                                 reg-names = "mpu","dat";
 2912                                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 2913                                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 2914                                 interrupt-names = "tx", "rx";
 2915                                 dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
 2916                                 dma-names = "tx", "rx";
 2917                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
 2918                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
 2919                                 clock-names = "fck", "ahclkx";
 2920                                 status = "disabled";
 2921                         };
 2922                 };
 2923 
 2924                 target-module@74000 {                   /* 0x48474000, ap 35 14.0 */
 2925                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
 2926                         reg = <0x74000 0x4>,
 2927                               <0x74004 0x4>;
 2928                         reg-names = "rev", "sysc";
 2929                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 2930                                         <SYSC_IDLE_NO>,
 2931                                         <SYSC_IDLE_SMART>;
 2932                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
 2933                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
 2934                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
 2935                         clock-names = "fck", "ahclkx";
 2936                         #address-cells = <1>;
 2937                         #size-cells = <1>;
 2938                         ranges = <0x0 0x74000 0x2000>,
 2939                                  <0x4844c000 0x4844c000 0x400000>;
 2940 
 2941                         mcasp6: mcasp@0 {
 2942                                 compatible = "ti,dra7-mcasp-audio";
 2943                                 reg = <0x0 0x2000>,
 2944                                       <0x4844c000 0x1000>;      /* L3 data port */
 2945                                 reg-names = "mpu","dat";
 2946                                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 2947                                              <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 2948                                 interrupt-names = "tx", "rx";
 2949                                 dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
 2950                                 dma-names = "tx", "rx";
 2951                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
 2952                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
 2953                                 clock-names = "fck", "ahclkx";
 2954                                 status = "disabled";
 2955                         };
 2956                 };
 2957 
 2958                 target-module@78000 {                   /* 0x48478000, ap 39 0c.0 */
 2959                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
 2960                         reg = <0x78000 0x4>,
 2961                               <0x78004 0x4>;
 2962                         reg-names = "rev", "sysc";
 2963                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 2964                                         <SYSC_IDLE_NO>,
 2965                                         <SYSC_IDLE_SMART>;
 2966                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
 2967                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
 2968                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
 2969                         clock-names = "fck", "ahclkx";
 2970                         #address-cells = <1>;
 2971                         #size-cells = <1>;
 2972                         ranges = <0x0 0x78000 0x2000>,
 2973                                  <0x48450000 0x48450000 0x400000>;
 2974 
 2975                         mcasp7: mcasp@0 {
 2976                                 compatible = "ti,dra7-mcasp-audio";
 2977                                 reg = <0x0 0x2000>,
 2978                                       <0x48450000 0x1000>;      /* L3 data port */
 2979                                 reg-names = "mpu","dat";
 2980                                 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
 2981                                              <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 2982                                 interrupt-names = "tx", "rx";
 2983                                 dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
 2984                                 dma-names = "tx", "rx";
 2985                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
 2986                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
 2987                                 clock-names = "fck", "ahclkx";
 2988                                 status = "disabled";
 2989                         };
 2990                 };
 2991 
 2992                 target-module@7c000 {                   /* 0x4847c000, ap 43 04.0 */
 2993                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
 2994                         reg = <0x7c000 0x4>,
 2995                               <0x7c004 0x4>;
 2996                         reg-names = "rev", "sysc";
 2997                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 2998                                         <SYSC_IDLE_NO>,
 2999                                         <SYSC_IDLE_SMART>;
 3000                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
 3001                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
 3002                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
 3003                         clock-names = "fck", "ahclkx";
 3004                         #address-cells = <1>;
 3005                         #size-cells = <1>;
 3006                         ranges = <0x0 0x7c000 0x2000>,
 3007                                  <0x48454000 0x48454000 0x400000>;
 3008 
 3009                         mcasp8: mcasp@0 {
 3010                                 compatible = "ti,dra7-mcasp-audio";
 3011                                 reg = <0x0 0x2000>,
 3012                                       <0x48454000 0x1000>;      /* L3 data port */
 3013                                 reg-names = "mpu","dat";
 3014                                 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 3015                                              <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
 3016                                 interrupt-names = "tx", "rx";
 3017                                 dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
 3018                                 dma-names = "tx", "rx";
 3019                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
 3020                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
 3021                                 clock-names = "fck", "ahclkx";
 3022                                 status = "disabled";
 3023                         };
 3024                 };
 3025 
 3026                 target-module@80000 {                   /* 0x48480000, ap 31 16.0 */
 3027                         compatible = "ti,sysc-omap4", "ti,sysc";
 3028                         reg = <0x80020 0x4>;
 3029                         reg-names = "rev";
 3030                         clocks = <&l4per2_clkctrl DRA7_L4PER2_DCAN2_CLKCTRL 0>;
 3031                         clock-names = "fck";
 3032                         #address-cells = <1>;
 3033                         #size-cells = <1>;
 3034                         ranges = <0x0 0x80000 0x2000>;
 3035 
 3036                         dcan2: can@0 {
 3037                                 compatible = "ti,dra7-d_can";
 3038                                 reg = <0x0 0x2000>;
 3039                                 syscon-raminit = <&scm_conf 0x558 1>;
 3040                                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 3041                                 clocks = <&sys_clkin1>;
 3042                                 status = "disabled";
 3043                         };
 3044                 };
 3045 
 3046                 target-module@84000 {                   /* 0x48484000, ap 3 10.0 */
 3047                         compatible = "ti,sysc-omap4-simple", "ti,sysc";
 3048                         reg = <0x85200 0x4>,
 3049                               <0x85208 0x4>,
 3050                               <0x85204 0x4>;
 3051                         reg-names = "rev", "sysc", "syss";
 3052                         ti,sysc-mask = <0>;
 3053                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 3054                                         <SYSC_IDLE_NO>;
 3055                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 3056                                         <SYSC_IDLE_NO>;
 3057                         ti,syss-mask = <1>;
 3058                         clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
 3059                         clock-names = "fck";
 3060                         #address-cells = <1>;
 3061                         #size-cells = <1>;
 3062                         ranges = <0x0 0x84000 0x4000>;
 3063                         /*
 3064                          * Do not allow gating of cpsw clock as workaround
 3065                          * for errata i877. Keeping internal clock disabled
 3066                          * causes the device switching characteristics
 3067                          * to degrade over time and eventually fail to meet
 3068                          * the data manual delay time/skew specs.
 3069                          */
 3070                         ti,no-idle;
 3071 
 3072                         mac_sw: switch@0 {
 3073                                 compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch";
 3074                                 reg = <0x0 0x4000>;
 3075                                 ranges = <0 0 0x4000>;
 3076                                 clocks = <&gmac_main_clk>;
 3077                                 clock-names = "fck";
 3078                                 #address-cells = <1>;
 3079                                 #size-cells = <1>;
 3080                                 syscon = <&scm_conf>;
 3081                                 status = "disabled";
 3082 
 3083                                 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
 3084                                              <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
 3085                                              <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
 3086                                              <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
 3087                                 interrupt-names = "rx_thresh", "rx", "tx", "misc";
 3088 
 3089                                 ethernet-ports {
 3090                                         #address-cells = <1>;
 3091                                         #size-cells = <0>;
 3092 
 3093                                         cpsw_port1: port@1 {
 3094                                                 reg = <1>;
 3095                                                 label = "port1";
 3096                                                 mac-address = [ 00 00 00 00 00 00 ];
 3097                                                 phys = <&phy_gmii_sel 1>;
 3098                                         };
 3099 
 3100                                         cpsw_port2: port@2 {
 3101                                                 reg = <2>;
 3102                                                 label = "port2";
 3103                                                 mac-address = [ 00 00 00 00 00 00 ];
 3104                                                 phys = <&phy_gmii_sel 2>;
 3105                                         };
 3106                                 };
 3107 
 3108                                 davinci_mdio_sw: mdio@1000 {
 3109                                         compatible = "ti,cpsw-mdio","ti,davinci_mdio";
 3110                                         clocks = <&gmac_main_clk>;
 3111                                         clock-names = "fck";
 3112                                         #address-cells = <1>;
 3113                                         #size-cells = <0>;
 3114                                         bus_freq = <1000000>;
 3115                                         reg = <0x1000 0x100>;
 3116                                 };
 3117 
 3118                                 cpts {
 3119                                         clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;
 3120                                         clock-names = "cpts";
 3121                                 };
 3122                         };
 3123                 };
 3124         };
 3125 };
 3126 
 3127 &l4_per3 {                                              /* 0x48800000 */
 3128         compatible = "ti,dra7-l4-per3", "simple-pm-bus";
 3129         power-domains = <&prm_l4per>;
 3130         clocks = <&l4per3_clkctrl DRA7_L4PER3_L4_PER3_CLKCTRL 0>;
 3131         clock-names = "fck";
 3132         reg = <0x48800000 0x800>,
 3133               <0x48800800 0x800>,
 3134               <0x48801000 0x400>,
 3135               <0x48801400 0x400>,
 3136               <0x48801800 0x400>;
 3137         reg-names = "ap", "la", "ia0", "ia1", "ia2";
 3138         #address-cells = <1>;
 3139         #size-cells = <1>;
 3140         ranges = <0x00000000 0x48800000 0x200000>;      /* segment 0 */
 3141 
 3142         segment@0 {                                     /* 0x48800000 */
 3143                 compatible = "simple-pm-bus";
 3144                 #address-cells = <1>;
 3145                 #size-cells = <1>;
 3146                 ranges = <0x00000000 0x00000000 0x000800>,      /* ap 0 */
 3147                          <0x00000800 0x00000800 0x000800>,      /* ap 1 */
 3148                          <0x00001000 0x00001000 0x000400>,      /* ap 2 */
 3149                          <0x00001400 0x00001400 0x000400>,      /* ap 3 */
 3150                          <0x00001800 0x00001800 0x000400>,      /* ap 4 */
 3151                          <0x00020000 0x00020000 0x001000>,      /* ap 5 */
 3152                          <0x00021000 0x00021000 0x001000>,      /* ap 6 */
 3153                          <0x00022000 0x00022000 0x001000>,      /* ap 7 */
 3154                          <0x00023000 0x00023000 0x001000>,      /* ap 8 */
 3155                          <0x00024000 0x00024000 0x001000>,      /* ap 9 */
 3156                          <0x00025000 0x00025000 0x001000>,      /* ap 10 */
 3157                          <0x00026000 0x00026000 0x001000>,      /* ap 11 */
 3158                          <0x00027000 0x00027000 0x001000>,      /* ap 12 */
 3159                          <0x00028000 0x00028000 0x001000>,      /* ap 13 */
 3160                          <0x00029000 0x00029000 0x001000>,      /* ap 14 */
 3161                          <0x0002a000 0x0002a000 0x001000>,      /* ap 15 */
 3162                          <0x0002b000 0x0002b000 0x001000>,      /* ap 16 */
 3163                          <0x0002c000 0x0002c000 0x001000>,      /* ap 17 */
 3164                          <0x0002d000 0x0002d000 0x001000>,      /* ap 18 */
 3165                          <0x0002e000 0x0002e000 0x001000>,      /* ap 19 */
 3166                          <0x0002f000 0x0002f000 0x001000>,      /* ap 20 */
 3167                          <0x00170000 0x00170000 0x010000>,      /* ap 21 */
 3168                          <0x00180000 0x00180000 0x001000>,      /* ap 22 */
 3169                          <0x00190000 0x00190000 0x010000>,      /* ap 23 */
 3170                          <0x001a0000 0x001a0000 0x001000>,      /* ap 24 */
 3171                          <0x001b0000 0x001b0000 0x010000>,      /* ap 25 */
 3172                          <0x001c0000 0x001c0000 0x001000>,      /* ap 26 */
 3173                          <0x001d0000 0x001d0000 0x010000>,      /* ap 27 */
 3174                          <0x001e0000 0x001e0000 0x001000>,      /* ap 28 */
 3175                          <0x00038000 0x00038000 0x001000>,      /* ap 29 */
 3176                          <0x00039000 0x00039000 0x001000>,      /* ap 30 */
 3177                          <0x0005c000 0x0005c000 0x001000>,      /* ap 31 */
 3178                          <0x0005d000 0x0005d000 0x001000>,      /* ap 32 */
 3179                          <0x0003a000 0x0003a000 0x001000>,      /* ap 33 */
 3180                          <0x0003b000 0x0003b000 0x001000>,      /* ap 34 */
 3181                          <0x0003c000 0x0003c000 0x001000>,      /* ap 35 */
 3182                          <0x0003d000 0x0003d000 0x001000>,      /* ap 36 */
 3183                          <0x0003e000 0x0003e000 0x001000>,      /* ap 37 */
 3184                          <0x0003f000 0x0003f000 0x001000>,      /* ap 38 */
 3185                          <0x00040000 0x00040000 0x001000>,      /* ap 39 */
 3186                          <0x00041000 0x00041000 0x001000>,      /* ap 40 */
 3187                          <0x00042000 0x00042000 0x001000>,      /* ap 41 */
 3188                          <0x00043000 0x00043000 0x001000>,      /* ap 42 */
 3189                          <0x00044000 0x00044000 0x001000>,      /* ap 43 */
 3190                          <0x00045000 0x00045000 0x001000>,      /* ap 44 */
 3191                          <0x00046000 0x00046000 0x001000>,      /* ap 45 */
 3192                          <0x00047000 0x00047000 0x001000>,      /* ap 46 */
 3193                          <0x00048000 0x00048000 0x001000>,      /* ap 47 */
 3194                          <0x00049000 0x00049000 0x001000>,      /* ap 48 */
 3195                          <0x0004a000 0x0004a000 0x001000>,      /* ap 49 */
 3196                          <0x0004b000 0x0004b000 0x001000>,      /* ap 50 */
 3197                          <0x0004c000 0x0004c000 0x001000>,      /* ap 51 */
 3198                          <0x0004d000 0x0004d000 0x001000>,      /* ap 52 */
 3199                          <0x0004e000 0x0004e000 0x001000>,      /* ap 53 */
 3200                          <0x0004f000 0x0004f000 0x001000>,      /* ap 54 */
 3201                          <0x00050000 0x00050000 0x001000>,      /* ap 55 */
 3202                          <0x00051000 0x00051000 0x001000>,      /* ap 56 */
 3203                          <0x00052000 0x00052000 0x001000>,      /* ap 57 */
 3204                          <0x00053000 0x00053000 0x001000>,      /* ap 58 */
 3205                          <0x00054000 0x00054000 0x001000>,      /* ap 59 */
 3206                          <0x00055000 0x00055000 0x001000>,      /* ap 60 */
 3207                          <0x00056000 0x00056000 0x001000>,      /* ap 61 */
 3208                          <0x00057000 0x00057000 0x001000>,      /* ap 62 */
 3209                          <0x00058000 0x00058000 0x001000>,      /* ap 63 */
 3210                          <0x00059000 0x00059000 0x001000>,      /* ap 64 */
 3211                          <0x0005a000 0x0005a000 0x001000>,      /* ap 65 */
 3212                          <0x0005b000 0x0005b000 0x001000>,      /* ap 66 */
 3213                          <0x00064000 0x00064000 0x001000>,      /* ap 67 */
 3214                          <0x00065000 0x00065000 0x001000>,      /* ap 68 */
 3215                          <0x0005e000 0x0005e000 0x001000>,      /* ap 69 */
 3216                          <0x0005f000 0x0005f000 0x001000>,      /* ap 70 */
 3217                          <0x00060000 0x00060000 0x001000>,      /* ap 71 */
 3218                          <0x00061000 0x00061000 0x001000>,      /* ap 72 */
 3219                          <0x00062000 0x00062000 0x001000>,      /* ap 73 */
 3220                          <0x00063000 0x00063000 0x001000>,      /* ap 74 */
 3221                          <0x00140000 0x00140000 0x020000>,      /* ap 75 */
 3222                          <0x00160000 0x00160000 0x001000>,      /* ap 76 */
 3223                          <0x00016000 0x00016000 0x001000>,      /* ap 77 */
 3224                          <0x00017000 0x00017000 0x001000>,      /* ap 78 */
 3225                          <0x000c0000 0x000c0000 0x020000>,      /* ap 79 */
 3226                          <0x000e0000 0x000e0000 0x001000>,      /* ap 80 */
 3227                          <0x00004000 0x00004000 0x001000>,      /* ap 81 */
 3228                          <0x00005000 0x00005000 0x001000>,      /* ap 82 */
 3229                          <0x00080000 0x00080000 0x020000>,      /* ap 83 */
 3230                          <0x000a0000 0x000a0000 0x001000>,      /* ap 84 */
 3231                          <0x00100000 0x00100000 0x020000>,      /* ap 85 */
 3232                          <0x00120000 0x00120000 0x001000>,      /* ap 86 */
 3233                          <0x00010000 0x00010000 0x001000>,      /* ap 87 */
 3234                          <0x00011000 0x00011000 0x001000>,      /* ap 88 */
 3235                          <0x0000a000 0x0000a000 0x001000>,      /* ap 89 */
 3236                          <0x0000b000 0x0000b000 0x001000>,      /* ap 90 */
 3237                          <0x0001c000 0x0001c000 0x001000>,      /* ap 91 */
 3238                          <0x0001d000 0x0001d000 0x001000>,      /* ap 92 */
 3239                          <0x0001e000 0x0001e000 0x001000>,      /* ap 93 */
 3240                          <0x0001f000 0x0001f000 0x001000>,      /* ap 94 */
 3241                          <0x00002000 0x00002000 0x001000>,      /* ap 95 */
 3242                          <0x00003000 0x00003000 0x001000>;      /* ap 96 */
 3243 
 3244                 target-module@2000 {                    /* 0x48802000, ap 95 7c.0 */
 3245                         compatible = "ti,sysc-omap4", "ti,sysc";
 3246                         reg = <0x2000 0x4>,
 3247                               <0x2010 0x4>;
 3248                         reg-names = "rev", "sysc";
 3249                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 3250                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 3251                                         <SYSC_IDLE_NO>,
 3252                                         <SYSC_IDLE_SMART>;
 3253                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
 3254                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX13_CLKCTRL 0>;
 3255                         clock-names = "fck";
 3256                         #address-cells = <1>;
 3257                         #size-cells = <1>;
 3258                         ranges = <0x0 0x2000 0x1000>;
 3259 
 3260                         mailbox13: mailbox@0 {
 3261                                 compatible = "ti,omap4-mailbox";
 3262                                 reg = <0x0 0x200>;
 3263                                 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
 3264                                              <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
 3265                                              <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
 3266                                              <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
 3267                                 #mbox-cells = <1>;
 3268                                 ti,mbox-num-users = <4>;
 3269                                 ti,mbox-num-fifos = <12>;
 3270                                 status = "disabled";
 3271                         };
 3272                 };
 3273 
 3274                 target-module@4000 {                    /* 0x48804000, ap 81 20.0 */
 3275                         compatible = "ti,sysc";
 3276                         status = "disabled";
 3277                         #address-cells = <1>;
 3278                         #size-cells = <1>;
 3279                         ranges = <0x0 0x4000 0x1000>;
 3280                 };
 3281 
 3282                 target-module@a000 {                    /* 0x4880a000, ap 89 18.0 */
 3283                         compatible = "ti,sysc";
 3284                         status = "disabled";
 3285                         #address-cells = <1>;
 3286                         #size-cells = <1>;
 3287                         ranges = <0x0 0xa000 0x1000>;
 3288                 };
 3289 
 3290                 target-module@10000 {                   /* 0x48810000, ap 87 28.0 */
 3291                         compatible = "ti,sysc";
 3292                         status = "disabled";
 3293                         #address-cells = <1>;
 3294                         #size-cells = <1>;
 3295                         ranges = <0x0 0x10000 0x1000>;
 3296                 };
 3297 
 3298                 target-module@16000 {                   /* 0x48816000, ap 77 1e.0 */
 3299                         compatible = "ti,sysc";
 3300                         status = "disabled";
 3301                         #address-cells = <1>;
 3302                         #size-cells = <1>;
 3303                         ranges = <0x0 0x16000 0x1000>;
 3304                 };
 3305 
 3306                 target-module@1c000 {                   /* 0x4881c000, ap 91 1c.0 */
 3307                         compatible = "ti,sysc";
 3308                         status = "disabled";
 3309                         #address-cells = <1>;
 3310                         #size-cells = <1>;
 3311                         ranges = <0x0 0x1c000 0x1000>;
 3312                 };
 3313 
 3314                 target-module@1e000 {                   /* 0x4881e000, ap 93 2c.0 */
 3315                         compatible = "ti,sysc";
 3316                         status = "disabled";
 3317                         #address-cells = <1>;
 3318                         #size-cells = <1>;
 3319                         ranges = <0x0 0x1e000 0x1000>;
 3320                 };
 3321 
 3322                 target-module@20000 {                   /* 0x48820000, ap 5 08.0 */
 3323                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 3324                         reg = <0x20000 0x4>,
 3325                               <0x20010 0x4>;
 3326                         reg-names = "rev", "sysc";
 3327                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 3328                                          SYSC_OMAP4_SOFTRESET)>;
 3329                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 3330                                         <SYSC_IDLE_NO>,
 3331                                         <SYSC_IDLE_SMART>,
 3332                                         <SYSC_IDLE_SMART_WKUP>;
 3333                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
 3334                         clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>;
 3335                         clock-names = "fck";
 3336                         #address-cells = <1>;
 3337                         #size-cells = <1>;
 3338                         ranges = <0x0 0x20000 0x1000>;
 3339 
 3340                         timer5: timer@0 {
 3341                                 compatible = "ti,omap5430-timer";
 3342                                 reg = <0x0 0x80>;
 3343                                 clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>, <&timer_sys_clk_div>;
 3344                                 clock-names = "fck", "timer_sys_ck";
 3345                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 3346                         };
 3347                 };
 3348 
 3349                 target-module@22000 {                   /* 0x48822000, ap 7 24.0 */
 3350                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 3351                         reg = <0x22000 0x4>,
 3352                               <0x22010 0x4>;
 3353                         reg-names = "rev", "sysc";
 3354                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 3355                                          SYSC_OMAP4_SOFTRESET)>;
 3356                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 3357                                         <SYSC_IDLE_NO>,
 3358                                         <SYSC_IDLE_SMART>,
 3359                                         <SYSC_IDLE_SMART_WKUP>;
 3360                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
 3361                         clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>;
 3362                         clock-names = "fck";
 3363                         #address-cells = <1>;
 3364                         #size-cells = <1>;
 3365                         ranges = <0x0 0x22000 0x1000>;
 3366 
 3367                         timer6: timer@0 {
 3368                                 compatible = "ti,omap5430-timer";
 3369                                 reg = <0x0 0x80>;
 3370                                 clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>, <&timer_sys_clk_div>;
 3371                                 clock-names = "fck", "timer_sys_ck";
 3372                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 3373                         };
 3374                 };
 3375 
 3376                 target-module@24000 {                   /* 0x48824000, ap 9 26.0 */
 3377                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 3378                         reg = <0x24000 0x4>,
 3379                               <0x24010 0x4>;
 3380                         reg-names = "rev", "sysc";
 3381                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 3382                                          SYSC_OMAP4_SOFTRESET)>;
 3383                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 3384                                         <SYSC_IDLE_NO>,
 3385                                         <SYSC_IDLE_SMART>,
 3386                                         <SYSC_IDLE_SMART_WKUP>;
 3387                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
 3388                         clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 0>;
 3389                         clock-names = "fck";
 3390                         #address-cells = <1>;
 3391                         #size-cells = <1>;
 3392                         ranges = <0x0 0x24000 0x1000>;
 3393 
 3394                         timer7: timer@0 {
 3395                                 compatible = "ti,omap5430-timer";
 3396                                 reg = <0x0 0x80>;
 3397                                 clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>, <&timer_sys_clk_div>;
 3398                                 clock-names = "fck", "timer_sys_ck";
 3399                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 3400                         };
 3401                 };
 3402 
 3403                 target-module@26000 {                   /* 0x48826000, ap 11 0c.0 */
 3404                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 3405                         reg = <0x26000 0x4>,
 3406                               <0x26010 0x4>;
 3407                         reg-names = "rev", "sysc";
 3408                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 3409                                          SYSC_OMAP4_SOFTRESET)>;
 3410                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 3411                                         <SYSC_IDLE_NO>,
 3412                                         <SYSC_IDLE_SMART>,
 3413                                         <SYSC_IDLE_SMART_WKUP>;
 3414                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
 3415                         clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 0>;
 3416                         clock-names = "fck";
 3417                         #address-cells = <1>;
 3418                         #size-cells = <1>;
 3419                         ranges = <0x0 0x26000 0x1000>;
 3420 
 3421                         timer8: timer@0 {
 3422                                 compatible = "ti,omap5430-timer";
 3423                                 reg = <0x0 0x80>;
 3424                                 clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>, <&timer_sys_clk_div>;
 3425                                 clock-names = "fck", "timer_sys_ck";
 3426                                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 3427                         };
 3428                 };
 3429 
 3430                 target-module@28000 {                   /* 0x48828000, ap 13 16.0 */
 3431                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 3432                         reg = <0x28000 0x4>,
 3433                               <0x28010 0x4>;
 3434                         reg-names = "rev", "sysc";
 3435                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 3436                                          SYSC_OMAP4_SOFTRESET)>;
 3437                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 3438                                         <SYSC_IDLE_NO>,
 3439                                         <SYSC_IDLE_SMART>,
 3440                                         <SYSC_IDLE_SMART_WKUP>;
 3441                         /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
 3442                         clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 0>;
 3443                         clock-names = "fck";
 3444                         #address-cells = <1>;
 3445                         #size-cells = <1>;
 3446                         ranges = <0x0 0x28000 0x1000>;
 3447 
 3448                         timer13: timer@0 {
 3449                                 compatible = "ti,omap5430-timer";
 3450                                 reg = <0x0 0x80>;
 3451                                 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>, <&timer_sys_clk_div>;
 3452                                 clock-names = "fck", "timer_sys_ck";
 3453                                 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
 3454                                 ti,timer-pwm;
 3455                         };
 3456                 };
 3457 
 3458                 target-module@2a000 {                   /* 0x4882a000, ap 15 10.0 */
 3459                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 3460                         reg = <0x2a000 0x4>,
 3461                               <0x2a010 0x4>;
 3462                         reg-names = "rev", "sysc";
 3463                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 3464                                          SYSC_OMAP4_SOFTRESET)>;
 3465                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 3466                                         <SYSC_IDLE_NO>,
 3467                                         <SYSC_IDLE_SMART>,
 3468                                         <SYSC_IDLE_SMART_WKUP>;
 3469                         /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
 3470                         clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 0>;
 3471                         clock-names = "fck";
 3472                         #address-cells = <1>;
 3473                         #size-cells = <1>;
 3474                         ranges = <0x0 0x2a000 0x1000>;
 3475 
 3476                         timer14: timer@0 {
 3477                                 compatible = "ti,omap5430-timer";
 3478                                 reg = <0x0 0x80>;
 3479                                 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>, <&timer_sys_clk_div>;
 3480                                 clock-names = "fck", "timer_sys_ck";
 3481                                 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
 3482                                 ti,timer-pwm;
 3483                         };
 3484                 };
 3485                 timer15_target: target-module@2c000 {   /* 0x4882c000, ap 17 02.0 */
 3486                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 3487                         reg = <0x2c000 0x4>,
 3488                               <0x2c010 0x4>;
 3489                         reg-names = "rev", "sysc";
 3490                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 3491                                          SYSC_OMAP4_SOFTRESET)>;
 3492                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 3493                                         <SYSC_IDLE_NO>,
 3494                                         <SYSC_IDLE_SMART>,
 3495                                         <SYSC_IDLE_SMART_WKUP>;
 3496                         /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
 3497                         clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 0>;
 3498                         clock-names = "fck";
 3499                         #address-cells = <1>;
 3500                         #size-cells = <1>;
 3501                         ranges = <0x0 0x2c000 0x1000>;
 3502 
 3503                         timer15: timer@0 {
 3504                                 compatible = "ti,omap5430-timer";
 3505                                 reg = <0x0 0x80>;
 3506                                 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>, <&timer_sys_clk_div>;
 3507                                 clock-names = "fck", "timer_sys_ck";
 3508                                 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
 3509                                 ti,timer-pwm;
 3510                         };
 3511                 };
 3512 
 3513                 timer16_target: target-module@2e000 {   /* 0x4882e000, ap 19 14.0 */
 3514                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 3515                         reg = <0x2e000 0x4>,
 3516                               <0x2e010 0x4>;
 3517                         reg-names = "rev", "sysc";
 3518                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 3519                                          SYSC_OMAP4_SOFTRESET)>;
 3520                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 3521                                         <SYSC_IDLE_NO>,
 3522                                         <SYSC_IDLE_SMART>,
 3523                                         <SYSC_IDLE_SMART_WKUP>;
 3524                         /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
 3525                         clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 0>;
 3526                         clock-names = "fck";
 3527                         #address-cells = <1>;
 3528                         #size-cells = <1>;
 3529                         ranges = <0x0 0x2e000 0x1000>;
 3530 
 3531                         timer16: timer@0 {
 3532                                 compatible = "ti,omap5430-timer";
 3533                                 reg = <0x0 0x80>;
 3534                                 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>, <&timer_sys_clk_div>;
 3535                                 clock-names = "fck", "timer_sys_ck";
 3536                                 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
 3537                                 ti,timer-pwm;
 3538                         };
 3539                 };
 3540 
 3541                 rtctarget: target-module@38000 {                        /* 0x48838000, ap 29 12.0 */
 3542                         compatible = "ti,sysc-omap4-simple", "ti,sysc";
 3543                         reg = <0x38074 0x4>,
 3544                               <0x38078 0x4>;
 3545                         reg-names = "rev", "sysc";
 3546                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 3547                                         <SYSC_IDLE_NO>,
 3548                                         <SYSC_IDLE_SMART>,
 3549                                         <SYSC_IDLE_SMART_WKUP>;
 3550                         /* Domains (P, C): rtc_pwrdm, rtc_clkdm */
 3551                         clocks = <&rtc_clkctrl DRA7_RTC_RTCSS_CLKCTRL 0>;
 3552                         clock-names = "fck";
 3553                         #address-cells = <1>;
 3554                         #size-cells = <1>;
 3555                         ranges = <0x0 0x38000 0x1000>;
 3556 
 3557                         rtc: rtc@0 {
 3558                                 compatible = "ti,am3352-rtc";
 3559                                 reg = <0x0 0x100>;
 3560                                 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
 3561                                              <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
 3562                                 clocks = <&sys_32k_ck>;
 3563                         };
 3564                 };
 3565 
 3566                 target-module@3a000 {                   /* 0x4883a000, ap 33 3e.0 */
 3567                         compatible = "ti,sysc-omap4", "ti,sysc";
 3568                         reg = <0x3a000 0x4>,
 3569                               <0x3a010 0x4>;
 3570                         reg-names = "rev", "sysc";
 3571                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 3572                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 3573                                         <SYSC_IDLE_NO>,
 3574                                         <SYSC_IDLE_SMART>;
 3575                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
 3576                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX2_CLKCTRL 0>;
 3577                         clock-names = "fck";
 3578                         #address-cells = <1>;
 3579                         #size-cells = <1>;
 3580                         ranges = <0x0 0x3a000 0x1000>;
 3581 
 3582                         mailbox2: mailbox@0 {
 3583                                 compatible = "ti,omap4-mailbox";
 3584                                 reg = <0x0 0x200>;
 3585                                 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
 3586                                              <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
 3587                                              <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
 3588                                              <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 3589                                 #mbox-cells = <1>;
 3590                                 ti,mbox-num-users = <4>;
 3591                                 ti,mbox-num-fifos = <12>;
 3592                                 status = "disabled";
 3593                         };
 3594                 };
 3595 
 3596                 target-module@3c000 {                   /* 0x4883c000, ap 35 3a.0 */
 3597                         compatible = "ti,sysc-omap4", "ti,sysc";
 3598                         reg = <0x3c000 0x4>,
 3599                               <0x3c010 0x4>;
 3600                         reg-names = "rev", "sysc";
 3601                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 3602                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 3603                                         <SYSC_IDLE_NO>,
 3604                                         <SYSC_IDLE_SMART>;
 3605                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
 3606                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX3_CLKCTRL 0>;
 3607                         clock-names = "fck";
 3608                         #address-cells = <1>;
 3609                         #size-cells = <1>;
 3610                         ranges = <0x0 0x3c000 0x1000>;
 3611 
 3612                         mailbox3: mailbox@0 {
 3613                                 compatible = "ti,omap4-mailbox";
 3614                                 reg = <0x0 0x200>;
 3615                                 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
 3616                                              <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
 3617                                              <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
 3618                                              <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
 3619                                 #mbox-cells = <1>;
 3620                                 ti,mbox-num-users = <4>;
 3621                                 ti,mbox-num-fifos = <12>;
 3622                                 status = "disabled";
 3623                         };
 3624                 };
 3625 
 3626                 target-module@3e000 {                   /* 0x4883e000, ap 37 46.0 */
 3627                         compatible = "ti,sysc-omap4", "ti,sysc";
 3628                         reg = <0x3e000 0x4>,
 3629                               <0x3e010 0x4>;
 3630                         reg-names = "rev", "sysc";
 3631                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 3632                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 3633                                         <SYSC_IDLE_NO>,
 3634                                         <SYSC_IDLE_SMART>;
 3635                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
 3636                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX4_CLKCTRL 0>;
 3637                         clock-names = "fck";
 3638                         #address-cells = <1>;
 3639                         #size-cells = <1>;
 3640                         ranges = <0x0 0x3e000 0x1000>;
 3641 
 3642                         mailbox4: mailbox@0 {
 3643                                 compatible = "ti,omap4-mailbox";
 3644                                 reg = <0x0 0x200>;
 3645                                 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 3646                                              <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 3647                                              <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 3648                                              <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
 3649                                 #mbox-cells = <1>;
 3650                                 ti,mbox-num-users = <4>;
 3651                                 ti,mbox-num-fifos = <12>;
 3652                                 status = "disabled";
 3653                         };
 3654                 };
 3655 
 3656                 target-module@40000 {                   /* 0x48840000, ap 39 64.0 */
 3657                         compatible = "ti,sysc-omap4", "ti,sysc";
 3658                         reg = <0x40000 0x4>,
 3659                               <0x40010 0x4>;
 3660                         reg-names = "rev", "sysc";
 3661                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 3662                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 3663                                         <SYSC_IDLE_NO>,
 3664                                         <SYSC_IDLE_SMART>;
 3665                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
 3666                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX5_CLKCTRL 0>;
 3667                         clock-names = "fck";
 3668                         #address-cells = <1>;
 3669                         #size-cells = <1>;
 3670                         ranges = <0x0 0x40000 0x1000>;
 3671 
 3672                         mailbox5: mailbox@0 {
 3673                                 compatible = "ti,omap4-mailbox";
 3674                                 reg = <0x0 0x200>;
 3675                                 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 3676                                              <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 3677                                              <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 3678                                              <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
 3679                                 #mbox-cells = <1>;
 3680                                 ti,mbox-num-users = <4>;
 3681                                 ti,mbox-num-fifos = <12>;
 3682                                 status = "disabled";
 3683                         };
 3684                 };
 3685 
 3686                 target-module@42000 {                   /* 0x48842000, ap 41 4e.0 */
 3687                         compatible = "ti,sysc-omap4", "ti,sysc";
 3688                         reg = <0x42000 0x4>,
 3689                               <0x42010 0x4>;
 3690                         reg-names = "rev", "sysc";
 3691                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 3692                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 3693                                         <SYSC_IDLE_NO>,
 3694                                         <SYSC_IDLE_SMART>;
 3695                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
 3696                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX6_CLKCTRL 0>;
 3697                         clock-names = "fck";
 3698                         #address-cells = <1>;
 3699                         #size-cells = <1>;
 3700                         ranges = <0x0 0x42000 0x1000>;
 3701 
 3702                         mailbox6: mailbox@0 {
 3703                                 compatible = "ti,omap4-mailbox";
 3704                                 reg = <0x0 0x200>;
 3705                                 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 3706                                              <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 3707                                              <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 3708                                              <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
 3709                                 #mbox-cells = <1>;
 3710                                 ti,mbox-num-users = <4>;
 3711                                 ti,mbox-num-fifos = <12>;
 3712                                 status = "disabled";
 3713                         };
 3714                 };
 3715 
 3716                 target-module@44000 {                   /* 0x48844000, ap 43 42.0 */
 3717                         compatible = "ti,sysc-omap4", "ti,sysc";
 3718                         reg = <0x44000 0x4>,
 3719                               <0x44010 0x4>;
 3720                         reg-names = "rev", "sysc";
 3721                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 3722                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 3723                                         <SYSC_IDLE_NO>,
 3724                                         <SYSC_IDLE_SMART>;
 3725                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
 3726                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX7_CLKCTRL 0>;
 3727                         clock-names = "fck";
 3728                         #address-cells = <1>;
 3729                         #size-cells = <1>;
 3730                         ranges = <0x0 0x44000 0x1000>;
 3731 
 3732                         mailbox7: mailbox@0 {
 3733                                 compatible = "ti,omap4-mailbox";
 3734                                 reg = <0x0 0x200>;
 3735                                 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
 3736                                              <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
 3737                                              <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
 3738                                              <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
 3739                                 #mbox-cells = <1>;
 3740                                 ti,mbox-num-users = <4>;
 3741                                 ti,mbox-num-fifos = <12>;
 3742                                 status = "disabled";
 3743                         };
 3744                 };
 3745 
 3746                 target-module@46000 {                   /* 0x48846000, ap 45 48.0 */
 3747                         compatible = "ti,sysc-omap4", "ti,sysc";
 3748                         reg = <0x46000 0x4>,
 3749                               <0x46010 0x4>;
 3750                         reg-names = "rev", "sysc";
 3751                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 3752                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 3753                                         <SYSC_IDLE_NO>,
 3754                                         <SYSC_IDLE_SMART>;
 3755                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
 3756                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX8_CLKCTRL 0>;
 3757                         clock-names = "fck";
 3758                         #address-cells = <1>;
 3759                         #size-cells = <1>;
 3760                         ranges = <0x0 0x46000 0x1000>;
 3761 
 3762                         mailbox8: mailbox@0 {
 3763                                 compatible = "ti,omap4-mailbox";
 3764                                 reg = <0x0 0x200>;
 3765                                 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 3766                                              <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
 3767                                              <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
 3768                                              <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
 3769                                 #mbox-cells = <1>;
 3770                                 ti,mbox-num-users = <4>;
 3771                                 ti,mbox-num-fifos = <12>;
 3772                                 status = "disabled";
 3773                         };
 3774                 };
 3775 
 3776                 target-module@48000 {                   /* 0x48848000, ap 47 36.0 */
 3777                         compatible = "ti,sysc";
 3778                         status = "disabled";
 3779                         #address-cells = <1>;
 3780                         #size-cells = <1>;
 3781                         ranges = <0x0 0x48000 0x1000>;
 3782                 };
 3783 
 3784                 target-module@4a000 {                   /* 0x4884a000, ap 49 38.0 */
 3785                         compatible = "ti,sysc";
 3786                         status = "disabled";
 3787                         #address-cells = <1>;
 3788                         #size-cells = <1>;
 3789                         ranges = <0x0 0x4a000 0x1000>;
 3790                 };
 3791 
 3792                 target-module@4c000 {                   /* 0x4884c000, ap 51 44.0 */
 3793                         compatible = "ti,sysc";
 3794                         status = "disabled";
 3795                         #address-cells = <1>;
 3796                         #size-cells = <1>;
 3797                         ranges = <0x0 0x4c000 0x1000>;
 3798                 };
 3799 
 3800                 target-module@4e000 {                   /* 0x4884e000, ap 53 4c.0 */
 3801                         compatible = "ti,sysc";
 3802                         status = "disabled";
 3803                         #address-cells = <1>;
 3804                         #size-cells = <1>;
 3805                         ranges = <0x0 0x4e000 0x1000>;
 3806                 };
 3807 
 3808                 target-module@50000 {                   /* 0x48850000, ap 55 40.0 */
 3809                         compatible = "ti,sysc";
 3810                         status = "disabled";
 3811                         #address-cells = <1>;
 3812                         #size-cells = <1>;
 3813                         ranges = <0x0 0x50000 0x1000>;
 3814                 };
 3815 
 3816                 target-module@52000 {                   /* 0x48852000, ap 57 54.0 */
 3817                         compatible = "ti,sysc";
 3818                         status = "disabled";
 3819                         #address-cells = <1>;
 3820                         #size-cells = <1>;
 3821                         ranges = <0x0 0x52000 0x1000>;
 3822                 };
 3823 
 3824                 target-module@54000 {                   /* 0x48854000, ap 59 1a.0 */
 3825                         compatible = "ti,sysc";
 3826                         status = "disabled";
 3827                         #address-cells = <1>;
 3828                         #size-cells = <1>;
 3829                         ranges = <0x0 0x54000 0x1000>;
 3830                 };
 3831 
 3832                 target-module@56000 {                   /* 0x48856000, ap 61 22.0 */
 3833                         compatible = "ti,sysc";
 3834                         status = "disabled";
 3835                         #address-cells = <1>;
 3836                         #size-cells = <1>;
 3837                         ranges = <0x0 0x56000 0x1000>;
 3838                 };
 3839 
 3840                 target-module@58000 {                   /* 0x48858000, ap 63 2a.0 */
 3841                         compatible = "ti,sysc";
 3842                         status = "disabled";
 3843                         #address-cells = <1>;
 3844                         #size-cells = <1>;
 3845                         ranges = <0x0 0x58000 0x1000>;
 3846                 };
 3847 
 3848                 target-module@5a000 {                   /* 0x4885a000, ap 65 5c.0 */
 3849                         compatible = "ti,sysc";
 3850                         status = "disabled";
 3851                         #address-cells = <1>;
 3852                         #size-cells = <1>;
 3853                         ranges = <0x0 0x5a000 0x1000>;
 3854                 };
 3855 
 3856                 target-module@5c000 {                   /* 0x4885c000, ap 31 32.0 */
 3857                         compatible = "ti,sysc";
 3858                         status = "disabled";
 3859                         #address-cells = <1>;
 3860                         #size-cells = <1>;
 3861                         ranges = <0x0 0x5c000 0x1000>;
 3862                 };
 3863 
 3864                 target-module@5e000 {                   /* 0x4885e000, ap 69 6c.0 */
 3865                         compatible = "ti,sysc-omap4", "ti,sysc";
 3866                         reg = <0x5e000 0x4>,
 3867                               <0x5e010 0x4>;
 3868                         reg-names = "rev", "sysc";
 3869                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 3870                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 3871                                         <SYSC_IDLE_NO>,
 3872                                         <SYSC_IDLE_SMART>;
 3873                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
 3874                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX9_CLKCTRL 0>;
 3875                         clock-names = "fck";
 3876                         #address-cells = <1>;
 3877                         #size-cells = <1>;
 3878                         ranges = <0x0 0x5e000 0x1000>;
 3879 
 3880                         mailbox9: mailbox@0 {
 3881                                 compatible = "ti,omap4-mailbox";
 3882                                 reg = <0x0 0x200>;
 3883                                 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
 3884                                              <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
 3885                                              <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
 3886                                              <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 3887                                 #mbox-cells = <1>;
 3888                                 ti,mbox-num-users = <4>;
 3889                                 ti,mbox-num-fifos = <12>;
 3890                                 status = "disabled";
 3891                         };
 3892                 };
 3893 
 3894                 target-module@60000 {                   /* 0x48860000, ap 71 4a.0 */
 3895                         compatible = "ti,sysc-omap4", "ti,sysc";
 3896                         reg = <0x60000 0x4>,
 3897                               <0x60010 0x4>;
 3898                         reg-names = "rev", "sysc";
 3899                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 3900                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 3901                                         <SYSC_IDLE_NO>,
 3902                                         <SYSC_IDLE_SMART>;
 3903                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
 3904                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX10_CLKCTRL 0>;
 3905                         clock-names = "fck";
 3906                         #address-cells = <1>;
 3907                         #size-cells = <1>;
 3908                         ranges = <0x0 0x60000 0x1000>;
 3909 
 3910                         mailbox10: mailbox@0 {
 3911                                 compatible = "ti,omap4-mailbox";
 3912                                 reg = <0x0 0x200>;
 3913                                 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
 3914                                              <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
 3915                                              <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
 3916                                              <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 3917                                 #mbox-cells = <1>;
 3918                                 ti,mbox-num-users = <4>;
 3919                                 ti,mbox-num-fifos = <12>;
 3920                                 status = "disabled";
 3921                         };
 3922                 };
 3923 
 3924                 target-module@62000 {                   /* 0x48862000, ap 73 74.0 */
 3925                         compatible = "ti,sysc-omap4", "ti,sysc";
 3926                         reg = <0x62000 0x4>,
 3927                               <0x62010 0x4>;
 3928                         reg-names = "rev", "sysc";
 3929                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 3930                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 3931                                         <SYSC_IDLE_NO>,
 3932                                         <SYSC_IDLE_SMART>;
 3933                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
 3934                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX11_CLKCTRL 0>;
 3935                         clock-names = "fck";
 3936                         #address-cells = <1>;
 3937                         #size-cells = <1>;
 3938                         ranges = <0x0 0x62000 0x1000>;
 3939 
 3940                         mailbox11: mailbox@0 {
 3941                                 compatible = "ti,omap4-mailbox";
 3942                                 reg = <0x0 0x200>;
 3943                                 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
 3944                                              <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
 3945                                              <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
 3946                                              <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
 3947                                 #mbox-cells = <1>;
 3948                                 ti,mbox-num-users = <4>;
 3949                                 ti,mbox-num-fifos = <12>;
 3950                                 status = "disabled";
 3951                         };
 3952                 };
 3953 
 3954                 target-module@64000 {                   /* 0x48864000, ap 67 52.0 */
 3955                         compatible = "ti,sysc-omap4", "ti,sysc";
 3956                         reg = <0x64000 0x4>,
 3957                               <0x64010 0x4>;
 3958                         reg-names = "rev", "sysc";
 3959                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 3960                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 3961                                         <SYSC_IDLE_NO>,
 3962                                         <SYSC_IDLE_SMART>;
 3963                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
 3964                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX12_CLKCTRL 0>;
 3965                         clock-names = "fck";
 3966                         #address-cells = <1>;
 3967                         #size-cells = <1>;
 3968                         ranges = <0x0 0x64000 0x1000>;
 3969 
 3970                         mailbox12: mailbox@0 {
 3971                                 compatible = "ti,omap4-mailbox";
 3972                                 reg = <0x0 0x200>;
 3973                                 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
 3974                                              <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
 3975                                              <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
 3976                                              <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
 3977                                 #mbox-cells = <1>;
 3978                                 ti,mbox-num-users = <4>;
 3979                                 ti,mbox-num-fifos = <12>;
 3980                                 status = "disabled";
 3981                         };
 3982                 };
 3983 
 3984                 target-module@80000 {                   /* 0x48880000, ap 83 0e.1 */
 3985                         compatible = "ti,sysc-omap4", "ti,sysc";
 3986                         reg = <0x80000 0x4>,
 3987                               <0x80010 0x4>;
 3988                         reg-names = "rev", "sysc";
 3989                         ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
 3990                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 3991                                         <SYSC_IDLE_NO>,
 3992                                         <SYSC_IDLE_SMART>,
 3993                                         <SYSC_IDLE_SMART_WKUP>;
 3994                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 3995                                         <SYSC_IDLE_NO>,
 3996                                         <SYSC_IDLE_SMART>,
 3997                                         <SYSC_IDLE_SMART_WKUP>;
 3998                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
 3999                         clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 0>;
 4000                         clock-names = "fck";
 4001                         #address-cells = <1>;
 4002                         #size-cells = <1>;
 4003                         ranges = <0x0 0x80000 0x20000>;
 4004 
 4005                         omap_dwc3_1: omap_dwc3_1@0 {
 4006                                 compatible = "ti,dwc3";
 4007                                 reg = <0x0 0x10000>;
 4008                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 4009                                 #address-cells = <1>;
 4010                                 #size-cells = <1>;
 4011                                 utmi-mode = <2>;
 4012                                 ranges = <0 0 0x20000>;
 4013 
 4014                                 usb1: usb@10000 {
 4015                                         compatible = "snps,dwc3";
 4016                                         reg = <0x10000 0x17000>;
 4017                                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
 4018                                                      <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
 4019                                                      <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 4020                                         interrupt-names = "peripheral",
 4021                                                           "host",
 4022                                                           "otg";
 4023                                         phys = <&usb2_phy1>, <&usb3_phy1>;
 4024                                         phy-names = "usb2-phy", "usb3-phy";
 4025                                         maximum-speed = "super-speed";
 4026                                         dr_mode = "otg";
 4027                                         snps,dis_u3_susphy_quirk;
 4028                                         snps,dis_u2_susphy_quirk;
 4029                                 };
 4030                         };
 4031                 };
 4032 
 4033                 target-module@c0000 {                   /* 0x488c0000, ap 79 06.0 */
 4034                         compatible = "ti,sysc-omap4", "ti,sysc";
 4035                         reg = <0xc0000 0x4>,
 4036                               <0xc0010 0x4>;
 4037                         reg-names = "rev", "sysc";
 4038                         ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
 4039                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 4040                                         <SYSC_IDLE_NO>,
 4041                                         <SYSC_IDLE_SMART>,
 4042                                         <SYSC_IDLE_SMART_WKUP>;
 4043                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 4044                                         <SYSC_IDLE_NO>,
 4045                                         <SYSC_IDLE_SMART>,
 4046                                         <SYSC_IDLE_SMART_WKUP>;
 4047                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
 4048                         clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 0>;
 4049                         clock-names = "fck";
 4050                         #address-cells = <1>;
 4051                         #size-cells = <1>;
 4052                         ranges = <0x0 0xc0000 0x20000>;
 4053 
 4054                         omap_dwc3_2: omap_dwc3_2@0 {
 4055                                 compatible = "ti,dwc3";
 4056                                 reg = <0x0 0x10000>;
 4057                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 4058                                 #address-cells = <1>;
 4059                                 #size-cells = <1>;
 4060                                 utmi-mode = <2>;
 4061                                 ranges = <0 0 0x20000>;
 4062 
 4063                                 usb2: usb@10000 {
 4064                                         compatible = "snps,dwc3";
 4065                                         reg = <0x10000 0x17000>;
 4066                                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
 4067                                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
 4068                                                      <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 4069                                         interrupt-names = "peripheral",
 4070                                                           "host",
 4071                                                           "otg";
 4072                                         phys = <&usb2_phy2>;
 4073                                         phy-names = "usb2-phy";
 4074                                         maximum-speed = "high-speed";
 4075                                         dr_mode = "otg";
 4076                                         snps,dis_u3_susphy_quirk;
 4077                                         snps,dis_u2_susphy_quirk;
 4078                                         snps,dis_metastability_quirk;
 4079                                 };
 4080                         };
 4081                 };
 4082 
 4083                 usb3_tm: target-module@100000 {         /* 0x48900000, ap 85 04.0 */
 4084                         compatible = "ti,sysc-omap4", "ti,sysc";
 4085                         reg = <0x100000 0x4>,
 4086                               <0x100010 0x4>;
 4087                         reg-names = "rev", "sysc";
 4088                         ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
 4089                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 4090                                         <SYSC_IDLE_NO>,
 4091                                         <SYSC_IDLE_SMART>,
 4092                                         <SYSC_IDLE_SMART_WKUP>;
 4093                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 4094                                         <SYSC_IDLE_NO>,
 4095                                         <SYSC_IDLE_SMART>,
 4096                                         <SYSC_IDLE_SMART_WKUP>;
 4097                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
 4098                         clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS3_CLKCTRL 0>;
 4099                         clock-names = "fck";
 4100                         #address-cells = <1>;
 4101                         #size-cells = <1>;
 4102                         ranges = <0x0 0x100000 0x20000>;
 4103 
 4104                         omap_dwc3_3: omap_dwc3_3@0 {
 4105                                 compatible = "ti,dwc3";
 4106                                 reg = <0x0 0x10000>;
 4107                                 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
 4108                                 #address-cells = <1>;
 4109                                 #size-cells = <1>;
 4110                                 utmi-mode = <2>;
 4111                                 ranges = <0 0 0x20000>;
 4112                                 status = "disabled";
 4113 
 4114                                 usb3: usb@10000 {
 4115                                         compatible = "snps,dwc3";
 4116                                         reg = <0x10000 0x17000>;
 4117                                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 4118                                                      <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 4119                                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
 4120                                         interrupt-names = "peripheral",
 4121                                                           "host",
 4122                                                           "otg";
 4123                                         maximum-speed = "high-speed";
 4124                                         dr_mode = "otg";
 4125                                         snps,dis_u3_susphy_quirk;
 4126                                         snps,dis_u2_susphy_quirk;
 4127                                 };
 4128                         };
 4129                 };
 4130 
 4131                 target-module@170000 {                  /* 0x48970000, ap 21 0a.0 */
 4132                         compatible = "ti,sysc-omap4", "ti,sysc";
 4133                         reg = <0x170010 0x4>;
 4134                         reg-names = "sysc";
 4135                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 4136                                         <SYSC_IDLE_NO>,
 4137                                         <SYSC_IDLE_SMART>;
 4138                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 4139                                         <SYSC_IDLE_NO>,
 4140                                         <SYSC_IDLE_SMART>;
 4141                         clocks = <&cam_clkctrl DRA7_CAM_VIP1_CLKCTRL 0>;
 4142                         clock-names = "fck";
 4143                         #address-cells = <1>;
 4144                         #size-cells = <1>;
 4145                         ranges = <0x0 0x170000 0x10000>;
 4146                         status = "disabled";
 4147                 };
 4148 
 4149                 target-module@190000 {                  /* 0x48990000, ap 23 2e.0 */
 4150                         compatible = "ti,sysc-omap4", "ti,sysc";
 4151                         reg = <0x190010 0x4>;
 4152                         reg-names = "sysc";
 4153                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 4154                                         <SYSC_IDLE_NO>,
 4155                                         <SYSC_IDLE_SMART>;
 4156                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 4157                                         <SYSC_IDLE_NO>,
 4158                                         <SYSC_IDLE_SMART>;
 4159                         clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
 4160                         clock-names = "fck";
 4161                         #address-cells = <1>;
 4162                         #size-cells = <1>;
 4163                         ranges = <0x0 0x190000 0x10000>;
 4164                         status = "disabled";
 4165                 };
 4166 
 4167                 target-module@1b0000 {                  /* 0x489b0000, ap 25 34.0 */
 4168                         compatible = "ti,sysc-omap4", "ti,sysc";
 4169                         reg = <0x1b0000 0x4>,
 4170                               <0x1b0010 0x4>;
 4171                         reg-names = "rev", "sysc";
 4172                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 4173                                         <SYSC_IDLE_NO>,
 4174                                         <SYSC_IDLE_SMART>;
 4175                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 4176                                         <SYSC_IDLE_NO>,
 4177                                         <SYSC_IDLE_SMART>;
 4178                         clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>;
 4179                         clock-names = "fck";
 4180                         #address-cells = <1>;
 4181                         #size-cells = <1>;
 4182                         ranges = <0x0 0x1b0000 0x10000>;
 4183                         status = "disabled";
 4184                 };
 4185 
 4186                 target-module@1d0010 {                  /* 0x489d0000, ap 27 30.0 */
 4187                         compatible = "ti,sysc-omap4", "ti,sysc";
 4188                         reg = <0x1d0010 0x4>;
 4189                         reg-names = "sysc";
 4190                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 4191                                         <SYSC_IDLE_NO>;
 4192                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 4193                                         <SYSC_IDLE_NO>,
 4194                                         <SYSC_IDLE_SMART>;
 4195                         power-domains = <&prm_vpe>;
 4196                         clocks = <&vpe_clkctrl DRA7_VPE_VPE_CLKCTRL 0>;
 4197                         clock-names = "fck";
 4198                         #address-cells = <1>;
 4199                         #size-cells = <1>;
 4200                         ranges = <0x0 0x1d0000 0x10000>;
 4201 
 4202                         vpe: vpe@0 {
 4203                                 compatible = "ti,dra7-vpe";
 4204                                 reg = <0x0000 0x120>,
 4205                                       <0x0700 0x80>,
 4206                                       <0x5700 0x18>,
 4207                                       <0xd000 0x400>;
 4208                                 reg-names = "vpe_top",
 4209                                             "sc",
 4210                                             "csc",
 4211                                             "vpdma";
 4212                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
 4213                         };
 4214                 };
 4215         };
 4216 };
 4217 
 4218 &l4_wkup {                                              /* 0x4ae00000 */
 4219         compatible = "ti,dra7-l4-wkup", "simple-pm-bus";
 4220         power-domains = <&prm_wkupaon>;
 4221         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_L4_WKUP_CLKCTRL 0>;
 4222         clock-names = "fck";
 4223         reg = <0x4ae00000 0x800>,
 4224               <0x4ae00800 0x800>,
 4225               <0x4ae01000 0x1000>;
 4226         reg-names = "ap", "la", "ia0";
 4227         #address-cells = <1>;
 4228         #size-cells = <1>;
 4229         ranges = <0x00000000 0x4ae00000 0x010000>,      /* segment 0 */
 4230                  <0x00010000 0x4ae10000 0x010000>,      /* segment 1 */
 4231                  <0x00020000 0x4ae20000 0x010000>,      /* segment 2 */
 4232                  <0x00030000 0x4ae30000 0x010000>;      /* segment 3 */
 4233 
 4234         segment@0 {                                     /* 0x4ae00000 */
 4235                 compatible = "simple-pm-bus";
 4236                 #address-cells = <1>;
 4237                 #size-cells = <1>;
 4238                 ranges = <0x00000000 0x00000000 0x000800>,      /* ap 0 */
 4239                          <0x00001000 0x00001000 0x001000>,      /* ap 1 */
 4240                          <0x00000800 0x00000800 0x000800>,      /* ap 2 */
 4241                          <0x00006000 0x00006000 0x002000>,      /* ap 3 */
 4242                          <0x00008000 0x00008000 0x001000>,      /* ap 4 */
 4243                          <0x00004000 0x00004000 0x001000>,      /* ap 15 */
 4244                          <0x00005000 0x00005000 0x001000>,      /* ap 16 */
 4245                          <0x0000c000 0x0000c000 0x001000>,      /* ap 17 */
 4246                          <0x0000d000 0x0000d000 0x001000>;      /* ap 18 */
 4247 
 4248                 target-module@4000 {                    /* 0x4ae04000, ap 15 40.0 */
 4249                         compatible = "ti,sysc-omap2", "ti,sysc";
 4250                         reg = <0x4000 0x4>,
 4251                               <0x4010 0x4>;
 4252                         reg-names = "rev", "sysc";
 4253                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 4254                                         <SYSC_IDLE_NO>,
 4255                                         <SYSC_IDLE_SMART>,
 4256                                         <SYSC_IDLE_SMART_WKUP>;
 4257                         /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
 4258                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_COUNTER_32K_CLKCTRL 0>;
 4259                         clock-names = "fck";
 4260                         #address-cells = <1>;
 4261                         #size-cells = <1>;
 4262                         ranges = <0x0 0x4000 0x1000>;
 4263 
 4264                         counter32k: counter@0 {
 4265                                 compatible = "ti,omap-counter32k";
 4266                                 reg = <0x0 0x40>;
 4267                         };
 4268                 };
 4269 
 4270                 target-module@6000 {                    /* 0x4ae06000, ap 3 10.0 */
 4271                         compatible = "ti,sysc-omap4", "ti,sysc";
 4272                         reg = <0x6000 0x4>;
 4273                         reg-names = "rev";
 4274                         #address-cells = <1>;
 4275                         #size-cells = <1>;
 4276                         ranges = <0x0 0x6000 0x2000>;
 4277 
 4278                         prm: prm@0 {
 4279                                 compatible = "ti,dra7-prm", "simple-bus";
 4280                                 reg = <0 0x3000>;
 4281                                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 4282                                 #address-cells = <1>;
 4283                                 #size-cells = <1>;
 4284                                 ranges = <0 0 0x3000>;
 4285 
 4286                                 prm_clocks: clocks {
 4287                                         #address-cells = <1>;
 4288                                         #size-cells = <0>;
 4289                                 };
 4290 
 4291                                 prm_clockdomains: clockdomains {
 4292                                 };
 4293                         };
 4294                 };
 4295 
 4296                 target-module@c000 {                    /* 0x4ae0c000, ap 17 50.0 */
 4297                         compatible = "ti,sysc-omap4", "ti,sysc";
 4298                         reg = <0xc000 0x4>;
 4299                         reg-names = "rev";
 4300                         #address-cells = <1>;
 4301                         #size-cells = <1>;
 4302                         ranges = <0x0 0xc000 0x1000>;
 4303 
 4304                         scm_wkup: scm_conf@0 {
 4305                                 compatible = "syscon";
 4306                                 reg = <0 0x1000>;
 4307                         };
 4308                 };
 4309         };
 4310 
 4311         segment@10000 {                                 /* 0x4ae10000 */
 4312                 compatible = "simple-pm-bus";
 4313                 #address-cells = <1>;
 4314                 #size-cells = <1>;
 4315                 ranges = <0x00000000 0x00010000 0x001000>,      /* ap 5 */
 4316                          <0x00001000 0x00011000 0x001000>,      /* ap 6 */
 4317                          <0x00004000 0x00014000 0x001000>,      /* ap 7 */
 4318                          <0x00005000 0x00015000 0x001000>,      /* ap 8 */
 4319                          <0x00008000 0x00018000 0x001000>,      /* ap 9 */
 4320                          <0x00009000 0x00019000 0x001000>,      /* ap 10 */
 4321                          <0x0000c000 0x0001c000 0x001000>,      /* ap 11 */
 4322                          <0x0000d000 0x0001d000 0x001000>;      /* ap 12 */
 4323 
 4324                 target-module@0 {                       /* 0x4ae10000, ap 5 20.0 */
 4325                         compatible = "ti,sysc-omap2", "ti,sysc";
 4326                         reg = <0x0 0x4>,
 4327                               <0x10 0x4>,
 4328                               <0x114 0x4>;
 4329                         reg-names = "rev", "sysc", "syss";
 4330                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
 4331                                          SYSC_OMAP2_SOFTRESET |
 4332                                          SYSC_OMAP2_AUTOIDLE)>;
 4333                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 4334                                         <SYSC_IDLE_NO>,
 4335                                         <SYSC_IDLE_SMART>,
 4336                                         <SYSC_IDLE_SMART_WKUP>;
 4337                         ti,syss-mask = <1>;
 4338                         /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
 4339                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 0>,
 4340                                  <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 8>;
 4341                         clock-names = "fck", "dbclk";
 4342                         #address-cells = <1>;
 4343                         #size-cells = <1>;
 4344                         ranges = <0x0 0x0 0x1000>;
 4345 
 4346                         gpio1: gpio@0 {
 4347                                 compatible = "ti,omap4-gpio";
 4348                                 reg = <0x0 0x200>;
 4349                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 4350                                 gpio-controller;
 4351                                 #gpio-cells = <2>;
 4352                                 interrupt-controller;
 4353                                 #interrupt-cells = <2>;
 4354                         };
 4355                 };
 4356 
 4357                 target-module@4000 {                    /* 0x4ae14000, ap 7 28.0 */
 4358                         compatible = "ti,sysc-omap2", "ti,sysc";
 4359                         reg = <0x4000 0x4>,
 4360                               <0x4010 0x4>,
 4361                               <0x4014 0x4>;
 4362                         reg-names = "rev", "sysc", "syss";
 4363                         ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
 4364                                          SYSC_OMAP2_SOFTRESET)>;
 4365                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 4366                                         <SYSC_IDLE_NO>,
 4367                                         <SYSC_IDLE_SMART>,
 4368                                         <SYSC_IDLE_SMART_WKUP>;
 4369                         ti,syss-mask = <1>;
 4370                         /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
 4371                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_WD_TIMER2_CLKCTRL 0>;
 4372                         clock-names = "fck";
 4373                         #address-cells = <1>;
 4374                         #size-cells = <1>;
 4375                         ranges = <0x0 0x4000 0x1000>;
 4376 
 4377                         wdt2: wdt@0 {
 4378                                 compatible = "ti,omap3-wdt";
 4379                                 reg = <0x0 0x80>;
 4380                                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 4381                         };
 4382                 };
 4383 
 4384                 timer1_target: target-module@8000 {     /* 0x4ae18000, ap 9 30.0 */
 4385                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 4386                         reg = <0x8000 0x4>,
 4387                               <0x8010 0x4>;
 4388                         reg-names = "rev", "sysc";
 4389                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 4390                                          SYSC_OMAP4_SOFTRESET)>;
 4391                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 4392                                         <SYSC_IDLE_NO>,
 4393                                         <SYSC_IDLE_SMART>,
 4394                                         <SYSC_IDLE_SMART_WKUP>;
 4395                         /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
 4396                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 0>;
 4397                         clock-names = "fck";
 4398                         #address-cells = <1>;
 4399                         #size-cells = <1>;
 4400                         ranges = <0x0 0x8000 0x1000>;
 4401 
 4402                         timer1: timer@0 {
 4403                                 compatible = "ti,omap5430-timer";
 4404                                 reg = <0x0 0x80>;
 4405                                 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>;
 4406                                 clock-names = "fck";
 4407                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 4408                                 ti,timer-alwon;
 4409                         };
 4410                 };
 4411 
 4412                 target-module@c000 {                    /* 0x4ae1c000, ap 11 38.0 */
 4413                         compatible = "ti,sysc";
 4414                         status = "disabled";
 4415                         #address-cells = <1>;
 4416                         #size-cells = <1>;
 4417                         ranges = <0x0 0xc000 0x1000>;
 4418                 };
 4419         };
 4420 
 4421         segment@20000 {                                 /* 0x4ae20000 */
 4422                 compatible = "simple-pm-bus";
 4423                 #address-cells = <1>;
 4424                 #size-cells = <1>;
 4425                 ranges = <0x00006000 0x00026000 0x001000>,      /* ap 13 */
 4426                          <0x0000a000 0x0002a000 0x001000>,      /* ap 14 */
 4427                          <0x00000000 0x00020000 0x001000>,      /* ap 19 */
 4428                          <0x00001000 0x00021000 0x001000>,      /* ap 20 */
 4429                          <0x00002000 0x00022000 0x001000>,      /* ap 21 */
 4430                          <0x00003000 0x00023000 0x001000>,      /* ap 22 */
 4431                          <0x00007000 0x00027000 0x000400>,      /* ap 23 */
 4432                          <0x00008000 0x00028000 0x000800>,      /* ap 24 */
 4433                          <0x00009000 0x00029000 0x000100>,      /* ap 25 */
 4434                          <0x00008800 0x00028800 0x000200>,      /* ap 26 */
 4435                          <0x00008a00 0x00028a00 0x000100>,      /* ap 27 */
 4436                          <0x0000b000 0x0002b000 0x001000>,      /* ap 28 */
 4437                          <0x0000c000 0x0002c000 0x001000>,      /* ap 29 */
 4438                          <0x0000f000 0x0002f000 0x001000>;      /* ap 32 */
 4439 
 4440                 target-module@0 {                       /* 0x4ae20000, ap 19 08.0 */
 4441                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
 4442                         reg = <0x0 0x4>,
 4443                               <0x10 0x4>;
 4444                         reg-names = "rev", "sysc";
 4445                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
 4446                                          SYSC_OMAP4_SOFTRESET)>;
 4447                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 4448                                         <SYSC_IDLE_NO>,
 4449                                         <SYSC_IDLE_SMART>,
 4450                                         <SYSC_IDLE_SMART_WKUP>;
 4451                         /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
 4452                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER12_CLKCTRL 0>;
 4453                         clock-names = "fck";
 4454                         #address-cells = <1>;
 4455                         #size-cells = <1>;
 4456                         ranges = <0x0 0x0 0x1000>;
 4457 
 4458                         timer12: timer@0 {
 4459                                 compatible = "ti,omap5430-timer";
 4460                                 reg = <0x0 0x80>;
 4461                                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 4462                                 ti,timer-alwon;
 4463                                 ti,timer-secure;
 4464                         };
 4465                 };
 4466 
 4467                 target-module@2000 {                    /* 0x4ae22000, ap 21 18.0 */
 4468                         compatible = "ti,sysc";
 4469                         status = "disabled";
 4470                         #address-cells = <1>;
 4471                         #size-cells = <1>;
 4472                         ranges = <0x0 0x2000 0x1000>;
 4473                 };
 4474 
 4475                 target-module@6000 {                    /* 0x4ae26000, ap 13 48.0 */
 4476                         compatible = "ti,sysc";
 4477                         status = "disabled";
 4478                         #address-cells = <1>;
 4479                         #size-cells = <1>;
 4480                         ranges = <0x00000000 0x00006000 0x00001000>,
 4481                                  <0x00001000 0x00007000 0x00000400>,
 4482                                  <0x00002000 0x00008000 0x00000800>,
 4483                                  <0x00002800 0x00008800 0x00000200>,
 4484                                  <0x00002a00 0x00008a00 0x00000100>,
 4485                                  <0x00003000 0x00009000 0x00000100>;
 4486                 };
 4487 
 4488                 target-module@b000 {                    /* 0x4ae2b000, ap 28 02.0 */
 4489                         compatible = "ti,sysc-omap2", "ti,sysc";
 4490                         reg = <0xb050 0x4>,
 4491                               <0xb054 0x4>,
 4492                               <0xb058 0x4>;
 4493                         reg-names = "rev", "sysc", "syss";
 4494                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
 4495                                          SYSC_OMAP2_SOFTRESET |
 4496                                          SYSC_OMAP2_AUTOIDLE)>;
 4497                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 4498                                         <SYSC_IDLE_NO>,
 4499                                         <SYSC_IDLE_SMART>,
 4500                                         <SYSC_IDLE_SMART_WKUP>;
 4501                         ti,syss-mask = <1>;
 4502                         /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
 4503                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_UART10_CLKCTRL 0>;
 4504                         clock-names = "fck";
 4505                         #address-cells = <1>;
 4506                         #size-cells = <1>;
 4507                         ranges = <0x0 0xb000 0x1000>;
 4508 
 4509                         uart10: serial@0 {
 4510                                 compatible = "ti,dra742-uart";
 4511                                 reg = <0x0 0x100>;
 4512                                 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 4513                                 clock-frequency = <48000000>;
 4514                                 status = "disabled";
 4515                         };
 4516                 };
 4517 
 4518                 target-module@f000 {                    /* 0x4ae2f000, ap 32 58.0 */
 4519                         compatible = "ti,sysc";
 4520                         status = "disabled";
 4521                         #address-cells = <1>;
 4522                         #size-cells = <1>;
 4523                         ranges = <0x0 0xf000 0x1000>;
 4524                 };
 4525         };
 4526 
 4527         segment@30000 {                                 /* 0x4ae30000 */
 4528                 compatible = "simple-pm-bus";
 4529                 #address-cells = <1>;
 4530                 #size-cells = <1>;
 4531                 ranges = <0x0000c000 0x0003c000 0x002000>,      /* ap 30 */
 4532                          <0x0000e000 0x0003e000 0x001000>,      /* ap 31 */
 4533                          <0x00000000 0x00030000 0x001000>,      /* ap 33 */
 4534                          <0x00001000 0x00031000 0x001000>,      /* ap 34 */
 4535                          <0x00002000 0x00032000 0x001000>,      /* ap 35 */
 4536                          <0x00003000 0x00033000 0x001000>,      /* ap 36 */
 4537                          <0x00004000 0x00034000 0x001000>,      /* ap 37 */
 4538                          <0x00005000 0x00035000 0x001000>,      /* ap 38 */
 4539                          <0x00006000 0x00036000 0x001000>,      /* ap 39 */
 4540                          <0x00007000 0x00037000 0x001000>,      /* ap 40 */
 4541                          <0x00008000 0x00038000 0x001000>,      /* ap 41 */
 4542                          <0x00009000 0x00039000 0x001000>,      /* ap 42 */
 4543                          <0x0000a000 0x0003a000 0x001000>;      /* ap 43 */
 4544 
 4545                 target-module@1000 {                    /* 0x4ae31000, ap 34 60.0 */
 4546                         compatible = "ti,sysc";
 4547                         status = "disabled";
 4548                         #address-cells = <1>;
 4549                         #size-cells = <1>;
 4550                         ranges = <0x0 0x1000 0x1000>;
 4551                 };
 4552 
 4553                 target-module@3000 {                    /* 0x4ae33000, ap 36 0a.0 */
 4554                         compatible = "ti,sysc";
 4555                         status = "disabled";
 4556                         #address-cells = <1>;
 4557                         #size-cells = <1>;
 4558                         ranges = <0x0 0x3000 0x1000>;
 4559                 };
 4560 
 4561                 target-module@5000 {                    /* 0x4ae35000, ap 38 0c.0 */
 4562                         compatible = "ti,sysc";
 4563                         status = "disabled";
 4564                         #address-cells = <1>;
 4565                         #size-cells = <1>;
 4566                         ranges = <0x0 0x5000 0x1000>;
 4567                 };
 4568 
 4569                 target-module@7000 {                    /* 0x4ae37000, ap 40 68.0 */
 4570                         compatible = "ti,sysc";
 4571                         status = "disabled";
 4572                         #address-cells = <1>;
 4573                         #size-cells = <1>;
 4574                         ranges = <0x0 0x7000 0x1000>;
 4575                 };
 4576 
 4577                 target-module@9000 {                    /* 0x4ae39000, ap 42 70.0 */
 4578                         compatible = "ti,sysc";
 4579                         status = "disabled";
 4580                         #address-cells = <1>;
 4581                         #size-cells = <1>;
 4582                         ranges = <0x0 0x9000 0x1000>;
 4583                 };
 4584 
 4585                 target-module@c000 {                    /* 0x4ae3c000, ap 30 04.0 */
 4586                         compatible = "ti,sysc-omap4", "ti,sysc";
 4587                         reg = <0xc020 0x4>;
 4588                         reg-names = "rev";
 4589                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 0>;
 4590                         clock-names = "fck";
 4591                         #address-cells = <1>;
 4592                         #size-cells = <1>;
 4593                         ranges = <0x0 0xc000 0x2000>;
 4594 
 4595                         dcan1: can@0 {
 4596                                 compatible = "ti,dra7-d_can";
 4597                                 reg = <0x0 0x2000>;
 4598                                 syscon-raminit = <&scm_conf 0x558 0>;
 4599                                 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
 4600                                 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 24>;
 4601                                 status = "disabled";
 4602                         };
 4603                 };
 4604         };
 4605 };
 4606
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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm/dra7-l4.dtsi

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/dra7-l4.dtsi
