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1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * MMC IOdelay values for TI's DRA72x, DRA71x and AM571x SoCs. 4 * 5 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8 /* 9 * Rules for modifying this file: 10 * a) Update of this file should typically correspond to a datamanual revision. 11 * Datamanual revision that was used should be updated in comment below. 12 * If there is no update to datamanual, do not update the values. If you 13 * need to use values different from that recommended by the datamanual 14 * for your design, then you should consider adding values to the device- 15 * -tree file for your board directly. 16 * b) We keep the mode names as close to the datamanual as possible. So 17 * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v, 18 * we follow that in code too. 19 * c) If the values change between multiple revisions of silicon, we add 20 * a revision tag to both the new and old entry. Use 'rev10' for PG 1.0, 21 * 'rev20' for PG 2.0 and so on. 22 * d) The node name and node label should be the exact same string. This is 23 * to curb naming creativity and achieve consistency. 24 * e) If in future, DRA71x and DRA72x values differ, then add 'dra71_' and 25 * 'dra72_' tag to entries. Both the new and old entries should gain a tag. 26 * 27 * Datamanual Revisions: 28 * 29 * AM571x Silicon Revision 2.0: SPRS957D, Revised January 2017 30 * AM571x Silicon Revision 1.0: SPRS919M, Revised November 2017 31 * DRA71x : SPRS960B, Revised February 2017 32 */ 33 34 &dra7_pmx_core { 35 mmc1_pins_default: mmc1_pins_default { 36 pinctrl-single,pins = < 37 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 38 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 39 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 40 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 41 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 42 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ 43 >; 44 }; 45 46 mmc1_pins_sdr12: mmc1_pins_sdr12 { 47 pinctrl-single,pins = < 48 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 49 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 50 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 51 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 52 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 53 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ 54 >; 55 }; 56 57 mmc1_pins_hs: mmc1_pins_hs { 58 pinctrl-single,pins = < 59 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 60 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 61 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 62 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 63 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 64 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ 65 >; 66 }; 67 68 mmc1_pins_sdr25: mmc1_pins_sdr25 { 69 pinctrl-single,pins = < 70 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 71 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 72 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 73 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 74 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 75 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ 76 >; 77 }; 78 79 mmc1_pins_sdr50: mmc1_pins_sdr50 { 80 pinctrl-single,pins = < 81 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_clk.clk */ 82 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_cmd.cmd */ 83 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat0.dat0 */ 84 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat1.dat1 */ 85 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat2.dat2 */ 86 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat3.dat3 */ 87 >; 88 }; 89 90 mmc1_pins_ddr50_rev10: mmc1_pins_ddr50_rev10 { 91 pinctrl-single,pins = < 92 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_clk.mmc1_clk */ 93 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ 94 DRA7XX_CORE_IOPAD(0x375C, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ 95 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ 96 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ 97 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ 98 >; 99 }; 100 101 mmc1_pins_ddr50_rev20: mmc1_pins_ddr50_rev20 { 102 pinctrl-single,pins = < 103 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ 104 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ 105 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ 106 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ 107 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ 108 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ 109 >; 110 }; 111 112 mmc1_pins_sdr104: mmc1_pins_sdr104 { 113 pinctrl-single,pins = < 114 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */ 115 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */ 116 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */ 117 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */ 118 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */ 119 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */ 120 >; 121 }; 122 123 mmc2_pins_default: mmc2_pins_default { 124 pinctrl-single,pins = < 125 DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ 126 DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ 127 DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ 128 DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ 129 DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ 130 DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ 131 DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ 132 DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ 133 DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ 134 DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ 135 >; 136 }; 137 138 mmc2_pins_hs: mmc2_pins_hs { 139 pinctrl-single,pins = < 140 DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ 141 DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ 142 DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ 143 DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ 144 DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ 145 DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ 146 DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ 147 DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ 148 DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ 149 DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ 150 >; 151 }; 152 153 mmc2_pins_ddr_rev10: mmc2_pins_ddr_rev10 { 154 pinctrl-single,pins = < 155 DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ 156 DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ 157 DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ 158 DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ 159 DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ 160 DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ 161 DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ 162 DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ 163 DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ 164 DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ 165 >; 166 }; 167 168 mmc2_pins_ddr_rev20: mmc2_pins_ddr_rev20 { 169 pinctrl-single,pins = < 170 DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ 171 DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ 172 DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ 173 DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ 174 DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ 175 DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ 176 DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ 177 DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ 178 DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ 179 DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ 180 >; 181 }; 182 183 mmc2_pins_hs200: mmc2_pins_hs200 { 184 pinctrl-single,pins = < 185 DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */ 186 DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ 187 DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ 188 DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ 189 DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ 190 DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ 191 DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ 192 DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ 193 DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ 194 DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ 195 >; 196 }; 197 198 mmc4_pins_default: mmc4_pins_default { 199 pinctrl-single,pins = < 200 DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ 201 DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ 202 DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ 203 DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ 204 DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ 205 DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ 206 >; 207 }; 208 }; 209 210 &dra7_iodelay_core { 211 212 /* Corresponds to MMC1_MANUAL1 in datamanual */ 213 mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf { 214 pinctrl-pin-array = < 215 0x618 A_DELAY_PS(588) G_DELAY_PS(0) /* CFG_MMC1_CLK_IN */ 216 0x624 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */ 217 0x630 A_DELAY_PS(1375) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */ 218 0x63C A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */ 219 0x648 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */ 220 0x654 A_DELAY_PS(1000) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */ 221 0x620 A_DELAY_PS(1230) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */ 222 0x62C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ 223 0x638 A_DELAY_PS(56) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ 224 0x644 A_DELAY_PS(76) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ 225 0x650 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ 226 0x65C A_DELAY_PS(99) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ 227 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ 228 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ 229 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ 230 0x64C A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ 231 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ 232 >; 233 }; 234 235 /* Corresponds to MMC1_MANUAL2 in datamanual */ 236 mmc1_iodelay_sdr104_rev10_conf: mmc1_iodelay_sdr104_rev10_conf { 237 pinctrl-pin-array = < 238 0x620 A_DELAY_PS(560) G_DELAY_PS(365) /* CFG_MMC1_CLK_OUT */ 239 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ 240 0x638 A_DELAY_PS(29) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ 241 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ 242 0x650 A_DELAY_PS(47) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ 243 0x65c A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ 244 0x628 A_DELAY_PS(125) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ 245 0x634 A_DELAY_PS(43) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ 246 0x640 A_DELAY_PS(433) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ 247 0x64c A_DELAY_PS(287) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ 248 0x658 A_DELAY_PS(351) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ 249 >; 250 }; 251 252 /* Corresponds to MMC1_MANUAL2 in datamanual */ 253 mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf { 254 pinctrl-pin-array = < 255 0x620 A_DELAY_PS(520) G_DELAY_PS(320) /* CFG_MMC1_CLK_OUT */ 256 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */ 257 0x638 A_DELAY_PS(40) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */ 258 0x644 A_DELAY_PS(83) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */ 259 0x650 A_DELAY_PS(98) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */ 260 0x65c A_DELAY_PS(106) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */ 261 0x628 A_DELAY_PS(51) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */ 262 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */ 263 0x640 A_DELAY_PS(363) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */ 264 0x64c A_DELAY_PS(199) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */ 265 0x658 A_DELAY_PS(273) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */ 266 >; 267 }; 268 269 /* Corresponds to MMC2_MANUAL1 in datamanual */ 270 mmc2_iodelay_ddr_conf: mmc2_iodelay_ddr_conf { 271 pinctrl-pin-array = < 272 0x18c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_IN */ 273 0x1a4 A_DELAY_PS(119) G_DELAY_PS(0) /* CFG_GPMC_A20_IN */ 274 0x1b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_IN */ 275 0x1bc A_DELAY_PS(18) G_DELAY_PS(0) /* CFG_GPMC_A22_IN */ 276 0x1c8 A_DELAY_PS(894) G_DELAY_PS(0) /* CFG_GPMC_A23_IN */ 277 0x1d4 A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_GPMC_A24_IN */ 278 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ 279 0x1ec A_DELAY_PS(23) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */ 280 0x1f8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_IN */ 281 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ 282 0x194 A_DELAY_PS(152) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ 283 0x1ac A_DELAY_PS(206) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ 284 0x1b8 A_DELAY_PS(78) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ 285 0x1c4 A_DELAY_PS(2) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ 286 0x1d0 A_DELAY_PS(266) G_DELAY_PS(0) /* CFG_GPMC_A23_OUT */ 287 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ 288 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ 289 0x1f4 A_DELAY_PS(43) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ 290 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ 291 0x368 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ 292 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ 293 0x1a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ 294 0x1b4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ 295 0x1c0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ 296 0x1d8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ 297 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ 298 0x1f0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ 299 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ 300 0x364 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ 301 >; 302 }; 303 304 /* Corresponds to MMC2_MANUAL3 in datamanual */ 305 mmc2_iodelay_hs200_rev10_conf: mmc2_iodelay_hs200_rev10_conf { 306 pinctrl-pin-array = < 307 0x194 A_DELAY_PS(150) G_DELAY_PS(95) /* CFG_GPMC_A19_OUT */ 308 0x1ac A_DELAY_PS(250) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ 309 0x1b8 A_DELAY_PS(125) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */ 310 0x1c4 A_DELAY_PS(100) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */ 311 0x1d0 A_DELAY_PS(870) G_DELAY_PS(415) /* CFG_GPMC_A23_OUT */ 312 0x1dc A_DELAY_PS(30) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ 313 0x1e8 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ 314 0x1f4 A_DELAY_PS(200) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ 315 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ 316 0x368 A_DELAY_PS(240) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */ 317 0x190 A_DELAY_PS(695) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ 318 0x1a8 A_DELAY_PS(924) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ 319 0x1b4 A_DELAY_PS(719) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ 320 0x1c0 A_DELAY_PS(824) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ 321 0x1d8 A_DELAY_PS(877) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ 322 0x1e4 A_DELAY_PS(446) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ 323 0x1f0 A_DELAY_PS(847) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ 324 0x1fc A_DELAY_PS(586) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ 325 0x364 A_DELAY_PS(1039) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ 326 >; 327 }; 328 329 /* Corresponds to MMC2_MANUAL3 in datamanual */ 330 mmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf { 331 pinctrl-pin-array = < 332 0x194 A_DELAY_PS(285) G_DELAY_PS(0) /* CFG_GPMC_A19_OUT */ 333 0x1ac A_DELAY_PS(189) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */ 334 0x1b8 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_OUT */ 335 0x1c4 A_DELAY_PS(0) G_DELAY_PS(70) /* CFG_GPMC_A22_OUT */ 336 0x1d0 A_DELAY_PS(730) G_DELAY_PS(360) /* CFG_GPMC_A23_OUT */ 337 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */ 338 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */ 339 0x1f4 A_DELAY_PS(70) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */ 340 0x200 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */ 341 0x368 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_CS1_OUT */ 342 0x190 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */ 343 0x1a8 A_DELAY_PS(231) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */ 344 0x1b4 A_DELAY_PS(39) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */ 345 0x1c0 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */ 346 0x1d8 A_DELAY_PS(176) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */ 347 0x1e4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */ 348 0x1f0 A_DELAY_PS(101) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */ 349 0x1fc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */ 350 0x364 A_DELAY_PS(360) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */ 351 >; 352 }; 353 };
Cache object: 1c17c2b67e5090b24b3bcbafbe4b0398
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