Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/contrib/device-tree/src/arm/exynos5422-odroid-core.dtsi
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1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source 4 * 5 * Copyright (c) 2017 Marek Szyprowski 6 * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd. 7 * http://www.samsung.com 8 */ 9 10 #include <dt-bindings/clock/samsung,s2mps11.h> 11 #include <dt-bindings/interrupt-controller/irq.h> 12 #include <dt-bindings/gpio/gpio.h> 13 #include "exynos5800.dtsi" 14 #include "exynos5422-cpus.dtsi" 15 16 / { 17 memory@40000000 { 18 device_type = "memory"; 19 reg = <0x40000000 0x7EA00000>; 20 }; 21 22 chosen { 23 stdout-path = "serial2:115200n8"; 24 }; 25 26 firmware@2073000 { 27 compatible = "samsung,secure-firmware"; 28 reg = <0x02073000 0x1000>; 29 }; 30 31 fixed-rate-clocks { 32 oscclk { 33 compatible = "samsung,exynos5420-oscclk"; 34 clock-frequency = <24000000>; 35 }; 36 }; 37 38 bus_wcore_opp_table: opp-table2 { 39 compatible = "operating-points-v2"; 40 41 /* derived from 532MHz MPLL */ 42 opp00 { 43 opp-hz = /bits/ 64 <88700000>; 44 opp-microvolt = <925000 925000 1400000>; 45 }; 46 opp01 { 47 opp-hz = /bits/ 64 <133000000>; 48 opp-microvolt = <950000 950000 1400000>; 49 }; 50 opp02 { 51 opp-hz = /bits/ 64 <177400000>; 52 opp-microvolt = <950000 950000 1400000>; 53 }; 54 opp03 { 55 opp-hz = /bits/ 64 <266000000>; 56 opp-microvolt = <950000 950000 1400000>; 57 }; 58 opp04 { 59 opp-hz = /bits/ 64 <532000000>; 60 opp-microvolt = <1000000 1000000 1400000>; 61 }; 62 }; 63 64 bus_noc_opp_table: opp-table3 { 65 compatible = "operating-points-v2"; 66 67 /* derived from 666MHz CPLL */ 68 opp00 { 69 opp-hz = /bits/ 64 <66600000>; 70 }; 71 opp01 { 72 opp-hz = /bits/ 64 <74000000>; 73 }; 74 opp02 { 75 opp-hz = /bits/ 64 <83250000>; 76 }; 77 opp03 { 78 opp-hz = /bits/ 64 <111000000>; 79 }; 80 }; 81 82 bus_fsys_apb_opp_table: opp-table4 { 83 compatible = "operating-points-v2"; 84 85 /* derived from 666MHz CPLL */ 86 opp00 { 87 opp-hz = /bits/ 64 <111000000>; 88 }; 89 opp01 { 90 opp-hz = /bits/ 64 <222000000>; 91 }; 92 }; 93 94 bus_fsys2_opp_table: opp-table5 { 95 compatible = "operating-points-v2"; 96 97 /* derived from 600MHz DPLL */ 98 opp00 { 99 opp-hz = /bits/ 64 <75000000>; 100 }; 101 opp01 { 102 opp-hz = /bits/ 64 <120000000>; 103 }; 104 opp02 { 105 opp-hz = /bits/ 64 <200000000>; 106 }; 107 }; 108 109 bus_mfc_opp_table: opp-table6 { 110 compatible = "operating-points-v2"; 111 112 /* derived from 666MHz CPLL */ 113 opp00 { 114 opp-hz = /bits/ 64 <83250000>; 115 }; 116 opp01 { 117 opp-hz = /bits/ 64 <111000000>; 118 }; 119 opp02 { 120 opp-hz = /bits/ 64 <166500000>; 121 }; 122 opp03 { 123 opp-hz = /bits/ 64 <222000000>; 124 }; 125 opp04 { 126 opp-hz = /bits/ 64 <333000000>; 127 }; 128 }; 129 130 bus_gen_opp_table: opp-table7 { 131 compatible = "operating-points-v2"; 132 133 /* derived from 532MHz MPLL */ 134 opp00 { 135 opp-hz = /bits/ 64 <88700000>; 136 }; 137 opp01 { 138 opp-hz = /bits/ 64 <133000000>; 139 }; 140 opp02 { 141 opp-hz = /bits/ 64 <178000000>; 142 }; 143 opp03 { 144 opp-hz = /bits/ 64 <266000000>; 145 }; 146 }; 147 148 bus_peri_opp_table: opp-table8 { 149 compatible = "operating-points-v2"; 150 151 /* derived from 666MHz CPLL */ 152 opp00 { 153 opp-hz = /bits/ 64 <66600000>; 154 }; 155 }; 156 157 bus_g2d_opp_table: opp-table9 { 158 compatible = "operating-points-v2"; 159 160 /* derived from 666MHz CPLL */ 161 opp00 { 162 opp-hz = /bits/ 64 <83250000>; 163 }; 164 opp01 { 165 opp-hz = /bits/ 64 <111000000>; 166 }; 167 opp02 { 168 opp-hz = /bits/ 64 <166500000>; 169 }; 170 opp03 { 171 opp-hz = /bits/ 64 <222000000>; 172 }; 173 opp04 { 174 opp-hz = /bits/ 64 <333000000>; 175 }; 176 }; 177 178 bus_g2d_acp_opp_table: opp-table10 { 179 compatible = "operating-points-v2"; 180 181 /* derived from 532MHz MPLL */ 182 opp00 { 183 opp-hz = /bits/ 64 <66500000>; 184 }; 185 opp01 { 186 opp-hz = /bits/ 64 <133000000>; 187 }; 188 opp02 { 189 opp-hz = /bits/ 64 <178000000>; 190 }; 191 opp03 { 192 opp-hz = /bits/ 64 <266000000>; 193 }; 194 }; 195 196 bus_jpeg_opp_table: opp-table11 { 197 compatible = "operating-points-v2"; 198 199 /* derived from 600MHz DPLL */ 200 opp00 { 201 opp-hz = /bits/ 64 <75000000>; 202 }; 203 opp01 { 204 opp-hz = /bits/ 64 <150000000>; 205 }; 206 opp02 { 207 opp-hz = /bits/ 64 <200000000>; 208 }; 209 opp03 { 210 opp-hz = /bits/ 64 <300000000>; 211 }; 212 }; 213 214 bus_jpeg_apb_opp_table: opp-table12 { 215 compatible = "operating-points-v2"; 216 217 /* derived from 666MHz CPLL */ 218 opp00 { 219 opp-hz = /bits/ 64 <83250000>; 220 }; 221 opp01 { 222 opp-hz = /bits/ 64 <111000000>; 223 }; 224 opp02 { 225 opp-hz = /bits/ 64 <133000000>; 226 }; 227 opp03 { 228 opp-hz = /bits/ 64 <166500000>; 229 }; 230 }; 231 232 bus_disp1_fimd_opp_table: opp-table13 { 233 compatible = "operating-points-v2"; 234 235 /* derived from 600MHz DPLL */ 236 opp00 { 237 opp-hz = /bits/ 64 <120000000>; 238 }; 239 opp01 { 240 opp-hz = /bits/ 64 <200000000>; 241 }; 242 }; 243 244 bus_disp1_opp_table: opp-table14 { 245 compatible = "operating-points-v2"; 246 247 /* derived from 600MHz DPLL */ 248 opp00 { 249 opp-hz = /bits/ 64 <120000000>; 250 }; 251 opp01 { 252 opp-hz = /bits/ 64 <200000000>; 253 }; 254 opp02 { 255 opp-hz = /bits/ 64 <300000000>; 256 }; 257 }; 258 259 bus_gscl_opp_table: opp-table15 { 260 compatible = "operating-points-v2"; 261 262 /* derived from 600MHz DPLL */ 263 opp00 { 264 opp-hz = /bits/ 64 <150000000>; 265 }; 266 opp01 { 267 opp-hz = /bits/ 64 <200000000>; 268 }; 269 opp02 { 270 opp-hz = /bits/ 64 <300000000>; 271 }; 272 }; 273 274 bus_mscl_opp_table: opp-table16 { 275 compatible = "operating-points-v2"; 276 277 /* derived from 666MHz CPLL */ 278 opp00 { 279 opp-hz = /bits/ 64 <84000000>; 280 }; 281 opp01 { 282 opp-hz = /bits/ 64 <167000000>; 283 }; 284 opp02 { 285 opp-hz = /bits/ 64 <222000000>; 286 }; 287 opp03 { 288 opp-hz = /bits/ 64 <333000000>; 289 }; 290 opp04 { 291 opp-hz = /bits/ 64 <666000000>; 292 }; 293 }; 294 295 dmc_opp_table: opp-table17 { 296 compatible = "operating-points-v2"; 297 298 opp00 { 299 opp-hz = /bits/ 64 <165000000>; 300 opp-microvolt = <875000>; 301 }; 302 opp01 { 303 opp-hz = /bits/ 64 <206000000>; 304 opp-microvolt = <875000>; 305 }; 306 opp02 { 307 opp-hz = /bits/ 64 <275000000>; 308 opp-microvolt = <875000>; 309 }; 310 opp03 { 311 opp-hz = /bits/ 64 <413000000>; 312 opp-microvolt = <887500>; 313 }; 314 opp04 { 315 opp-hz = /bits/ 64 <543000000>; 316 opp-microvolt = <937500>; 317 }; 318 opp05 { 319 opp-hz = /bits/ 64 <633000000>; 320 opp-microvolt = <1012500>; 321 }; 322 opp06 { 323 opp-hz = /bits/ 64 <728000000>; 324 opp-microvolt = <1037500>; 325 }; 326 opp07 { 327 opp-hz = /bits/ 64 <825000000>; 328 opp-microvolt = <1050000>; 329 }; 330 }; 331 332 samsung_K3QF2F20DB: lpddr3 { 333 compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; 334 density = <16384>; 335 io-width = <32>; 336 337 tRFC-min-tck = <17>; 338 tRRD-min-tck = <2>; 339 tRPab-min-tck = <2>; 340 tRPpb-min-tck = <2>; 341 tRCD-min-tck = <3>; 342 tRC-min-tck = <6>; 343 tRAS-min-tck = <5>; 344 tWTR-min-tck = <2>; 345 tWR-min-tck = <7>; 346 tRTP-min-tck = <2>; 347 tW2W-C2C-min-tck = <0>; 348 tR2R-C2C-min-tck = <0>; 349 tWL-min-tck = <8>; 350 tDQSCK-min-tck = <5>; 351 tRL-min-tck = <14>; 352 tFAW-min-tck = <5>; 353 tXSR-min-tck = <12>; 354 tXP-min-tck = <2>; 355 tCKE-min-tck = <2>; 356 tCKESR-min-tck = <2>; 357 tMRD-min-tck = <5>; 358 359 timings_samsung_K3QF2F20DB_800mhz: timings { 360 compatible = "jedec,lpddr3-timings"; 361 max-freq = <800000000>; 362 min-freq = <100000000>; 363 tRFC = <65000>; 364 tRRD = <6000>; 365 tRPab = <12000>; 366 tRPpb = <12000>; 367 tRCD = <10000>; 368 tRC = <33750>; 369 tRAS = <23000>; 370 tWTR = <3750>; 371 tWR = <7500>; 372 tRTP = <3750>; 373 tW2W-C2C = <0>; 374 tR2R-C2C = <0>; 375 tFAW = <25000>; 376 tXSR = <70000>; 377 tXP = <3750>; 378 tCKE = <3750>; 379 tCKESR = <3750>; 380 tMRD = <7000>; 381 }; 382 }; 383 }; 384 385 &adc { 386 vdd-supply = <&ldo4_reg>; 387 status = "okay"; 388 }; 389 390 &bus_wcore { 391 operating-points-v2 = <&bus_wcore_opp_table>; 392 devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>, 393 <&nocp_mem1_0>, <&nocp_mem1_1>; 394 vdd-supply = <&buck3_reg>; 395 exynos,saturation-ratio = <100>; 396 status = "okay"; 397 }; 398 399 &bus_noc { 400 operating-points-v2 = <&bus_noc_opp_table>; 401 devfreq = <&bus_wcore>; 402 status = "okay"; 403 }; 404 405 &bus_fsys_apb { 406 operating-points-v2 = <&bus_fsys_apb_opp_table>; 407 devfreq = <&bus_wcore>; 408 status = "okay"; 409 }; 410 411 &bus_fsys2 { 412 operating-points-v2 = <&bus_fsys2_opp_table>; 413 devfreq = <&bus_wcore>; 414 status = "okay"; 415 }; 416 417 &bus_mfc { 418 operating-points-v2 = <&bus_mfc_opp_table>; 419 devfreq = <&bus_wcore>; 420 status = "okay"; 421 }; 422 423 &bus_gen { 424 operating-points-v2 = <&bus_gen_opp_table>; 425 devfreq = <&bus_wcore>; 426 status = "okay"; 427 }; 428 429 &bus_peri { 430 operating-points-v2 = <&bus_peri_opp_table>; 431 devfreq = <&bus_wcore>; 432 status = "okay"; 433 }; 434 435 &bus_g2d { 436 operating-points-v2 = <&bus_g2d_opp_table>; 437 devfreq = <&bus_wcore>; 438 status = "okay"; 439 }; 440 441 &bus_g2d_acp { 442 operating-points-v2 = <&bus_g2d_acp_opp_table>; 443 devfreq = <&bus_wcore>; 444 status = "okay"; 445 }; 446 447 &bus_jpeg { 448 operating-points-v2 = <&bus_jpeg_opp_table>; 449 devfreq = <&bus_wcore>; 450 status = "okay"; 451 }; 452 453 &bus_jpeg_apb { 454 operating-points-v2 = <&bus_jpeg_apb_opp_table>; 455 devfreq = <&bus_wcore>; 456 status = "okay"; 457 }; 458 459 &bus_disp1_fimd { 460 operating-points-v2 = <&bus_disp1_fimd_opp_table>; 461 devfreq = <&bus_wcore>; 462 status = "okay"; 463 }; 464 465 &bus_disp1 { 466 operating-points-v2 = <&bus_disp1_opp_table>; 467 devfreq = <&bus_wcore>; 468 status = "okay"; 469 }; 470 471 &bus_gscl_scaler { 472 operating-points-v2 = <&bus_gscl_opp_table>; 473 devfreq = <&bus_wcore>; 474 status = "okay"; 475 }; 476 477 &bus_mscl { 478 operating-points-v2 = <&bus_mscl_opp_table>; 479 devfreq = <&bus_wcore>; 480 status = "okay"; 481 }; 482 483 &cpu0 { 484 cpu-supply = <&buck6_reg>; 485 }; 486 487 &cpu4 { 488 cpu-supply = <&buck2_reg>; 489 }; 490 491 &dmc { 492 devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, 493 <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; 494 device-handle = <&samsung_K3QF2F20DB>; 495 operating-points-v2 = <&dmc_opp_table>; 496 vdd-supply = <&buck1_reg>; 497 status = "okay"; 498 }; 499 500 &hsi2c_4 { 501 status = "okay"; 502 503 pmic@66 { 504 compatible = "samsung,s2mps11-pmic"; 505 reg = <0x66>; 506 samsung,s2mps11-acokb-ground; 507 508 interrupt-parent = <&gpx0>; 509 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 510 pinctrl-names = "default"; 511 pinctrl-0 = <&s2mps11_irq>; 512 wakeup-source; 513 514 s2mps11_osc: clocks { 515 compatible = "samsung,s2mps11-clk"; 516 #clock-cells = <1>; 517 clock-output-names = "s2mps11_ap", 518 "s2mps11_cp", "s2mps11_bt"; 519 }; 520 521 regulators { 522 ldo1_reg: LDO1 { 523 regulator-name = "vdd_ldo1"; 524 regulator-min-microvolt = <1000000>; 525 regulator-max-microvolt = <1000000>; 526 regulator-always-on; 527 }; 528 529 ldo2_reg: LDO2 { 530 regulator-name = "vdd_ldo2"; 531 regulator-min-microvolt = <1800000>; 532 regulator-max-microvolt = <1800000>; 533 regulator-always-on; 534 }; 535 536 ldo3_reg: LDO3 { 537 regulator-name = "vddq_mmc0"; 538 regulator-min-microvolt = <1800000>; 539 regulator-max-microvolt = <1800000>; 540 }; 541 542 ldo4_reg: LDO4 { 543 regulator-name = "vdd_adc"; 544 regulator-min-microvolt = <1800000>; 545 regulator-max-microvolt = <1800000>; 546 547 regulator-state-mem { 548 regulator-off-in-suspend; 549 }; 550 }; 551 552 ldo5_reg: LDO5 { 553 regulator-name = "vdd_ldo5"; 554 regulator-min-microvolt = <1800000>; 555 regulator-max-microvolt = <1800000>; 556 regulator-always-on; 557 558 regulator-state-mem { 559 regulator-off-in-suspend; 560 }; 561 }; 562 563 ldo6_reg: LDO6 { 564 regulator-name = "vdd_ldo6"; 565 regulator-min-microvolt = <1000000>; 566 regulator-max-microvolt = <1000000>; 567 regulator-always-on; 568 569 regulator-state-mem { 570 regulator-off-in-suspend; 571 }; 572 }; 573 574 ldo7_reg: LDO7 { 575 regulator-name = "vdd_ldo7"; 576 regulator-min-microvolt = <1800000>; 577 regulator-max-microvolt = <1800000>; 578 regulator-always-on; 579 580 regulator-state-mem { 581 regulator-off-in-suspend; 582 }; 583 }; 584 585 ldo8_reg: LDO8 { 586 regulator-name = "vdd_ldo8"; 587 regulator-min-microvolt = <1800000>; 588 regulator-max-microvolt = <1800000>; 589 regulator-always-on; 590 591 regulator-state-mem { 592 regulator-off-in-suspend; 593 }; 594 }; 595 596 ldo9_reg: LDO9 { 597 regulator-name = "vdd_ldo9"; 598 regulator-min-microvolt = <3000000>; 599 regulator-max-microvolt = <3000000>; 600 regulator-always-on; 601 602 regulator-state-mem { 603 regulator-off-in-suspend; 604 }; 605 }; 606 607 ldo10_reg: LDO10 { 608 regulator-name = "vdd_ldo10"; 609 regulator-min-microvolt = <1800000>; 610 regulator-max-microvolt = <1800000>; 611 regulator-always-on; 612 613 regulator-state-mem { 614 regulator-off-in-suspend; 615 }; 616 }; 617 618 ldo11_reg: LDO11 { 619 regulator-name = "vdd_ldo11"; 620 regulator-min-microvolt = <1000000>; 621 regulator-max-microvolt = <1000000>; 622 regulator-always-on; 623 624 regulator-state-mem { 625 regulator-off-in-suspend; 626 }; 627 }; 628 629 ldo12_reg: LDO12 { 630 /* Unused */ 631 regulator-name = "vdd_ldo12"; 632 regulator-min-microvolt = <800000>; 633 regulator-max-microvolt = <2375000>; 634 }; 635 636 ldo13_reg: LDO13 { 637 regulator-name = "vddq_mmc2"; 638 regulator-min-microvolt = <1800000>; 639 regulator-max-microvolt = <2800000>; 640 641 regulator-state-mem { 642 regulator-off-in-suspend; 643 }; 644 }; 645 646 ldo14_reg: LDO14 { 647 /* Unused */ 648 regulator-name = "vdd_ldo14"; 649 regulator-min-microvolt = <800000>; 650 regulator-max-microvolt = <3950000>; 651 }; 652 653 ldo15_reg: LDO15 { 654 regulator-name = "vdd_ldo15"; 655 regulator-min-microvolt = <3300000>; 656 regulator-max-microvolt = <3300000>; 657 regulator-always-on; 658 659 regulator-state-mem { 660 regulator-off-in-suspend; 661 }; 662 }; 663 664 ldo16_reg: LDO16 { 665 /* Unused */ 666 regulator-name = "vdd_ldo16"; 667 regulator-min-microvolt = <800000>; 668 regulator-max-microvolt = <3950000>; 669 }; 670 671 ldo17_reg: LDO17 { 672 regulator-name = "vdd_ldo17"; 673 regulator-min-microvolt = <3300000>; 674 regulator-max-microvolt = <3300000>; 675 regulator-always-on; 676 677 regulator-state-mem { 678 regulator-off-in-suspend; 679 }; 680 }; 681 682 ldo18_reg: LDO18 { 683 regulator-name = "vdd_emmc_1V8"; 684 regulator-min-microvolt = <1800000>; 685 regulator-max-microvolt = <1800000>; 686 687 regulator-state-mem { 688 regulator-off-in-suspend; 689 }; 690 }; 691 692 ldo19_reg: LDO19 { 693 regulator-name = "vdd_sd"; 694 regulator-min-microvolt = <2800000>; 695 regulator-max-microvolt = <2800000>; 696 697 regulator-state-mem { 698 regulator-off-in-suspend; 699 }; 700 }; 701 702 ldo20_reg: LDO20 { 703 /* Unused */ 704 regulator-name = "vdd_ldo20"; 705 regulator-min-microvolt = <800000>; 706 regulator-max-microvolt = <3950000>; 707 }; 708 709 ldo21_reg: LDO21 { 710 /* Unused */ 711 regulator-name = "vdd_ldo21"; 712 regulator-min-microvolt = <800000>; 713 regulator-max-microvolt = <3950000>; 714 }; 715 716 ldo22_reg: LDO22 { 717 /* Unused */ 718 regulator-name = "vdd_ldo22"; 719 regulator-min-microvolt = <800000>; 720 regulator-max-microvolt = <2375000>; 721 }; 722 723 ldo23_reg: LDO23 { 724 regulator-name = "vdd_mifs"; 725 regulator-min-microvolt = <1100000>; 726 regulator-max-microvolt = <1100000>; 727 regulator-always-on; 728 729 regulator-state-mem { 730 regulator-off-in-suspend; 731 }; 732 }; 733 734 ldo24_reg: LDO24 { 735 /* Unused */ 736 regulator-name = "vdd_ldo24"; 737 regulator-min-microvolt = <800000>; 738 regulator-max-microvolt = <3950000>; 739 }; 740 741 ldo25_reg: LDO25 { 742 /* Unused */ 743 regulator-name = "vdd_ldo25"; 744 regulator-min-microvolt = <800000>; 745 regulator-max-microvolt = <3950000>; 746 }; 747 748 ldo26_reg: LDO26 { 749 /* Used on XU3, XU3-Lite and XU4 */ 750 regulator-name = "vdd_ldo26"; 751 regulator-min-microvolt = <800000>; 752 regulator-max-microvolt = <3950000>; 753 754 regulator-state-mem { 755 regulator-off-in-suspend; 756 }; 757 }; 758 759 ldo27_reg: LDO27 { 760 regulator-name = "vdd_g3ds"; 761 regulator-min-microvolt = <1000000>; 762 regulator-max-microvolt = <1000000>; 763 regulator-always-on; 764 765 regulator-state-mem { 766 regulator-off-in-suspend; 767 }; 768 }; 769 770 ldo28_reg: LDO28 { 771 /* Used on XU3 */ 772 regulator-name = "vdd_ldo28"; 773 regulator-min-microvolt = <800000>; 774 regulator-max-microvolt = <3950000>; 775 776 regulator-state-mem { 777 regulator-off-in-suspend; 778 }; 779 }; 780 781 ldo29_reg: LDO29 { 782 /* Unused */ 783 regulator-name = "vdd_ldo29"; 784 regulator-min-microvolt = <800000>; 785 regulator-max-microvolt = <3950000>; 786 }; 787 788 ldo30_reg: LDO30 { 789 /* Unused */ 790 regulator-name = "vdd_ldo30"; 791 regulator-min-microvolt = <800000>; 792 regulator-max-microvolt = <3950000>; 793 }; 794 795 ldo31_reg: LDO31 { 796 /* Unused */ 797 regulator-name = "vdd_ldo31"; 798 regulator-min-microvolt = <800000>; 799 regulator-max-microvolt = <3950000>; 800 }; 801 802 ldo32_reg: LDO32 { 803 /* Unused */ 804 regulator-name = "vdd_ldo32"; 805 regulator-min-microvolt = <800000>; 806 regulator-max-microvolt = <3950000>; 807 }; 808 809 ldo33_reg: LDO33 { 810 /* Unused */ 811 regulator-name = "vdd_ldo33"; 812 regulator-min-microvolt = <800000>; 813 regulator-max-microvolt = <3950000>; 814 }; 815 816 ldo34_reg: LDO34 { 817 /* Unused */ 818 regulator-name = "vdd_ldo34"; 819 regulator-min-microvolt = <800000>; 820 regulator-max-microvolt = <3950000>; 821 }; 822 823 ldo35_reg: LDO35 { 824 /* Unused */ 825 regulator-name = "vdd_ldo35"; 826 regulator-min-microvolt = <800000>; 827 regulator-max-microvolt = <2375000>; 828 }; 829 830 ldo36_reg: LDO36 { 831 /* Unused */ 832 regulator-name = "vdd_ldo36"; 833 regulator-min-microvolt = <800000>; 834 regulator-max-microvolt = <3950000>; 835 }; 836 837 ldo37_reg: LDO37 { 838 /* Unused */ 839 regulator-name = "vdd_ldo37"; 840 regulator-min-microvolt = <800000>; 841 regulator-max-microvolt = <3950000>; 842 }; 843 844 ldo38_reg: LDO38 { 845 /* Unused */ 846 regulator-name = "vdd_ldo38"; 847 regulator-min-microvolt = <800000>; 848 regulator-max-microvolt = <3950000>; 849 }; 850 851 buck1_reg: BUCK1 { 852 regulator-name = "vdd_mif"; 853 regulator-min-microvolt = <800000>; 854 regulator-max-microvolt = <1300000>; 855 regulator-always-on; 856 regulator-boot-on; 857 858 regulator-state-mem { 859 regulator-off-in-suspend; 860 }; 861 }; 862 863 buck2_reg: BUCK2 { 864 regulator-name = "vdd_arm"; 865 regulator-min-microvolt = <800000>; 866 regulator-max-microvolt = <1500000>; 867 regulator-always-on; 868 regulator-boot-on; 869 regulator-coupled-with = <&buck3_reg>; 870 regulator-coupled-max-spread = <300000>; 871 872 regulator-state-mem { 873 regulator-off-in-suspend; 874 }; 875 }; 876 877 buck3_reg: BUCK3 { 878 regulator-name = "vdd_int"; 879 regulator-min-microvolt = <800000>; 880 regulator-max-microvolt = <1400000>; 881 regulator-always-on; 882 regulator-boot-on; 883 regulator-coupled-with = <&buck2_reg>; 884 regulator-coupled-max-spread = <300000>; 885 886 regulator-state-mem { 887 regulator-off-in-suspend; 888 }; 889 }; 890 891 buck4_reg: BUCK4 { 892 regulator-name = "vdd_g3d"; 893 regulator-min-microvolt = <800000>; 894 regulator-max-microvolt = <1400000>; 895 regulator-boot-on; 896 regulator-always-on; 897 898 regulator-state-mem { 899 regulator-off-in-suspend; 900 }; 901 }; 902 903 buck5_reg: BUCK5 { 904 regulator-name = "vdd_mem"; 905 regulator-min-microvolt = <800000>; 906 regulator-max-microvolt = <1400000>; 907 regulator-always-on; 908 regulator-boot-on; 909 }; 910 911 buck6_reg: BUCK6 { 912 regulator-name = "vdd_kfc"; 913 regulator-min-microvolt = <800000>; 914 regulator-max-microvolt = <1500000>; 915 regulator-always-on; 916 regulator-boot-on; 917 918 regulator-state-mem { 919 regulator-off-in-suspend; 920 }; 921 }; 922 923 buck7_reg: BUCK7 { 924 regulator-name = "vdd_1.35v_ldo"; 925 regulator-min-microvolt = <1200000>; 926 regulator-max-microvolt = <1500000>; 927 regulator-always-on; 928 regulator-boot-on; 929 }; 930 931 buck8_reg: BUCK8 { 932 regulator-name = "vdd_2.0v_ldo"; 933 regulator-min-microvolt = <1800000>; 934 regulator-max-microvolt = <2100000>; 935 regulator-always-on; 936 regulator-boot-on; 937 }; 938 939 buck9_reg: BUCK9 { 940 regulator-name = "vdd_2.8v_ldo"; 941 regulator-min-microvolt = <3000000>; 942 regulator-max-microvolt = <3750000>; 943 regulator-always-on; 944 regulator-boot-on; 945 946 regulator-state-mem { 947 regulator-off-in-suspend; 948 }; 949 }; 950 951 buck10_reg: BUCK10 { 952 regulator-name = "vdd_vmem"; 953 regulator-min-microvolt = <2850000>; 954 regulator-max-microvolt = <2850000>; 955 956 regulator-state-mem { 957 regulator-off-in-suspend; 958 }; 959 }; 960 }; 961 }; 962 }; 963 964 &mmc_2 { 965 status = "okay"; 966 card-detect-delay = <200>; 967 samsung,dw-mshc-ciu-div = <3>; 968 samsung,dw-mshc-sdr-timing = <0 4>; 969 samsung,dw-mshc-ddr-timing = <0 2>; 970 pinctrl-names = "default"; 971 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>; 972 bus-width = <4>; 973 cap-sd-highspeed; 974 max-frequency = <200000000>; 975 vmmc-supply = <&ldo19_reg>; 976 vqmmc-supply = <&ldo13_reg>; 977 sd-uhs-sdr50; 978 sd-uhs-sdr104; 979 sd-uhs-ddr50; 980 }; 981 982 &nocp_mem0_0 { 983 status = "okay"; 984 }; 985 986 &nocp_mem0_1 { 987 status = "okay"; 988 }; 989 990 &nocp_mem1_0 { 991 status = "okay"; 992 }; 993 994 &nocp_mem1_1 { 995 status = "okay"; 996 }; 997 998 &pinctrl_0 { 999 s2mps11_irq: s2mps11-irq-pins { 1000 samsung,pins = "gpx0-4"; 1001 samsung,pin-function = <EXYNOS_PIN_FUNC_F>; 1002 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 1003 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>; 1004 }; 1005 }; 1006 1007 &ppmu_dmc0_0 { 1008 status = "okay"; 1009 }; 1010 1011 &ppmu_dmc0_1 { 1012 status = "okay"; 1013 }; 1014 1015 &ppmu_dmc1_0 { 1016 status = "okay"; 1017 }; 1018 1019 &ppmu_dmc1_1 { 1020 status = "okay"; 1021 }; 1022 1023 &tmu_cpu0 { 1024 vtmu-supply = <&ldo7_reg>; 1025 }; 1026 1027 &tmu_cpu1 { 1028 vtmu-supply = <&ldo7_reg>; 1029 }; 1030 1031 &tmu_cpu2 { 1032 vtmu-supply = <&ldo7_reg>; 1033 }; 1034 1035 &tmu_cpu3 { 1036 vtmu-supply = <&ldo7_reg>; 1037 }; 1038 1039 &tmu_gpu { 1040 vtmu-supply = <&ldo7_reg>; 1041 }; 1042 1043 &gpu { 1044 mali-supply = <&buck4_reg>; 1045 status = "okay"; 1046 }; 1047 1048 &rtc { 1049 status = "okay"; 1050 clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; 1051 clock-names = "rtc", "rtc_src"; 1052 }; 1053 1054 &usbdrd_dwc3_0 { 1055 dr_mode = "host"; 1056 }; 1057 1058 /* usbdrd_dwc3_1 mode customized in each board */ 1059 1060 &usbdrd3_0 { 1061 vdd33-supply = <&ldo9_reg>; 1062 vdd10-supply = <&ldo11_reg>; 1063 }; 1064 1065 &usbdrd3_1 { 1066 vdd33-supply = <&ldo9_reg>; 1067 vdd10-supply = <&ldo11_reg>; 1068 };
Cache object: cbc6b22a2d92d32278fe26bf1778efb0
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