exynos54xx.dtsi

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    1 // SPDX-License-Identifier: GPL-2.0
    2 /*
    3  * Samsung's Exynos54xx SoC series common device tree source
    4  *
    5  * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
    6  *              http://www.samsung.com
    7  * Copyright (c) 2016 Krzysztof Kozlowski
    8  *
    9  * Device nodes common for Samsung Exynos5410/5420/5422/5800. Specific
   10  * Exynos 54xx SoCs should include this file and customize it further
   11  * (e.g. with clocks).
   12  */
   13 
   14 #include "exynos5.dtsi"
   15 
   16 / {
   17         compatible = "samsung,exynos5";
   18 
   19         aliases {
   20                 i2c4 = &hsi2c_4;
   21                 i2c5 = &hsi2c_5;
   22                 i2c6 = &hsi2c_6;
   23                 i2c7 = &hsi2c_7;
   24                 usbdrdphy0 = &usbdrd_phy0;
   25                 usbdrdphy1 = &usbdrd_phy1;
   26         };
   27 
   28         arm_a7_pmu: arm-a7-pmu {
   29                 compatible = "arm,cortex-a7-pmu";
   30                 interrupt-parent = <&gic>;
   31                 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
   32                              <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
   33                              <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
   34                              <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
   35                 status = "disabled";
   36         };
   37 
   38         arm_a15_pmu: arm-a15-pmu {
   39                 compatible = "arm,cortex-a15-pmu";
   40                 interrupt-parent = <&combiner>;
   41                 interrupts = <1 2>,
   42                              <7 0>,
   43                              <16 6>,
   44                              <19 2>;
   45                 status = "disabled";
   46         };
   47 
   48         timer: timer {
   49                 compatible = "arm,armv7-timer";
   50                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
   51                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
   52                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
   53                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
   54                 clock-frequency = <24000000>;
   55         };
   56 
   57         soc: soc {
   58                 sram@2020000 {
   59                         compatible = "mmio-sram";
   60                         reg = <0x02020000 0x54000>;
   61                         #address-cells = <1>;
   62                         #size-cells = <1>;
   63                         ranges = <0 0x02020000 0x54000>;
   64 
   65                         smp-sram@0 {
   66                                 compatible = "samsung,exynos4210-sysram";
   67                                 reg = <0x0 0x1000>;
   68                         };
   69 
   70                         smp-sram@53000 {
   71                                 compatible = "samsung,exynos4210-sysram-ns";
   72                                 reg = <0x53000 0x1000>;
   73                         };
   74                 };
   75 
   76                 mct: timer@101c0000 {
   77                         compatible = "samsung,exynos5420-mct",
   78                                      "samsung,exynos4210-mct";
   79                         reg = <0x101c0000 0xb00>;
   80                         interrupts-extended = <&combiner 23 3>,
   81                                               <&combiner 23 4>,
   82                                               <&combiner 25 2>,
   83                                               <&combiner 25 3>,
   84                                               <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
   85                                               <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
   86                                               <&gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
   87                                               <&gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
   88                                               <&gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
   89                                               <&gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
   90                                               <&gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
   91                                               <&gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
   92                 };
   93 
   94                 watchdog: watchdog@101d0000 {
   95                         compatible = "samsung,exynos5420-wdt";
   96                         reg = <0x101d0000 0x100>;
   97                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
   98                 };
   99 
  100                 adc: adc@12d10000 {
  101                         compatible = "samsung,exynos-adc-v2";
  102                         reg = <0x12d10000 0x100>;
  103                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
  104                         #io-channel-cells = <1>;
  105                         status = "disabled";
  106                 };
  107 
  108                 /* i2c_0-3 are defined in exynos5.dtsi */
  109                 hsi2c_4: i2c@12ca0000 {
  110                         compatible = "samsung,exynos5250-hsi2c";
  111                         reg = <0x12ca0000 0x1000>;
  112                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
  113                         #address-cells = <1>;
  114                         #size-cells = <0>;
  115                         status = "disabled";
  116                 };
  117 
  118                 hsi2c_5: i2c@12cb0000 {
  119                         compatible = "samsung,exynos5250-hsi2c";
  120                         reg = <0x12cb0000 0x1000>;
  121                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
  122                         #address-cells = <1>;
  123                         #size-cells = <0>;
  124                         status = "disabled";
  125                 };
  126 
  127                 hsi2c_6: i2c@12cc0000 {
  128                         compatible = "samsung,exynos5250-hsi2c";
  129                         reg = <0x12cc0000 0x1000>;
  130                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
  131                         #address-cells = <1>;
  132                         #size-cells = <0>;
  133                         status = "disabled";
  134                 };
  135 
  136                 hsi2c_7: i2c@12cd0000 {
  137                         compatible = "samsung,exynos5250-hsi2c";
  138                         reg = <0x12cd0000 0x1000>;
  139                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
  140                         #address-cells = <1>;
  141                         #size-cells = <0>;
  142                         status = "disabled";
  143                 };
  144 
  145                 usbdrd3_0: usb3-0 {
  146                         compatible = "samsung,exynos5250-dwusb3";
  147                         #address-cells = <1>;
  148                         #size-cells = <1>;
  149                         ranges;
  150 
  151                         usbdrd_dwc3_0: usb@12000000 {
  152                                 compatible = "snps,dwc3";
  153                                 reg = <0x12000000 0x10000>;
  154                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  155                                 phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
  156                                 phy-names = "usb2-phy", "usb3-phy";
  157                                 snps,dis_u3_susphy_quirk;
  158                         };
  159                 };
  160 
  161                 usbdrd_phy0: phy@12100000 {
  162                         compatible = "samsung,exynos5420-usbdrd-phy";
  163                         reg = <0x12100000 0x100>;
  164                         #phy-cells = <1>;
  165                 };
  166 
  167                 usbdrd3_1: usb3-1 {
  168                         compatible = "samsung,exynos5250-dwusb3";
  169                         #address-cells = <1>;
  170                         #size-cells = <1>;
  171                         ranges;
  172 
  173                         usbdrd_dwc3_1: usb@12400000 {
  174                                 compatible = "snps,dwc3";
  175                                 reg = <0x12400000 0x10000>;
  176                                 phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
  177                                 phy-names = "usb2-phy", "usb3-phy";
  178                                 snps,dis_u3_susphy_quirk;
  179                         };
  180                 };
  181 
  182                 usbdrd_phy1: phy@12500000 {
  183                         compatible = "samsung,exynos5420-usbdrd-phy";
  184                         reg = <0x12500000 0x100>;
  185                         #phy-cells = <1>;
  186                 };
  187 
  188                 usbhost2: usb@12110000 {
  189                         compatible = "samsung,exynos4210-ehci";
  190                         reg = <0x12110000 0x100>;
  191                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  192                         phys = <&usb2_phy 0>;
  193                         phy-names = "host";
  194                 };
  195 
  196                 usbhost1: usb@12120000 {
  197                         compatible = "samsung,exynos4210-ohci";
  198                         reg = <0x12120000 0x100>;
  199                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  200                         phys = <&usb2_phy 0>;
  201                         phy-names = "host";
  202                 };
  203 
  204                 usb2_phy: phy@12130000 {
  205                         compatible = "samsung,exynos5420-usb2-phy";
  206                         reg = <0x12130000 0x100>;
  207                         #phy-cells = <1>;
  208                 };
  209         };
  210 };

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sys/contrib/device-tree/src/arm/exynos54xx.dtsi