Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/highbank.dts
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1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright 2011-2012 Calxeda, Inc. 4 */ 5 6 /dts-v1/; 7 8 /* First 4KB has pen for secondary cores. */ 9 /memreserve/ 0x00000000 0x0001000; 10 11 / { 12 model = "Calxeda Highbank"; 13 compatible = "calxeda,highbank"; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu@900 { 22 compatible = "arm,cortex-a9"; 23 device_type = "cpu"; 24 reg = <0x900>; 25 next-level-cache = <&L2>; 26 clocks = <&a9pll>; 27 clock-names = "cpu"; 28 operating-points = < 29 /* kHz ignored */ 30 1300000 1000000 31 1200000 1000000 32 1100000 1000000 33 800000 1000000 34 400000 1000000 35 200000 1000000 36 >; 37 clock-latency = <100000>; 38 }; 39 40 cpu@901 { 41 compatible = "arm,cortex-a9"; 42 device_type = "cpu"; 43 reg = <0x901>; 44 next-level-cache = <&L2>; 45 clocks = <&a9pll>; 46 clock-names = "cpu"; 47 operating-points = < 48 /* kHz ignored */ 49 1300000 1000000 50 1200000 1000000 51 1100000 1000000 52 800000 1000000 53 400000 1000000 54 200000 1000000 55 >; 56 clock-latency = <100000>; 57 }; 58 59 cpu@902 { 60 compatible = "arm,cortex-a9"; 61 device_type = "cpu"; 62 reg = <0x902>; 63 next-level-cache = <&L2>; 64 clocks = <&a9pll>; 65 clock-names = "cpu"; 66 operating-points = < 67 /* kHz ignored */ 68 1300000 1000000 69 1200000 1000000 70 1100000 1000000 71 800000 1000000 72 400000 1000000 73 200000 1000000 74 >; 75 clock-latency = <100000>; 76 }; 77 78 cpu@903 { 79 compatible = "arm,cortex-a9"; 80 device_type = "cpu"; 81 reg = <0x903>; 82 next-level-cache = <&L2>; 83 clocks = <&a9pll>; 84 clock-names = "cpu"; 85 operating-points = < 86 /* kHz ignored */ 87 1300000 1000000 88 1200000 1000000 89 1100000 1000000 90 800000 1000000 91 400000 1000000 92 200000 1000000 93 >; 94 clock-latency = <100000>; 95 }; 96 }; 97 98 memory@0 { 99 name = "memory"; 100 device_type = "memory"; 101 reg = <0x00000000 0xff900000>; 102 }; 103 104 soc { 105 ranges = <0x00000000 0x00000000 0xffffffff>; 106 107 memory-controller@fff00000 { 108 compatible = "calxeda,hb-ddr-ctrl"; 109 reg = <0xfff00000 0x1000>; 110 interrupts = <0 91 4>; 111 }; 112 113 timer@fff10600 { 114 compatible = "arm,cortex-a9-twd-timer"; 115 reg = <0xfff10600 0x20>; 116 interrupts = <1 13 0xf01>; 117 clocks = <&a9periphclk>; 118 }; 119 120 watchdog@fff10620 { 121 compatible = "arm,cortex-a9-twd-wdt"; 122 reg = <0xfff10620 0x20>; 123 interrupts = <1 14 0xf01>; 124 clocks = <&a9periphclk>; 125 }; 126 127 intc: interrupt-controller@fff11000 { 128 compatible = "arm,cortex-a9-gic"; 129 #interrupt-cells = <3>; 130 interrupt-controller; 131 reg = <0xfff11000 0x1000>, 132 <0xfff10100 0x100>; 133 }; 134 135 L2: cache-controller { 136 compatible = "arm,pl310-cache"; 137 reg = <0xfff12000 0x1000>; 138 interrupts = <0 70 4>; 139 cache-unified; 140 cache-level = <2>; 141 }; 142 143 pmu { 144 compatible = "arm,cortex-a9-pmu"; 145 interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>; 146 }; 147 148 149 sregs@fff3c200 { 150 compatible = "calxeda,hb-sregs-l2-ecc"; 151 reg = <0xfff3c200 0x100>; 152 interrupts = <0 71 4>, <0 72 4>; 153 }; 154 155 }; 156 }; 157 158 /include/ "ecx-common.dtsi"
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