Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/imx1-pinfunc.h
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> 4 */ 5 6 #ifndef __DTS_IMX1_PINFUNC_H 7 #define __DTS_IMX1_PINFUNC_H 8 9 /* 10 * The pin function ID is a tuple of 11 * <pin mux_id> 12 * mux_id consists of 13 * function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10) 14 * 15 * function: 0 - Primary function 16 * 1 - Alternate function 17 * 2 - GPIO 18 * direction: 0 - Input 19 * 1 - Output 20 * gpio_oconf: 0 - A_IN 21 * 1 - B_IN 22 * 2 - A_OUT 23 * 3 - Data Register 24 * gpio_iconfa/b: 0 - GPIO_IN 25 * 1 - Interrupt Status Register 26 * 2 - 0 27 * 3 - 1 28 * 29 * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32 30 * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is 31 * the pin number on the specific port (between 0 and 31). 32 */ 33 34 #define MX1_PAD_A24__A24 0x00 0x004 35 #define MX1_PAD_A24__GPIO1_0 0x00 0x032 36 #define MX1_PAD_A24__SPI2_CLK 0x00 0x006 37 #define MX1_PAD_TIN__TIN 0x01 0x000 38 #define MX1_PAD_TIN__GPIO1_1 0x01 0x032 39 #define MX1_PAD_TIN__SPI2_RXD 0x01 0x022 40 #define MX1_PAD_PWMO__PWMO 0x02 0x004 41 #define MX1_PAD_PWMO__GPIO1_2 0x02 0x032 42 #define MX1_PAD_CSI_MCLK__CSI_MCLK 0x03 0x004 43 #define MX1_PAD_CSI_MCLK__GPIO1_3 0x03 0x032 44 #define MX1_PAD_CSI_D0__CSI_D0 0x04 0x000 45 #define MX1_PAD_CSI_D0__GPIO1_4 0x04 0x032 46 #define MX1_PAD_CSI_D1__CSI_D1 0x05 0x000 47 #define MX1_PAD_CSI_D1__GPIO1_5 0x05 0x032 48 #define MX1_PAD_CSI_D2__CSI_D2 0x06 0x000 49 #define MX1_PAD_CSI_D2__GPIO1_6 0x06 0x032 50 #define MX1_PAD_CSI_D3__CSI_D3 0x07 0x000 51 #define MX1_PAD_CSI_D3__GPIO1_7 0x07 0x032 52 #define MX1_PAD_CSI_D4__CSI_D4 0x08 0x000 53 #define MX1_PAD_CSI_D4__GPIO1_8 0x08 0x032 54 #define MX1_PAD_CSI_D5__CSI_D5 0x09 0x000 55 #define MX1_PAD_CSI_D5__GPIO1_9 0x09 0x032 56 #define MX1_PAD_CSI_D6__CSI_D6 0x0a 0x000 57 #define MX1_PAD_CSI_D6__GPIO1_10 0x0a 0x032 58 #define MX1_PAD_CSI_D7__CSI_D7 0x0b 0x000 59 #define MX1_PAD_CSI_D7__GPIO1_11 0x0b 0x032 60 #define MX1_PAD_CSI_VSYNC__CSI_VSYNC 0x0c 0x000 61 #define MX1_PAD_CSI_VSYNC__GPIO1_12 0x0c 0x032 62 #define MX1_PAD_CSI_HSYNC__CSI_HSYNC 0x0d 0x000 63 #define MX1_PAD_CSI_HSYNC__GPIO1_13 0x0d 0x032 64 #define MX1_PAD_CSI_PIXCLK__CSI_PIXCLK 0x0e 0x000 65 #define MX1_PAD_CSI_PIXCLK__GPIO1_14 0x0e 0x032 66 #define MX1_PAD_I2C_SDA__I2C_SDA 0x0f 0x000 67 #define MX1_PAD_I2C_SDA__GPIO1_15 0x0f 0x032 68 #define MX1_PAD_I2C_SCL__I2C_SCL 0x10 0x004 69 #define MX1_PAD_I2C_SCL__GPIO1_16 0x10 0x032 70 #define MX1_PAD_DTACK__DTACK 0x11 0x000 71 #define MX1_PAD_DTACK__GPIO1_17 0x11 0x032 72 #define MX1_PAD_DTACK__SPI2_SS 0x11 0x002 73 #define MX1_PAD_DTACK__A25 0x11 0x016 74 #define MX1_PAD_BCLK__BCLK 0x12 0x004 75 #define MX1_PAD_BCLK__GPIO1_18 0x12 0x032 76 #define MX1_PAD_LBA__LBA 0x13 0x004 77 #define MX1_PAD_LBA__GPIO1_19 0x13 0x032 78 #define MX1_PAD_ECB__ECB 0x14 0x000 79 #define MX1_PAD_ECB__GPIO1_20 0x14 0x032 80 #define MX1_PAD_A0__A0 0x15 0x004 81 #define MX1_PAD_A0__GPIO1_21 0x15 0x032 82 #define MX1_PAD_CS4__CS4 0x16 0x004 83 #define MX1_PAD_CS4__GPIO1_22 0x16 0x032 84 #define MX1_PAD_CS5__CS5 0x17 0x004 85 #define MX1_PAD_CS5__GPIO1_23 0x17 0x032 86 #define MX1_PAD_A16__A16 0x18 0x004 87 #define MX1_PAD_A16__GPIO1_24 0x18 0x032 88 #define MX1_PAD_A17__A17 0x19 0x004 89 #define MX1_PAD_A17__GPIO1_25 0x19 0x032 90 #define MX1_PAD_A18__A18 0x1a 0x004 91 #define MX1_PAD_A18__GPIO1_26 0x1a 0x032 92 #define MX1_PAD_A19__A19 0x1b 0x004 93 #define MX1_PAD_A19__GPIO1_27 0x1b 0x032 94 #define MX1_PAD_A20__A20 0x1c 0x004 95 #define MX1_PAD_A20__GPIO1_28 0x1c 0x032 96 #define MX1_PAD_A21__A21 0x1d 0x004 97 #define MX1_PAD_A21__GPIO1_29 0x1d 0x032 98 #define MX1_PAD_A22__A22 0x1e 0x004 99 #define MX1_PAD_A22__GPIO1_30 0x1e 0x032 100 #define MX1_PAD_A23__A23 0x1f 0x004 101 #define MX1_PAD_A23__GPIO1_31 0x1f 0x032 102 #define MX1_PAD_SD_DAT0__SD_DAT0 0x28 0x000 103 #define MX1_PAD_SD_DAT0__MS_PI0 0x28 0x001 104 #define MX1_PAD_SD_DAT0__GPIO2_8 0x28 0x032 105 #define MX1_PAD_SD_DAT1__SD_DAT1 0x29 0x000 106 #define MX1_PAD_SD_DAT1__MS_PI1 0x29 0x001 107 #define MX1_PAD_SD_DAT1__GPIO2_9 0x29 0x032 108 #define MX1_PAD_SD_DAT2__SD_DAT2 0x2a 0x000 109 #define MX1_PAD_SD_DAT2__MS_SCLKI 0x2a 0x001 110 #define MX1_PAD_SD_DAT2__GPIO2_10 0x2a 0x032 111 #define MX1_PAD_SD_DAT3__SD_DAT3 0x2b 0x000 112 #define MX1_PAD_SD_DAT3__MS_SDIO 0x2b 0x001 113 #define MX1_PAD_SD_DAT3__GPIO2_11 0x2b 0x032 114 #define MX1_PAD_SD_SCLK__SD_SCLK 0x2c 0x004 115 #define MX1_PAD_SD_SCLK__MS_SCLKO 0x2c 0x005 116 #define MX1_PAD_SD_SCLK__GPIO2_12 0x2c 0x032 117 #define MX1_PAD_SD_CMD__SD_CMD 0x2d 0x000 118 #define MX1_PAD_SD_CMD__MS_BS 0x2d 0x005 119 #define MX1_PAD_SD_CMD__GPIO2_13 0x2d 0x032 120 #define MX1_PAD_SIM_SVEN__SIM_SVEN 0x2e 0x004 121 #define MX1_PAD_SIM_SVEN__SSI_RXFS 0x2e 0x001 122 #define MX1_PAD_SIM_SVEN__GPIO2_14 0x2e 0x032 123 #define MX1_PAD_SIM_PD__SIM_PD 0x2f 0x000 124 #define MX1_PAD_SIM_PD__SSI_RXCLK 0x2f 0x001 125 #define MX1_PAD_SIM_PD__GPIO2_15 0x2f 0x032 126 #define MX1_PAD_SIM_TX__SIM_TX 0x30 0x000 127 #define MX1_PAD_SIM_TX__SSI_RXDAT 0x30 0x001 128 #define MX1_PAD_SIM_TX__GPIO2_16 0x30 0x032 129 #define MX1_PAD_SIM_RX__SIM_RX 0x31 0x000 130 #define MX1_PAD_SIM_RX__SSI_TXDAT 0x31 0x005 131 #define MX1_PAD_SIM_RX__GPIO2_17 0x31 0x032 132 #define MX1_PAD_SIM_RST__SIM_RST 0x32 0x004 133 #define MX1_PAD_SIM_RST__SSI_TXFS 0x32 0x001 134 #define MX1_PAD_SIM_RST__GPIO2_18 0x32 0x032 135 #define MX1_PAD_SIM_CLK__SIM_CLK 0x33 0x004 136 #define MX1_PAD_SIM_CLK__SSI_TXCLK 0x33 0x001 137 #define MX1_PAD_SIM_CLK__GPIO2_19 0x33 0x032 138 #define MX1_PAD_USBD_AFE__USBD_AFE 0x34 0x004 139 #define MX1_PAD_USBD_AFE__GPIO2_20 0x34 0x032 140 #define MX1_PAD_USBD_OE__USBD_OE 0x35 0x004 141 #define MX1_PAD_USBD_OE__GPIO2_21 0x35 0x032 142 #define MX1_PAD_USBD_RCV__USBD_RCV 0x36 0x000 143 #define MX1_PAD_USBD_RCV__GPIO2_22 0x36 0x032 144 #define MX1_PAD_USBD_SUSPND__USBD_SUSPND 0x37 0x004 145 #define MX1_PAD_USBD_SUSPND__GPIO2_23 0x37 0x032 146 #define MX1_PAD_USBD_VP__USBD_VP 0x38 0x000 147 #define MX1_PAD_USBD_VP__GPIO2_24 0x38 0x032 148 #define MX1_PAD_USBD_VM__USBD_VM 0x39 0x000 149 #define MX1_PAD_USBD_VM__GPIO2_25 0x39 0x032 150 #define MX1_PAD_USBD_VPO__USBD_VPO 0x3a 0x004 151 #define MX1_PAD_USBD_VPO__GPIO2_26 0x3a 0x032 152 #define MX1_PAD_USBD_VMO__USBD_VMO 0x3b 0x004 153 #define MX1_PAD_USBD_VMO__GPIO2_27 0x3b 0x032 154 #define MX1_PAD_UART2_CTS__UART2_CTS 0x3c 0x004 155 #define MX1_PAD_UART2_CTS__GPIO2_28 0x3c 0x032 156 #define MX1_PAD_UART2_RTS__UART2_RTS 0x3d 0x000 157 #define MX1_PAD_UART2_RTS__GPIO2_29 0x3d 0x032 158 #define MX1_PAD_UART2_TXD__UART2_TXD 0x3e 0x004 159 #define MX1_PAD_UART2_TXD__GPIO2_30 0x3e 0x032 160 #define MX1_PAD_UART2_RXD__UART2_RXD 0x3f 0x000 161 #define MX1_PAD_UART2_RXD__GPIO2_31 0x3f 0x032 162 #define MX1_PAD_SSI_RXFS__SSI_RXFS 0x43 0x000 163 #define MX1_PAD_SSI_RXFS__GPIO3_3 0x43 0x032 164 #define MX1_PAD_SSI_RXCLK__SSI_RXCLK 0x44 0x000 165 #define MX1_PAD_SSI_RXCLK__GPIO3_4 0x44 0x032 166 #define MX1_PAD_SSI_RXDAT__SSI_RXDAT 0x45 0x000 167 #define MX1_PAD_SSI_RXDAT__GPIO3_5 0x45 0x032 168 #define MX1_PAD_SSI_TXDAT__SSI_TXDAT 0x46 0x004 169 #define MX1_PAD_SSI_TXDAT__GPIO3_6 0x46 0x032 170 #define MX1_PAD_SSI_TXFS__SSI_TXFS 0x47 0x000 171 #define MX1_PAD_SSI_TXFS__GPIO3_7 0x47 0x032 172 #define MX1_PAD_SSI_TXCLK__SSI_TXCLK 0x48 0x000 173 #define MX1_PAD_SSI_TXCLK__GPIO3_8 0x48 0x032 174 #define MX1_PAD_UART1_CTS__UART1_CTS 0x49 0x004 175 #define MX1_PAD_UART1_CTS__GPIO3_9 0x49 0x032 176 #define MX1_PAD_UART1_RTS__UART1_RTS 0x4a 0x000 177 #define MX1_PAD_UART1_RTS__GPIO3_10 0x4a 0x032 178 #define MX1_PAD_UART1_TXD__UART1_TXD 0x4b 0x004 179 #define MX1_PAD_UART1_TXD__GPIO3_11 0x4b 0x032 180 #define MX1_PAD_UART1_RXD__UART1_RXD 0x4c 0x000 181 #define MX1_PAD_UART1_RXD__GPIO3_12 0x4c 0x032 182 #define MX1_PAD_SPI1_RDY__SPI1_RDY 0x4d 0x000 183 #define MX1_PAD_SPI1_RDY__GPIO3_13 0x4d 0x032 184 #define MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x4e 0x004 185 #define MX1_PAD_SPI1_SCLK__GPIO3_14 0x4e 0x032 186 #define MX1_PAD_SPI1_SS__SPI1_SS 0x4f 0x000 187 #define MX1_PAD_SPI1_SS__GPIO3_15 0x4f 0x032 188 #define MX1_PAD_SPI1_MISO__SPI1_MISO 0x50 0x000 189 #define MX1_PAD_SPI1_MISO__GPIO3_16 0x50 0x032 190 #define MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x51 0x004 191 #define MX1_PAD_SPI1_MOSI__GPIO3_17 0x51 0x032 192 #define MX1_PAD_BT13__BT13 0x53 0x004 193 #define MX1_PAD_BT13__SSI2_RXCLK 0x53 0x001 194 #define MX1_PAD_BT13__GPIO3_19 0x53 0x032 195 #define MX1_PAD_BT12__BT12 0x54 0x004 196 #define MX1_PAD_BT12__SSI2_TXFS 0x54 0x001 197 #define MX1_PAD_BT12__GPIO3_20 0x54 0x032 198 #define MX1_PAD_BT11__BT11 0x55 0x004 199 #define MX1_PAD_BT11__SSI2_TXCLK 0x55 0x001 200 #define MX1_PAD_BT11__GPIO3_21 0x55 0x032 201 #define MX1_PAD_BT10__BT10 0x56 0x004 202 #define MX1_PAD_BT10__SSI2_TX 0x56 0x001 203 #define MX1_PAD_BT10__GPIO3_22 0x56 0x032 204 #define MX1_PAD_BT9__BT9 0x57 0x004 205 #define MX1_PAD_BT9__SSI2_RX 0x57 0x001 206 #define MX1_PAD_BT9__GPIO3_23 0x57 0x032 207 #define MX1_PAD_BT8__BT8 0x58 0x004 208 #define MX1_PAD_BT8__SSI2_RXFS 0x58 0x001 209 #define MX1_PAD_BT8__GPIO3_24 0x58 0x032 210 #define MX1_PAD_BT8__UART3_RI 0x58 0x016 211 #define MX1_PAD_BT7__BT7 0x59 0x004 212 #define MX1_PAD_BT7__GPIO3_25 0x59 0x032 213 #define MX1_PAD_BT7__UART3_DSR 0x59 0x016 214 #define MX1_PAD_BT6__BT6 0x5a 0x004 215 #define MX1_PAD_BT6__GPIO3_26 0x5a 0x032 216 #define MX1_PAD_BT6__SPI2_SS3 0x5a 0x016 217 #define MX1_PAD_BT6__UART3_DTR 0x5a 0x022 218 #define MX1_PAD_BT5__BT5 0x5b 0x000 219 #define MX1_PAD_BT5__GPIO3_27 0x5b 0x032 220 #define MX1_PAD_BT5__UART3_DCD 0x5b 0x016 221 #define MX1_PAD_BT4__BT4 0x5c 0x000 222 #define MX1_PAD_BT4__GPIO3_28 0x5c 0x032 223 #define MX1_PAD_BT4__UART3_CTS 0x5c 0x016 224 #define MX1_PAD_BT3__BT3 0x5d 0x000 225 #define MX1_PAD_BT3__GPIO3_29 0x5d 0x032 226 #define MX1_PAD_BT3__UART3_RTS 0x5d 0x022 227 #define MX1_PAD_BT2__BT2 0x5e 0x004 228 #define MX1_PAD_BT2__GPIO3_30 0x5e 0x032 229 #define MX1_PAD_BT2__UART3_TX 0x5e 0x016 230 #define MX1_PAD_BT1__BT1 0x5f 0x000 231 #define MX1_PAD_BT1__GPIO3_31 0x5f 0x032 232 #define MX1_PAD_BT1__UART3_RX 0x5f 0x022 233 #define MX1_PAD_LSCLK__LSCLK 0x66 0x004 234 #define MX1_PAD_LSCLK__GPIO4_6 0x66 0x032 235 #define MX1_PAD_REV__REV 0x67 0x004 236 #define MX1_PAD_REV__UART2_DTR 0x67 0x001 237 #define MX1_PAD_REV__GPIO4_7 0x67 0x032 238 #define MX1_PAD_REV__SPI2_CLK 0x67 0x006 239 #define MX1_PAD_CLS__CLS 0x68 0x004 240 #define MX1_PAD_CLS__UART2_DCD 0x68 0x005 241 #define MX1_PAD_CLS__GPIO4_8 0x68 0x032 242 #define MX1_PAD_CLS__SPI2_SS 0x68 0x002 243 #define MX1_PAD_PS__PS 0x69 0x004 244 #define MX1_PAD_PS__UART2_RI 0x69 0x005 245 #define MX1_PAD_PS__GPIO4_9 0x69 0x032 246 #define MX1_PAD_PS__SPI2_RXD 0x69 0x022 247 #define MX1_PAD_SPL_SPR__SPL_SPR 0x6a 0x004 248 #define MX1_PAD_SPL_SPR__UART2_DSR 0x6a 0x005 249 #define MX1_PAD_SPL_SPR__GPIO4_10 0x6a 0x032 250 #define MX1_PAD_SPL_SPR__SPI2_TXD 0x6a 0x006 251 #define MX1_PAD_CONTRAST__CONTRAST 0x6b 0x004 252 #define MX1_PAD_CONTRAST__GPIO4_11 0x6b 0x032 253 #define MX1_PAD_CONTRAST__SPI2_SS2 0x6b 0x012 254 #define MX1_PAD_ACD_OE__ACD_OE 0x6c 0x004 255 #define MX1_PAD_ACD_OE__GPIO4_12 0x6c 0x032 256 #define MX1_PAD_LP_HSYNC__LP_HSYNC 0x6d 0x004 257 #define MX1_PAD_LP_HSYNC__GPIO4_13 0x6d 0x032 258 #define MX1_PAD_FLM_VSYNC__FLM_VSYNC 0x6e 0x004 259 #define MX1_PAD_FLM_VSYNC__GPIO4_14 0x6e 0x032 260 #define MX1_PAD_LD0__LD0 0x6f 0x004 261 #define MX1_PAD_LD0__GPIO4_15 0x6f 0x032 262 #define MX1_PAD_LD1__LD1 0x70 0x004 263 #define MX1_PAD_LD1__GPIO4_16 0x70 0x032 264 #define MX1_PAD_LD2__LD2 0x71 0x004 265 #define MX1_PAD_LD2__GPIO4_17 0x71 0x032 266 #define MX1_PAD_LD3__LD3 0x72 0x004 267 #define MX1_PAD_LD3__GPIO4_18 0x72 0x032 268 #define MX1_PAD_LD4__LD4 0x73 0x004 269 #define MX1_PAD_LD4__GPIO4_19 0x73 0x032 270 #define MX1_PAD_LD5__LD5 0x74 0x004 271 #define MX1_PAD_LD5__GPIO4_20 0x74 0x032 272 #define MX1_PAD_LD6__LD6 0x75 0x004 273 #define MX1_PAD_LD6__GPIO4_21 0x75 0x032 274 #define MX1_PAD_LD7__LD7 0x76 0x004 275 #define MX1_PAD_LD7__GPIO4_22 0x76 0x032 276 #define MX1_PAD_LD8__LD8 0x77 0x004 277 #define MX1_PAD_LD8__GPIO4_23 0x77 0x032 278 #define MX1_PAD_LD9__LD9 0x78 0x004 279 #define MX1_PAD_LD9__GPIO4_24 0x78 0x032 280 #define MX1_PAD_LD10__LD10 0x79 0x004 281 #define MX1_PAD_LD10__GPIO4_25 0x79 0x032 282 #define MX1_PAD_LD11__LD11 0x7a 0x004 283 #define MX1_PAD_LD11__GPIO4_26 0x7a 0x032 284 #define MX1_PAD_LD12__LD12 0x7b 0x004 285 #define MX1_PAD_LD12__GPIO4_27 0x7b 0x032 286 #define MX1_PAD_LD13__LD13 0x7c 0x004 287 #define MX1_PAD_LD13__GPIO4_28 0x7c 0x032 288 #define MX1_PAD_LD14__LD14 0x7d 0x004 289 #define MX1_PAD_LD14__GPIO4_29 0x7d 0x032 290 #define MX1_PAD_LD15__LD15 0x7e 0x004 291 #define MX1_PAD_LD15__GPIO4_30 0x7e 0x032 292 #define MX1_PAD_TMR2OUT__TMR2OUT 0x7f 0x000 293 #define MX1_PAD_TMR2OUT__GPIO4_31 0x7f 0x032 294 #define MX1_PAD_TMR2OUT__SPI2_TXD 0x7f 0x006 295 296 #endif
Cache object: 6cceb7b9d5d61b246cf032e4b1667603
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]