The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/imx25-karo-tx25.dts

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    1 // SPDX-License-Identifier: GPL-2.0-or-later
    2 /*
    3  * Copyright 2012 Sascha Hauer, Pengutronix
    4  */
    5 
    6 /dts-v1/;
    7 #include "imx25.dtsi"
    8 
    9 / {
   10         model = "Ka-Ro TX25";
   11         compatible = "karo,imx25-tx25", "fsl,imx25";
   12 
   13         chosen {
   14                 stdout-path = &uart1;
   15         };
   16 
   17         regulators {
   18                 compatible = "simple-bus";
   19                 #address-cells = <1>;
   20                 #size-cells = <0>;
   21 
   22                 reg_fec_phy: regulator@0 {
   23                         compatible = "regulator-fixed";
   24                         reg = <0>;
   25                         regulator-name = "fec-phy";
   26                         regulator-min-microvolt = <3300000>;
   27                         regulator-max-microvolt = <3300000>;
   28                         gpio = <&gpio4 9 0>;
   29                         enable-active-high;
   30                 };
   31         };
   32 
   33         memory@80000000 {
   34                 device_type = "memory";
   35                 reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
   36         };
   37 };
   38 
   39 &iomuxc {
   40         pinctrl_uart1: uart1grp {
   41                 fsl,pins = <
   42                         MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
   43                         MX25_PAD_UART1_RXD__UART1_RXD 0x80000000
   44                         MX25_PAD_UART1_CTS__UART1_CTS 0x80000000
   45                         MX25_PAD_UART1_RTS__UART1_RTS 0x80000000
   46                 >;
   47         };
   48 
   49         pinctrl_fec: fecgrp {
   50                 fsl,pins = <
   51                         MX25_PAD_D11__GPIO_4_9          0x80000000 /* FEC PHY power on pin */
   52                         MX25_PAD_D13__GPIO_4_7          0x80000000 /* FEC reset */
   53                         MX25_PAD_FEC_MDC__FEC_MDC       0x80000000
   54                         MX25_PAD_FEC_MDIO__FEC_MDIO     0x80000000
   55                         MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000
   56                         MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000
   57                         MX25_PAD_FEC_TX_EN__FEC_TX_EN   0x80000000
   58                         MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000
   59                         MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000
   60                         MX25_PAD_FEC_RX_DV__FEC_RX_DV   0x80000000
   61                         MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000
   62                 >;
   63         };
   64 
   65         pinctrl_nfc: nfcgrp {
   66                 fsl,pins = <
   67                         MX25_PAD_NF_CE0__NF_CE0         0x80000000
   68                         MX25_PAD_NFWE_B__NFWE_B         0x80000000
   69                         MX25_PAD_NFRE_B__NFRE_B         0x80000000
   70                         MX25_PAD_NFALE__NFALE           0x80000000
   71                         MX25_PAD_NFCLE__NFCLE           0x80000000
   72                         MX25_PAD_NFWP_B__NFWP_B         0x80000000
   73                         MX25_PAD_NFRB__NFRB             0x80000000
   74                         MX25_PAD_D7__D7                 0x80000000
   75                         MX25_PAD_D6__D6                 0x80000000
   76                         MX25_PAD_D5__D5                 0x80000000
   77                         MX25_PAD_D4__D4                 0x80000000
   78                         MX25_PAD_D3__D3                 0x80000000
   79                         MX25_PAD_D2__D2                 0x80000000
   80                         MX25_PAD_D1__D1                 0x80000000
   81                         MX25_PAD_D0__D0                 0x80000000
   82                 >;
   83         };
   84 };
   85 
   86 &uart1 {
   87         pinctrl-names = "default";
   88         pinctrl-0 = <&pinctrl_uart1>;
   89         status = "okay";
   90 };
   91 
   92 &fec {
   93         pinctrl-names = "default";
   94         pinctrl-0 = <&pinctrl_fec>;
   95         phy-reset-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
   96         phy-mode = "rmii";
   97         phy-supply = <&reg_fec_phy>;
   98         status = "okay";
   99 };
  100 
  101 &nfc {
  102         pinctrl-names = "default";
  103         pinctrl-0 = <&pinctrl_nfc>;
  104         nand-on-flash-bbt;
  105         nand-ecc-mode = "hw";
  106         nand-bus-width = <8>;
  107         status = "okay";
  108 };

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