Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/imx25-pdk.dts
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1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Copyright 2013 Freescale Semiconductor, Inc. 4 5 /dts-v1/; 6 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/input/input.h> 8 #include "imx25.dtsi" 9 10 / { 11 model = "Freescale i.MX25 Product Development Kit"; 12 compatible = "fsl,imx25-pdk", "fsl,imx25"; 13 14 memory@80000000 { 15 device_type = "memory"; 16 reg = <0x80000000 0x4000000>; 17 }; 18 19 regulators { 20 compatible = "simple-bus"; 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 reg_fec_3v3: regulator@0 { 25 compatible = "regulator-fixed"; 26 reg = <0>; 27 regulator-name = "fec-3v3"; 28 regulator-min-microvolt = <3300000>; 29 regulator-max-microvolt = <3300000>; 30 gpio = <&gpio2 3 0>; 31 enable-active-high; 32 }; 33 34 reg_2p5v: regulator@1 { 35 compatible = "regulator-fixed"; 36 reg = <1>; 37 regulator-name = "2P5V"; 38 regulator-min-microvolt = <2500000>; 39 regulator-max-microvolt = <2500000>; 40 }; 41 42 reg_3p3v: regulator@2 { 43 compatible = "regulator-fixed"; 44 reg = <2>; 45 regulator-name = "3P3V"; 46 regulator-min-microvolt = <3300000>; 47 regulator-max-microvolt = <3300000>; 48 }; 49 50 reg_can_3v3: regulator@3 { 51 compatible = "regulator-fixed"; 52 reg = <3>; 53 regulator-name = "can-3v3"; 54 regulator-min-microvolt = <3300000>; 55 regulator-max-microvolt = <3300000>; 56 gpio = <&gpio4 6 0>; 57 }; 58 }; 59 60 sound { 61 compatible = "fsl,imx25-pdk-sgtl5000", 62 "fsl,imx-audio-sgtl5000"; 63 model = "imx25-pdk-sgtl5000"; 64 ssi-controller = <&ssi1>; 65 audio-codec = <&codec>; 66 audio-routing = 67 "MIC_IN", "Mic Jack", 68 "Mic Jack", "Mic Bias", 69 "Headphone Jack", "HP_OUT"; 70 mux-int-port = <1>; 71 mux-ext-port = <4>; 72 }; 73 74 wvga: display { 75 model = "CLAA057VC01CW"; 76 bits-per-pixel = <16>; 77 fsl,pcr = <0xfa208b80>; 78 bus-width = <18>; 79 display-timings { 80 native-mode = <&wvga_timings>; 81 wvga_timings: 640x480 { 82 hactive = <640>; 83 vactive = <480>; 84 hback-porch = <45>; 85 hfront-porch = <114>; 86 hsync-len = <1>; 87 vback-porch = <33>; 88 vfront-porch = <11>; 89 vsync-len = <1>; 90 clock-frequency = <25200000>; 91 }; 92 }; 93 }; 94 }; 95 96 &audmux { 97 pinctrl-names = "default"; 98 pinctrl-0 = <&pinctrl_audmux>; 99 status = "okay"; 100 }; 101 102 &can1 { 103 pinctrl-names = "default"; 104 pinctrl-0 = <&pinctrl_can1>; 105 xceiver-supply = <®_can_3v3>; 106 status = "okay"; 107 }; 108 109 &esdhc1 { 110 pinctrl-names = "default"; 111 pinctrl-0 = <&pinctrl_esdhc1>; 112 cd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 113 wp-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; 114 status = "okay"; 115 }; 116 117 &fec { 118 phy-mode = "rmii"; 119 pinctrl-names = "default"; 120 pinctrl-0 = <&pinctrl_fec>; 121 phy-supply = <®_fec_3v3>; 122 phy-reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; 123 status = "okay"; 124 }; 125 126 &i2c1 { 127 clock-frequency = <100000>; 128 pinctrl-names = "default"; 129 pinctrl-0 = <&pinctrl_i2c1>; 130 status = "okay"; 131 132 codec: sgtl5000@a { 133 compatible = "fsl,sgtl5000"; 134 reg = <0x0a>; 135 clocks = <&clks 129>; 136 VDDA-supply = <®_2p5v>; 137 VDDIO-supply = <®_3p3v>; 138 }; 139 }; 140 141 &iomuxc { 142 imx25-pdk { 143 pinctrl_audmux: audmuxgrp { 144 fsl,pins = < 145 MX25_PAD_RW__AUD4_TXFS 0xe0 146 MX25_PAD_OE__AUD4_TXC 0xe0 147 MX25_PAD_EB0__AUD4_TXD 0xe0 148 MX25_PAD_EB1__AUD4_RXD 0xe0 149 >; 150 }; 151 152 pinctrl_can1: can1grp { 153 fsl,pins = < 154 MX25_PAD_GPIO_A__CAN1_TX 0x0 155 MX25_PAD_GPIO_B__CAN1_RX 0x0 156 MX25_PAD_D14__GPIO_4_6 0x80000000 157 >; 158 }; 159 160 pinctrl_esdhc1: esdhc1grp { 161 fsl,pins = < 162 MX25_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 163 MX25_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 164 MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 165 MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 166 MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 167 MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000 168 MX25_PAD_A14__GPIO_2_0 0x80000000 169 MX25_PAD_A15__GPIO_2_1 0x80000000 170 >; 171 }; 172 173 pinctrl_fec: fecgrp { 174 fsl,pins = < 175 MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 176 MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0 177 MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 178 MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 179 MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 180 MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 181 MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 182 MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 183 MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 184 MX25_PAD_A17__GPIO_2_3 0x80000000 185 MX25_PAD_D12__GPIO_4_8 0x80000000 186 >; 187 }; 188 189 pinctrl_i2c1: i2c1grp { 190 fsl,pins = < 191 MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000 192 MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000 193 >; 194 }; 195 196 pinctrl_kpp: kppgrp { 197 fsl,pins = < 198 MX25_PAD_KPP_ROW0__KPP_ROW0 0x80000000 199 MX25_PAD_KPP_ROW1__KPP_ROW1 0x80000000 200 MX25_PAD_KPP_ROW2__KPP_ROW2 0x80000000 201 MX25_PAD_KPP_ROW3__KPP_ROW3 0x80000000 202 MX25_PAD_KPP_COL0__KPP_COL0 0x80000000 203 MX25_PAD_KPP_COL1__KPP_COL1 0x80000000 204 MX25_PAD_KPP_COL2__KPP_COL2 0x80000000 205 MX25_PAD_KPP_COL3__KPP_COL3 0x80000000 206 >; 207 }; 208 209 pinctrl_lcd: lcdgrp { 210 fsl,pins = < 211 MX25_PAD_LD0__LD0 0xe0 212 MX25_PAD_LD1__LD1 0xe0 213 MX25_PAD_LD2__LD2 0xe0 214 MX25_PAD_LD3__LD3 0xe0 215 MX25_PAD_LD4__LD4 0xe0 216 MX25_PAD_LD5__LD5 0xe0 217 MX25_PAD_LD6__LD6 0xe0 218 MX25_PAD_LD7__LD7 0xe0 219 MX25_PAD_LD8__LD8 0xe0 220 MX25_PAD_LD9__LD9 0xe0 221 MX25_PAD_LD10__LD10 0xe0 222 MX25_PAD_LD11__LD11 0xe0 223 MX25_PAD_LD12__LD12 0xe0 224 MX25_PAD_LD13__LD13 0xe0 225 MX25_PAD_LD14__LD14 0xe0 226 MX25_PAD_LD15__LD15 0xe0 227 MX25_PAD_GPIO_E__LD16 0xe0 228 MX25_PAD_GPIO_F__LD17 0xe0 229 MX25_PAD_HSYNC__HSYNC 0xe0 230 MX25_PAD_VSYNC__VSYNC 0xe0 231 MX25_PAD_LSCLK__LSCLK 0xe0 232 MX25_PAD_OE_ACD__OE_ACD 0xe0 233 MX25_PAD_CONTRAST__CONTRAST 0xe0 234 >; 235 }; 236 237 pinctrl_uart1: uart1grp { 238 fsl,pins = < 239 MX25_PAD_UART1_RTS__UART1_RTS 0xe0 240 MX25_PAD_UART1_CTS__UART1_CTS 0xe0 241 MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 242 MX25_PAD_UART1_RXD__UART1_RXD 0xc0 243 >; 244 }; 245 }; 246 }; 247 248 &lcdc { 249 display = <&wvga>; 250 fsl,lpccr = <0x00a903ff>; 251 fsl,lscr1 = <0x00120300>; 252 fsl,dmacr = <0x00020010>; 253 pinctrl-names = "default"; 254 pinctrl-0 = <&pinctrl_lcd>; 255 status = "okay"; 256 }; 257 258 &nfc { 259 nand-on-flash-bbt; 260 status = "okay"; 261 }; 262 263 &kpp { 264 pinctrl-names = "default"; 265 pinctrl-0 = <&pinctrl_kpp>; 266 linux,keymap = < 267 MATRIX_KEY(0x0, 0x0, KEY_UP) 268 MATRIX_KEY(0x0, 0x1, KEY_DOWN) 269 MATRIX_KEY(0x0, 0x2, KEY_VOLUMEDOWN) 270 MATRIX_KEY(0x0, 0x3, KEY_HOME) 271 MATRIX_KEY(0x1, 0x0, KEY_RIGHT) 272 MATRIX_KEY(0x1, 0x1, KEY_LEFT) 273 MATRIX_KEY(0x1, 0x2, KEY_ENTER) 274 MATRIX_KEY(0x1, 0x3, KEY_VOLUMEUP) 275 MATRIX_KEY(0x2, 0x0, KEY_F6) 276 MATRIX_KEY(0x2, 0x1, KEY_F8) 277 MATRIX_KEY(0x2, 0x2, KEY_F9) 278 MATRIX_KEY(0x2, 0x3, KEY_F10) 279 MATRIX_KEY(0x3, 0x0, KEY_F1) 280 MATRIX_KEY(0x3, 0x1, KEY_F2) 281 MATRIX_KEY(0x3, 0x2, KEY_F3) 282 MATRIX_KEY(0x3, 0x2, KEY_POWER) 283 >; 284 status = "okay"; 285 }; 286 287 &ssi1 { 288 status = "okay"; 289 }; 290 291 &tsc { 292 status = "okay"; 293 }; 294 295 &tscadc { 296 status = "okay"; 297 }; 298 299 &uart1 { 300 pinctrl-names = "default"; 301 pinctrl-0 = <&pinctrl_uart1>; 302 uart-has-rtscts; 303 status = "okay"; 304 }; 305 306 &usbhost1 { 307 status = "okay"; 308 }; 309 310 &usbotg { 311 external-vbus-divider; 312 status = "okay"; 313 };
Cache object: 485c2bdc61f69a73f3961929e0d03f77
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