Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/imx27-phytec-phycore-som.dtsi
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1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2012 Sascha Hauer, Pengutronix 4 */ 5 6 /dts-v1/; 7 #include "imx27.dtsi" 8 9 / { 10 model = "Phytec pcm038"; 11 compatible = "phytec,imx27-pcm038", "fsl,imx27"; 12 13 memory@a0000000 { 14 device_type = "memory"; 15 reg = <0xa0000000 0x08000000>; 16 }; 17 18 regulators { 19 compatible = "simple-bus"; 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 reg_3v3: regulator@0 { 24 compatible = "regulator-fixed"; 25 reg = <0>; 26 regulator-name = "3V3"; 27 regulator-min-microvolt = <3300000>; 28 regulator-max-microvolt = <3300000>; 29 }; 30 31 reg_5v0: regulator@1 { 32 compatible = "regulator-fixed"; 33 reg = <1>; 34 regulator-name = "5V0"; 35 regulator-min-microvolt = <5000000>; 36 regulator-max-microvolt = <5000000>; 37 }; 38 }; 39 40 usbphy { 41 compatible = "simple-bus"; 42 #address-cells = <1>; 43 #size-cells = <0>; 44 45 usbphy0: usbphy@0 { 46 compatible = "usb-nop-xceiv"; 47 reg = <0>; 48 vcc-supply = <&sw3_reg>; 49 clocks = <&clks IMX27_CLK_DUMMY>; 50 clock-names = "main_clk"; 51 #phy-cells = <0>; 52 }; 53 }; 54 }; 55 56 &audmux { 57 status = "okay"; 58 59 /* SSI0 <=> PINS_4 (MC13783 Audio) */ 60 ssi0 { 61 fsl,audmux-port = <0>; 62 fsl,port-config = <0xcb205000>; 63 }; 64 65 pins4 { 66 fsl,audmux-port = <2>; 67 fsl,port-config = <0x00001000>; 68 }; 69 }; 70 71 &cspi1 { 72 pinctrl-names = "default"; 73 pinctrl-0 = <&pinctrl_cspi1>; 74 cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; 75 status = "okay"; 76 77 pmic: mc13783@0 { 78 compatible = "fsl,mc13783"; 79 pinctrl-names = "default"; 80 pinctrl-0 = <&pinctrl_pmic>; 81 reg = <0>; 82 spi-cs-high; 83 spi-max-frequency = <20000000>; 84 interrupt-parent = <&gpio2>; 85 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; 86 fsl,mc13xxx-uses-adc; 87 fsl,mc13xxx-uses-rtc; 88 89 pmicleds: leds { 90 #address-cells = <1>; 91 #size-cells = <0>; 92 led-control = <0x001 0x000 0x000 0x000 0x000 0x000>; 93 }; 94 95 regulators { 96 /* SW1A and SW1B joined operation */ 97 sw1_reg: sw1a { 98 regulator-min-microvolt = <1200000>; 99 regulator-max-microvolt = <1520000>; 100 regulator-always-on; 101 regulator-boot-on; 102 }; 103 104 /* SW2A and SW2B joined operation */ 105 sw2_reg: sw2a { 106 regulator-min-microvolt = <1800000>; 107 regulator-max-microvolt = <1800000>; 108 regulator-always-on; 109 regulator-boot-on; 110 }; 111 112 sw3_reg: sw3 { 113 regulator-min-microvolt = <5000000>; 114 regulator-max-microvolt = <5000000>; 115 regulator-always-on; 116 regulator-boot-on; 117 }; 118 119 vaudio_reg: vaudio { 120 regulator-always-on; 121 regulator-boot-on; 122 }; 123 124 violo_reg: violo { 125 regulator-min-microvolt = <1800000>; 126 regulator-max-microvolt = <1800000>; 127 regulator-always-on; 128 regulator-boot-on; 129 }; 130 131 viohi_reg: viohi { 132 regulator-always-on; 133 regulator-boot-on; 134 }; 135 136 vgen_reg: vgen { 137 regulator-min-microvolt = <1500000>; 138 regulator-max-microvolt = <1500000>; 139 regulator-always-on; 140 regulator-boot-on; 141 }; 142 143 vcam_reg: vcam { 144 regulator-min-microvolt = <2800000>; 145 regulator-max-microvolt = <2800000>; 146 }; 147 148 vrf1_reg: vrf1 { 149 regulator-min-microvolt = <2775000>; 150 regulator-max-microvolt = <2775000>; 151 regulator-always-on; 152 regulator-boot-on; 153 }; 154 155 vrf2_reg: vrf2 { 156 regulator-min-microvolt = <2775000>; 157 regulator-max-microvolt = <2775000>; 158 regulator-always-on; 159 regulator-boot-on; 160 }; 161 162 vmmc1_reg: vmmc1 { 163 regulator-min-microvolt = <1600000>; 164 regulator-max-microvolt = <3000000>; 165 }; 166 167 gpo1_reg: gpo1 { }; 168 169 pwgt1spi_reg: pwgt1spi { 170 regulator-always-on; 171 }; 172 }; 173 }; 174 }; 175 176 &fec { 177 phy-mode = "mii"; 178 phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_LOW>; 179 phy-supply = <®_3v3>; 180 pinctrl-names = "default"; 181 pinctrl-0 = <&pinctrl_fec1>; 182 status = "okay"; 183 }; 184 185 &i2c2 { 186 clock-frequency = <400000>; 187 pinctrl-names = "default"; 188 pinctrl-0 = <&pinctrl_i2c2>; 189 status = "okay"; 190 191 at24@52 { 192 compatible = "atmel,24c32"; 193 pagesize = <32>; 194 reg = <0x52>; 195 }; 196 197 pcf8563@51 { 198 compatible = "nxp,pcf8563"; 199 reg = <0x51>; 200 }; 201 202 lm75@4a { 203 compatible = "national,lm75"; 204 reg = <0x4a>; 205 }; 206 }; 207 208 &iomuxc { 209 imx27_phycore_som { 210 pinctrl_cspi1: cspi1grp { 211 fsl,pins = < 212 MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 213 MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 214 MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 215 MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* SPI1 CS0 */ 216 >; 217 }; 218 219 pinctrl_fec1: fec1grp { 220 fsl,pins = < 221 MX27_PAD_SD3_CMD__FEC_TXD0 0x0 222 MX27_PAD_SD3_CLK__FEC_TXD1 0x0 223 MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 224 MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 225 MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 226 MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 227 MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 228 MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 229 MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 230 MX27_PAD_ATA_DATA7__FEC_MDC 0x0 231 MX27_PAD_ATA_DATA8__FEC_CRS 0x0 232 MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 233 MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 234 MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 235 MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 236 MX27_PAD_ATA_DATA13__FEC_COL 0x0 237 MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 238 MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 239 MX27_PAD_SSI3_TXDAT__GPIO3_30 0x0 /* FEC RST */ 240 >; 241 }; 242 243 pinctrl_i2c2: i2c2grp { 244 fsl,pins = < 245 MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 246 MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 247 >; 248 }; 249 250 pinctrl_nfc: nfcgrp { 251 fsl,pins = < 252 MX27_PAD_NFRB__NFRB 0x0 253 MX27_PAD_NFCLE__NFCLE 0x0 254 MX27_PAD_NFWP_B__NFWP_B 0x0 255 MX27_PAD_NFCE_B__NFCE_B 0x0 256 MX27_PAD_NFALE__NFALE 0x0 257 MX27_PAD_NFRE_B__NFRE_B 0x0 258 MX27_PAD_NFWE_B__NFWE_B 0x0 259 >; 260 }; 261 262 pinctrl_pmic: pmicgrp { 263 fsl,pins = < 264 MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */ 265 >; 266 }; 267 268 pinctrl_ssi1: ssi1grp { 269 fsl,pins = < 270 MX27_PAD_SSI1_FS__SSI1_FS 0x0 271 MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x0 272 MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x0 273 MX27_PAD_SSI1_CLK__SSI1_CLK 0x0 274 >; 275 }; 276 277 pinctrl_usbotg: usbotggrp { 278 fsl,pins = < 279 MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 280 MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 281 MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 282 MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 283 MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 284 MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 285 MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 286 MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 287 MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 288 MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 289 MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 290 MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 291 >; 292 }; 293 }; 294 }; 295 296 &nfc { 297 pinctrl-names = "default"; 298 pinctrl-0 = <&pinctrl_nfc>; 299 nand-bus-width = <8>; 300 nand-ecc-mode = "hw"; 301 nand-on-flash-bbt; 302 status = "okay"; 303 }; 304 305 &ssi1 { 306 pinctrl-names = "default"; 307 pinctrl-0 = <&pinctrl_ssi1>; 308 status = "okay"; 309 }; 310 311 &usbotg { 312 pinctrl-names = "default"; 313 pinctrl-0 = <&pinctrl_usbotg>; 314 dr_mode = "otg"; 315 phy_type = "ulpi"; 316 fsl,usbphy = <&usbphy0>; 317 vbus-supply = <&sw3_reg>; 318 disable-over-current; 319 status = "okay"; 320 }; 321 322 &weim { 323 status = "okay"; 324 325 nor: nor@0,0 { 326 compatible = "cfi-flash"; 327 reg = <0 0x00000000 0x02000000>; 328 bank-width = <2>; 329 linux,mtd-name = "physmap-flash.0"; 330 fsl,weim-cs-timing = <0x22c2cf00 0x75000d01 0x00000900>; 331 #address-cells = <1>; 332 #size-cells = <1>; 333 }; 334 335 sram: sram@1,0 { 336 compatible = "mtd-ram"; 337 reg = <1 0x00000000 0x00800000>; 338 bank-width = <2>; 339 linux,mtd-name = "mtd-ram.0"; 340 fsl,weim-cs-timing = <0x0000d843 0x22252521 0x22220a00>; 341 #address-cells = <1>; 342 #size-cells = <1>; 343 }; 344 };
Cache object: 2fe0777e98c15faefa108dddadbd8046
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