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sys/contrib/device-tree/src/arm/imx51-zii-rdu1.dts
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1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Copyright (C) 2017 Zodiac Inflight Innovations 4 */ 5 6 /dts-v1/; 7 #include "imx51.dtsi" 8 #include <dt-bindings/sound/fsl-imx-audmux.h> 9 10 / { 11 model = "ZII RDU1 Board"; 12 compatible = "zii,imx51-rdu1", "fsl,imx51"; 13 14 chosen { 15 stdout-path = &uart1; 16 }; 17 18 /* Will be filled by the bootloader */ 19 memory@90000000 { 20 device_type = "memory"; 21 reg = <0x90000000 0>; 22 }; 23 24 aliases { 25 mdio-gpio0 = &mdio_gpio; 26 rtc0 = &ds1341; 27 }; 28 29 clk_26M_osc: 26M_osc { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <26000000>; 33 }; 34 35 clk_26M_osc_gate: 26M_gate { 36 compatible = "gpio-gate-clock"; 37 pinctrl-names = "default"; 38 pinctrl-0 = <&pinctrl_clk26mhz>; 39 clocks = <&clk_26M_osc>; 40 #clock-cells = <0>; 41 enable-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; 42 }; 43 44 clk_26M_usb: usbhost_gate { 45 compatible = "gpio-gate-clock"; 46 pinctrl-names = "default"; 47 pinctrl-0 = <&pinctrl_usbgate26mhz>; 48 clocks = <&clk_26M_osc_gate>; 49 #clock-cells = <0>; 50 enable-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; 51 }; 52 53 clk_26M_snd: snd_gate { 54 compatible = "gpio-gate-clock"; 55 pinctrl-names = "default"; 56 pinctrl-0 = <&pinctrl_sndgate26mhz>; 57 clocks = <&clk_26M_osc_gate>; 58 #clock-cells = <0>; 59 enable-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; 60 }; 61 62 reg_5p0v_main: regulator-5p0v-main { 63 compatible = "regulator-fixed"; 64 regulator-name = "5V_MAIN"; 65 regulator-min-microvolt = <5000000>; 66 regulator-max-microvolt = <5000000>; 67 regulator-always-on; 68 }; 69 70 reg_3p3v: regulator-3p3v { 71 compatible = "regulator-fixed"; 72 regulator-name = "3.3V"; 73 regulator-min-microvolt = <3300000>; 74 regulator-max-microvolt = <3300000>; 75 regulator-always-on; 76 }; 77 78 disp0 { 79 compatible = "fsl,imx-parallel-display"; 80 pinctrl-names = "default"; 81 pinctrl-0 = <&pinctrl_ipu_disp1>; 82 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 port@0 { 87 reg = <0>; 88 89 display_in: endpoint { 90 remote-endpoint = <&ipu_di0_disp1>; 91 }; 92 }; 93 94 port@1 { 95 reg = <1>; 96 97 display_out: endpoint { 98 remote-endpoint = <&panel_in>; 99 }; 100 }; 101 }; 102 103 panel { 104 /* no compatible here, bootloader will patch in correct one */ 105 pinctrl-names = "default"; 106 pinctrl-0 = <&pinctrl_panel>; 107 power-supply = <®_3p3v>; 108 enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; 109 status = "disabled"; 110 111 port { 112 panel_in: endpoint { 113 remote-endpoint = <&display_out>; 114 }; 115 }; 116 }; 117 118 i2c_gpio: i2c-gpio { 119 compatible = "i2c-gpio"; 120 pinctrl-names = "default"; 121 pinctrl-0 = <&pinctrl_swi2c>; 122 gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>, /* sda */ 123 <&gpio3 4 GPIO_ACTIVE_HIGH>; /* scl */ 124 i2c-gpio,delay-us = <50>; 125 status = "okay"; 126 127 #address-cells = <1>; 128 #size-cells = <0>; 129 130 sgtl5000: codec@a { 131 compatible = "fsl,sgtl5000"; 132 reg = <0x0a>; 133 clocks = <&clk_26M_snd>; 134 VDDA-supply = <&vdig_reg>; 135 VDDIO-supply = <&vvideo_reg>; 136 #sound-dai-cells = <0>; 137 }; 138 }; 139 140 spi_gpio: spi-gpio { 141 compatible = "spi-gpio"; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&pinctrl_gpiospi0>; 146 status = "okay"; 147 148 gpio-sck = <&gpio4 15 GPIO_ACTIVE_HIGH>; 149 gpio-mosi = <&gpio4 12 GPIO_ACTIVE_HIGH>; 150 gpio-miso = <&gpio4 11 GPIO_ACTIVE_HIGH>; 151 num-chipselects = <1>; 152 cs-gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; 153 154 eeprom@0 { 155 compatible = "eeprom-93xx46"; 156 reg = <0>; 157 spi-max-frequency = <1000000>; 158 spi-cs-high; 159 data-size = <8>; 160 }; 161 }; 162 163 mdio_gpio: mdio-gpio { 164 compatible = "virtual,mdio-gpio"; 165 pinctrl-names = "default"; 166 pinctrl-0 = <&pinctrl_swmdio>; 167 gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>, /* mdc */ 168 <&gpio3 25 GPIO_ACTIVE_HIGH>; /* mdio */ 169 170 #address-cells = <1>; 171 #size-cells = <0>; 172 173 switch@0 { 174 compatible = "marvell,mv88e6085"; 175 reg = <0>; 176 dsa,member = <0 0>; 177 178 ports { 179 #address-cells = <1>; 180 #size-cells = <0>; 181 182 port@0 { 183 reg = <0>; 184 label = "cpu"; 185 ethernet = <&fec>; 186 187 fixed-link { 188 speed = <100>; 189 full-duplex; 190 }; 191 }; 192 193 port@1 { 194 reg = <1>; 195 label = "netaux"; 196 }; 197 198 port@3 { 199 reg = <3>; 200 label = "netright"; 201 }; 202 203 port@4 { 204 reg = <4>; 205 label = "netleft"; 206 }; 207 }; 208 }; 209 }; 210 211 sound { 212 compatible = "simple-audio-card"; 213 simple-audio-card,name = "Front"; 214 simple-audio-card,format = "i2s"; 215 simple-audio-card,bitclock-master = <&sound_codec>; 216 simple-audio-card,frame-master = <&sound_codec>; 217 simple-audio-card,widgets = 218 "Headphone", "Headphone Jack"; 219 simple-audio-card,routing = 220 "Headphone Jack", "TPA6130A2 HPLEFT", 221 "Headphone Jack", "TPA6130A2 HPRIGHT"; 222 simple-audio-card,aux-devs = <&hpa1>; 223 224 sound_cpu: simple-audio-card,cpu { 225 sound-dai = <&ssi2>; 226 }; 227 228 sound_codec: simple-audio-card,codec { 229 sound-dai = <&sgtl5000>; 230 clocks = <&clk_26M_snd>; 231 }; 232 }; 233 234 usbh1phy: usbphy1 { 235 compatible = "usb-nop-xceiv"; 236 pinctrl-names = "default"; 237 pinctrl-0 = <&pinctrl_usbh1phy>; 238 clocks = <&clk_26M_usb>; 239 clock-names = "main_clk"; 240 reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; 241 vcc-supply = <&vusb_reg>; 242 #phy-cells = <0>; 243 }; 244 245 usbh2phy: usbphy2 { 246 compatible = "usb-nop-xceiv"; 247 pinctrl-names = "default"; 248 pinctrl-0 = <&pinctrl_usbh2phy>; 249 clocks = <&clk_26M_usb>; 250 clock-names = "main_clk"; 251 reset-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; 252 vcc-supply = <&vusb_reg>; 253 #phy-cells = <0>; 254 }; 255 }; 256 257 &audmux { 258 pinctrl-names = "default"; 259 pinctrl-0 = <&pinctrl_audmux>; 260 status = "okay"; 261 262 ssi2 { 263 fsl,audmux-port = <1>; 264 fsl,port-config = < 265 (IMX_AUDMUX_V2_PTCR_SYN | 266 IMX_AUDMUX_V2_PTCR_TFSEL(2) | 267 IMX_AUDMUX_V2_PTCR_TCSEL(2) | 268 IMX_AUDMUX_V2_PTCR_TFSDIR | 269 IMX_AUDMUX_V2_PTCR_TCLKDIR) 270 IMX_AUDMUX_V2_PDCR_RXDSEL(2) 271 >; 272 }; 273 274 aud3 { 275 fsl,audmux-port = <2>; 276 fsl,port-config = < 277 IMX_AUDMUX_V2_PTCR_SYN 278 IMX_AUDMUX_V2_PDCR_RXDSEL(1) 279 >; 280 }; 281 }; 282 283 &cpu { 284 cpu-supply = <&sw1_reg>; 285 }; 286 287 &ecspi1 { 288 pinctrl-names = "default"; 289 pinctrl-0 = <&pinctrl_ecspi1>; 290 cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, 291 <&gpio4 25 GPIO_ACTIVE_LOW>; 292 status = "okay"; 293 294 pmic@0 { 295 compatible = "fsl,mc13892"; 296 pinctrl-names = "default"; 297 pinctrl-0 = <&pinctrl_pmic>; 298 spi-max-frequency = <6000000>; 299 spi-cs-high; 300 reg = <0>; 301 interrupt-parent = <&gpio1>; 302 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 303 fsl,mc13xxx-uses-adc; 304 305 regulators { 306 sw1_reg: sw1 { 307 regulator-min-microvolt = <600000>; 308 regulator-max-microvolt = <1375000>; 309 regulator-boot-on; 310 regulator-always-on; 311 }; 312 313 sw2_reg: sw2 { 314 regulator-min-microvolt = <900000>; 315 regulator-max-microvolt = <1850000>; 316 regulator-boot-on; 317 regulator-always-on; 318 }; 319 320 sw3_reg: sw3 { 321 regulator-min-microvolt = <1100000>; 322 regulator-max-microvolt = <1850000>; 323 regulator-boot-on; 324 regulator-always-on; 325 }; 326 327 sw4_reg: sw4 { 328 regulator-min-microvolt = <1100000>; 329 regulator-max-microvolt = <1850000>; 330 regulator-boot-on; 331 regulator-always-on; 332 }; 333 334 vpll_reg: vpll { 335 regulator-min-microvolt = <1050000>; 336 regulator-max-microvolt = <1800000>; 337 regulator-boot-on; 338 regulator-always-on; 339 }; 340 341 vdig_reg: vdig { 342 regulator-min-microvolt = <1650000>; 343 regulator-max-microvolt = <1650000>; 344 regulator-boot-on; 345 }; 346 347 vsd_reg: vsd { 348 regulator-min-microvolt = <1800000>; 349 regulator-max-microvolt = <3150000>; 350 }; 351 352 vusb_reg: vusb { 353 regulator-always-on; 354 }; 355 356 vusb2_reg: vusb2 { 357 regulator-min-microvolt = <2400000>; 358 regulator-max-microvolt = <2775000>; 359 regulator-boot-on; 360 regulator-always-on; 361 }; 362 363 vvideo_reg: vvideo { 364 regulator-min-microvolt = <2775000>; 365 regulator-max-microvolt = <2775000>; 366 }; 367 368 vaudio_reg: vaudio { 369 regulator-min-microvolt = <2300000>; 370 regulator-max-microvolt = <3000000>; 371 }; 372 373 vcam_reg: vcam { 374 regulator-min-microvolt = <2500000>; 375 regulator-max-microvolt = <3000000>; 376 }; 377 378 vgen1_reg: vgen1 { 379 regulator-min-microvolt = <1200000>; 380 regulator-max-microvolt = <1200000>; 381 }; 382 383 vgen2_reg: vgen2 { 384 regulator-min-microvolt = <1200000>; 385 regulator-max-microvolt = <3150000>; 386 regulator-always-on; 387 }; 388 389 vgen3_reg: vgen3 { 390 regulator-min-microvolt = <1800000>; 391 regulator-max-microvolt = <2900000>; 392 regulator-always-on; 393 }; 394 }; 395 396 leds { 397 #address-cells = <1>; 398 #size-cells = <0>; 399 led-control = <0x0 0x0 0x3f83f8 0x0>; 400 401 sysled0@3 { 402 reg = <3>; 403 label = "system:green:status"; 404 linux,default-trigger = "default-on"; 405 }; 406 407 sysled1@4 { 408 reg = <4>; 409 label = "system:green:act"; 410 linux,default-trigger = "heartbeat"; 411 }; 412 }; 413 }; 414 415 flash@1 { 416 #address-cells = <1>; 417 #size-cells = <1>; 418 compatible = "atmel,at45db642d", "atmel,at45", "atmel,dataflash"; 419 spi-max-frequency = <25000000>; 420 reg = <1>; 421 }; 422 }; 423 424 &esdhc1 { 425 pinctrl-names = "default"; 426 pinctrl-0 = <&pinctrl_esdhc1>; 427 bus-width = <4>; 428 no-1-8-v; 429 non-removable; 430 no-sdio; 431 no-sd; 432 status = "okay"; 433 }; 434 435 &fec { 436 pinctrl-names = "default"; 437 pinctrl-0 = <&pinctrl_fec>; 438 phy-mode = "mii"; 439 phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; 440 phy-supply = <&vgen3_reg>; 441 status = "okay"; 442 }; 443 444 &gpio1 { 445 gpio-line-names = "", "", "", "", 446 "", "", "", "", 447 "", "hp-amp-shutdown-b", "", "", 448 "", "", "", "", 449 "", "", "", "", 450 "", "", "", "", 451 "", "", "", "", 452 "", "", "", ""; 453 454 unused-sd3-wp-hog { 455 /* 456 * See pinctrl_esdhc1 below for more details on this 457 */ 458 gpio-hog; 459 gpios = <1 GPIO_ACTIVE_HIGH>; 460 output-high; 461 }; 462 }; 463 464 &i2c2 { 465 pinctrl-names = "default"; 466 pinctrl-0 = <&pinctrl_i2c2>; 467 status = "okay"; 468 469 hpa1: amp@60 { 470 compatible = "ti,tpa6130a2"; 471 reg = <0x60>; 472 Vdd-supply = <®_3p3v>; 473 sound-name-prefix = "TPA6130A2"; 474 }; 475 476 ds1341: rtc@68 { 477 compatible = "dallas,ds1341"; 478 reg = <0x68>; 479 }; 480 481 /* touch nodes default disabled, bootloader will enable the right one */ 482 483 touchscreen@4b { 484 compatible = "atmel,maxtouch"; 485 reg = <0x4b>; 486 pinctrl-names = "default"; 487 pinctrl-0 = <&pinctrl_ts>; 488 interrupt-parent = <&gpio3>; 489 interrupts = <12 IRQ_TYPE_LEVEL_LOW>; 490 status = "disabled"; 491 }; 492 493 touchscreen@4c { 494 compatible = "atmel,maxtouch"; 495 reg = <0x4c>; 496 pinctrl-names = "default"; 497 pinctrl-0 = <&pinctrl_ts>; 498 interrupt-parent = <&gpio3>; 499 interrupts = <12 IRQ_TYPE_LEVEL_LOW>; 500 status = "disabled"; 501 }; 502 503 touchscreen@20 { 504 compatible = "syna,rmi4-i2c"; 505 reg = <0x20>; 506 pinctrl-names = "default"; 507 pinctrl-0 = <&pinctrl_ts>; 508 interrupt-parent = <&gpio3>; 509 interrupts = <12 IRQ_TYPE_LEVEL_LOW>; 510 status = "disabled"; 511 512 #address-cells = <1>; 513 #size-cells = <0>; 514 515 rmi4-f01@1 { 516 reg = <0x1>; 517 syna,nosleep-mode = <2>; 518 }; 519 520 rmi4-f11@11 { 521 reg = <0x11>; 522 touchscreen-inverted-x; 523 touchscreen-swapped-x-y; 524 syna,sensor-type = <1>; 525 }; 526 }; 527 528 }; 529 530 &ipu_di0_disp1 { 531 remote-endpoint = <&display_in>; 532 }; 533 534 &pmu { 535 secure-reg-access; 536 }; 537 538 &ssi2 { 539 status = "okay"; 540 }; 541 542 &uart1 { 543 pinctrl-names = "default"; 544 pinctrl-0 = <&pinctrl_uart1>; 545 status = "okay"; 546 }; 547 548 &uart2 { 549 pinctrl-names = "default"; 550 pinctrl-0 = <&pinctrl_uart2>; 551 status = "okay"; 552 }; 553 554 &uart3 { 555 pinctrl-names = "default"; 556 pinctrl-0 = <&pinctrl_uart3>; 557 status = "okay"; 558 559 rave-sp { 560 compatible = "zii,rave-sp-rdu1"; 561 current-speed = <38400>; 562 #address-cells = <1>; 563 #size-cells = <1>; 564 565 watchdog { 566 compatible = "zii,rave-sp-watchdog"; 567 }; 568 569 backlight { 570 compatible = "zii,rave-sp-backlight"; 571 }; 572 573 pwrbutton { 574 compatible = "zii,rave-sp-pwrbutton"; 575 }; 576 577 eeprom@a3 { 578 compatible = "zii,rave-sp-eeprom"; 579 reg = <0xa3 0x2000>; 580 #address-cells = <1>; 581 #size-cells = <1>; 582 zii,eeprom-name = "dds-eeprom"; 583 }; 584 585 eeprom@a4 { 586 compatible = "zii,rave-sp-eeprom"; 587 reg = <0xa4 0x4000>; 588 #address-cells = <1>; 589 #size-cells = <1>; 590 zii,eeprom-name = "main-eeprom"; 591 }; 592 593 eeprom@ae { 594 compatible = "zii,rave-sp-eeprom"; 595 reg = <0xae 0x200>; 596 zii,eeprom-name = "switch-eeprom"; 597 /* 598 * Not all RDU1s have this functionality, so we 599 * rely on the bootloader to enable this 600 */ 601 status = "disabled"; 602 }; 603 }; 604 }; 605 606 &usbh1 { 607 pinctrl-names = "default"; 608 pinctrl-0 = <&pinctrl_usbh1>; 609 dr_mode = "host"; 610 phy_type = "ulpi"; 611 fsl,usbphy = <&usbh1phy>; 612 disable-over-current; 613 maximum-speed = "full-speed"; 614 vbus-supply = <®_5p0v_main>; 615 status = "okay"; 616 }; 617 618 &usbh2 { 619 pinctrl-names = "default"; 620 pinctrl-0 = <&pinctrl_usbh2>; 621 dr_mode = "host"; 622 phy_type = "ulpi"; 623 fsl,usbphy = <&usbh2phy>; 624 disable-over-current; 625 vbus-supply = <®_5p0v_main>; 626 status = "okay"; 627 }; 628 629 &usbphy0 { 630 vcc-supply = <&vusb_reg>; 631 }; 632 633 &usbotg { 634 dr_mode = "host"; 635 disable-over-current; 636 phy_type = "utmi_wide"; 637 vbus-supply = <®_5p0v_main>; 638 status = "okay"; 639 }; 640 641 &wdog1 { 642 status = "disabled"; 643 }; 644 645 &iomuxc { 646 pinctrl-names = "default"; 647 pinctrl-0 = <&pinctrl_hog>; 648 649 pinctrl_hog: hoggrp { 650 fsl,pins = < 651 MX51_PAD_GPIO1_9__GPIO1_9 0x5e 652 >; 653 }; 654 655 pinctrl_audmux: audmuxgrp { 656 fsl,pins = < 657 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0xa5 658 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x85 659 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0xa5 660 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x85 661 >; 662 }; 663 664 pinctrl_clk26mhz: clk26mhzgrp { 665 fsl,pins = < 666 MX51_PAD_DI1_PIN12__GPIO3_1 0x85 667 >; 668 }; 669 670 pinctrl_ecspi1: ecspi1grp { 671 fsl,pins = < 672 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 673 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 674 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 675 MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 676 MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 677 >; 678 }; 679 680 pinctrl_esdhc1: esdhc1grp { 681 fsl,pins = < 682 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 683 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 684 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 685 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 686 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 687 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 688 /* 689 * GPIO1_1 is not directly used by eSDHC1 in 690 * any capacity, but earlier versions of RDU1 691 * used that pin as WP GPIO for eSDHC3 and 692 * because of that that pad has an external 693 * pull-up resistor. This is problematic 694 * because out of reset the pad is configured 695 * as ALT0 which serves as SD1_WP, which, when 696 * pulled high by and external pull-up, will 697 * inhibit execution of any write request to 698 * attached eMMC device. 699 * 700 * To avoid this problem we configure the pad 701 * to ALT1/GPIO and avoid driving SD1_WP 702 * signal high. 703 */ 704 MX51_PAD_GPIO1_1__GPIO1_1 0x0000 705 >; 706 }; 707 708 pinctrl_fec: fecgrp { 709 fsl,pins = < 710 MX51_PAD_EIM_EB2__FEC_MDIO 0x1f5 711 MX51_PAD_NANDF_D9__FEC_RDATA0 0x2180 712 MX51_PAD_EIM_EB3__FEC_RDATA1 0x180 713 MX51_PAD_EIM_CS2__FEC_RDATA2 0x180 714 MX51_PAD_EIM_CS3__FEC_RDATA3 0x180 715 MX51_PAD_EIM_CS4__FEC_RX_ER 0x180 716 MX51_PAD_NANDF_D11__FEC_RX_DV 0x2084 717 MX51_PAD_EIM_CS5__FEC_CRS 0x180 718 MX51_PAD_NANDF_RB2__FEC_COL 0x2180 719 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x2180 720 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x2004 721 MX51_PAD_NANDF_CS3__FEC_MDC 0x2004 722 MX51_PAD_NANDF_D8__FEC_TDATA0 0x2180 723 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x2004 724 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x2004 725 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x2004 726 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004 727 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180 728 MX51_PAD_EIM_A20__GPIO2_14 0x85 729 >; 730 }; 731 732 pinctrl_gpiospi0: gpiospi0grp { 733 fsl,pins = < 734 MX51_PAD_CSI2_D18__GPIO4_11 0x85 735 MX51_PAD_CSI2_D19__GPIO4_12 0x85 736 MX51_PAD_CSI2_HSYNC__GPIO4_14 0x85 737 MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x85 738 >; 739 }; 740 741 pinctrl_i2c2: i2c2grp { 742 fsl,pins = < 743 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed 744 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed 745 >; 746 }; 747 748 pinctrl_ipu_disp1: ipudisp1grp { 749 fsl,pins = < 750 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 751 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 752 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 753 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 754 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 755 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 756 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 757 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 758 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 759 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 760 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 761 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 762 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 763 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 764 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 765 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 766 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 767 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 768 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 769 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 770 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 771 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 772 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 773 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 774 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 775 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 776 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 777 >; 778 }; 779 780 pinctrl_panel: panelgrp { 781 fsl,pins = < 782 MX51_PAD_DI1_D0_CS__GPIO3_3 0x85 783 >; 784 }; 785 786 pinctrl_pmic: pmicgrp { 787 fsl,pins = < 788 MX51_PAD_GPIO1_4__GPIO1_4 0x1e0 789 MX51_PAD_GPIO1_8__GPIO1_8 0x21e2 790 >; 791 }; 792 793 pinctrl_sndgate26mhz: sndgate26mhzgrp { 794 fsl,pins = < 795 MX51_PAD_CSPI1_RDY__GPIO4_26 0x85 796 >; 797 }; 798 799 pinctrl_swi2c: swi2cgrp { 800 fsl,pins = < 801 MX51_PAD_GPIO1_2__GPIO1_2 0xc5 802 MX51_PAD_DI1_D1_CS__GPIO3_4 0x400001f5 803 >; 804 }; 805 806 pinctrl_swmdio: swmdiogrp { 807 fsl,pins = < 808 MX51_PAD_NANDF_D14__GPIO3_26 0x21e6 809 MX51_PAD_NANDF_D15__GPIO3_25 0x21e6 810 >; 811 }; 812 813 pinctrl_ts: tsgrp { 814 fsl,pins = < 815 MX51_PAD_CSI1_D8__GPIO3_12 0x04 816 MX51_PAD_CSI1_D9__GPIO3_13 0x85 817 >; 818 }; 819 820 pinctrl_uart1: uart1grp { 821 fsl,pins = < 822 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 823 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 824 MX51_PAD_UART1_RTS__UART1_RTS 0x1c4 825 MX51_PAD_UART1_CTS__UART1_CTS 0x1c4 826 >; 827 }; 828 829 pinctrl_uart2: uart2grp { 830 fsl,pins = < 831 MX51_PAD_UART2_RXD__UART2_RXD 0xc5 832 MX51_PAD_UART2_TXD__UART2_TXD 0xc5 833 >; 834 }; 835 836 pinctrl_uart3: uart3grp { 837 fsl,pins = < 838 MX51_PAD_EIM_D25__UART3_RXD 0x1c5 839 MX51_PAD_EIM_D26__UART3_TXD 0x1c5 840 >; 841 }; 842 843 pinctrl_usbgate26mhz: usbgate26mhzgrp { 844 fsl,pins = < 845 MX51_PAD_DISP2_DAT6__GPIO1_19 0x85 846 >; 847 }; 848 849 pinctrl_usbh1: usbh1grp { 850 fsl,pins = < 851 MX51_PAD_USBH1_STP__USBH1_STP 0x0 852 MX51_PAD_USBH1_CLK__USBH1_CLK 0x0 853 MX51_PAD_USBH1_DIR__USBH1_DIR 0x0 854 MX51_PAD_USBH1_NXT__USBH1_NXT 0x0 855 MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x0 856 MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x0 857 MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x0 858 MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x0 859 MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x0 860 MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x0 861 MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x0 862 MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x0 863 >; 864 }; 865 866 pinctrl_usbh1phy: usbh1phygrp { 867 fsl,pins = < 868 MX51_PAD_NANDF_D0__GPIO4_8 0x85 869 >; 870 }; 871 872 pinctrl_usbh2: usbh2grp { 873 fsl,pins = < 874 MX51_PAD_EIM_A26__USBH2_STP 0x0 875 MX51_PAD_EIM_A24__USBH2_CLK 0x0 876 MX51_PAD_EIM_A25__USBH2_DIR 0x0 877 MX51_PAD_EIM_A27__USBH2_NXT 0x0 878 MX51_PAD_EIM_D16__USBH2_DATA0 0x0 879 MX51_PAD_EIM_D17__USBH2_DATA1 0x0 880 MX51_PAD_EIM_D18__USBH2_DATA2 0x0 881 MX51_PAD_EIM_D19__USBH2_DATA3 0x0 882 MX51_PAD_EIM_D20__USBH2_DATA4 0x0 883 MX51_PAD_EIM_D21__USBH2_DATA5 0x0 884 MX51_PAD_EIM_D22__USBH2_DATA6 0x0 885 MX51_PAD_EIM_D23__USBH2_DATA7 0x0 886 >; 887 }; 888 889 pinctrl_usbh2phy: usbh2phygrp { 890 fsl,pins = < 891 MX51_PAD_NANDF_D1__GPIO4_7 0x85 892 >; 893 }; 894 };
Cache object: bcc14df2b5d6c170a066a033dfe515b0
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