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sys/contrib/device-tree/src/arm/imx6dl-prtmvt.dts
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1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 /* 3 * Copyright (c) 2016 Protonic Holland 4 * Copyright (c) 2020 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix 5 */ 6 7 /dts-v1/; 8 #include <dt-bindings/display/sdtv-standards.h> 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/input/input.h> 11 #include <dt-bindings/leds/common.h> 12 #include <dt-bindings/media/tvp5150.h> 13 #include <dt-bindings/sound/fsl-imx-audmux.h> 14 #include "imx6dl.dtsi" 15 16 / { 17 model = "Protonic MVT board"; 18 compatible = "prt,prtmvt", "fsl,imx6dl"; 19 20 chosen { 21 stdout-path = &uart4; 22 }; 23 24 backlight: backlight { 25 compatible = "pwm-backlight"; 26 pinctrl-names = "default"; 27 pinctrl-0 = <&pinctrl_backlight>; 28 pwms = <&pwm1 0 5000000 0>; 29 brightness-levels = <0 16 64 255>; 30 num-interpolated-steps = <16>; 31 default-brightness-level = <1>; 32 power-supply = <®_3v3>; 33 enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; 34 }; 35 36 connector { 37 compatible = "composite-video-connector"; 38 label = "Composite0"; 39 sdtv-standards = <SDTV_STD_PAL_B>; 40 41 port { 42 comp0_out: endpoint { 43 remote-endpoint = <&tvp5150_comp0_in>; 44 }; 45 }; 46 }; 47 48 gpio-keys { 49 compatible = "gpio-keys"; 50 pinctrl-names = "default"; 51 pinctrl-0 = <&pinctrl_gpiokeys>; 52 autorepeat; 53 54 power { 55 label = "Power Button"; 56 gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; 57 linux,code = <KEY_POWER>; 58 wakeup-source; 59 }; 60 61 f1 { 62 label = "GPIO Key F1"; 63 linux,code = <KEY_F1>; 64 gpios = <&gpio_pca 0 GPIO_ACTIVE_LOW>; 65 }; 66 67 f2 { 68 label = "GPIO Key F2"; 69 linux,code = <KEY_F2>; 70 gpios = <&gpio_pca 1 GPIO_ACTIVE_LOW>; 71 }; 72 73 f3 { 74 label = "GPIO Key F3"; 75 linux,code = <KEY_F3>; 76 gpios = <&gpio_pca 2 GPIO_ACTIVE_LOW>; 77 }; 78 79 f4 { 80 label = "GPIO Key F4"; 81 linux,code = <KEY_F4>; 82 gpios = <&gpio_pca 3 GPIO_ACTIVE_LOW>; 83 }; 84 85 f5 { 86 label = "GPIO Key F5"; 87 linux,code = <KEY_F5>; 88 gpios = <&gpio_pca 4 GPIO_ACTIVE_LOW>; 89 }; 90 91 cycle { 92 label = "GPIO Key CYCLE"; 93 linux,code = <KEY_CYCLEWINDOWS>; 94 gpios = <&gpio_pca 5 GPIO_ACTIVE_LOW>; 95 }; 96 97 esc { 98 label = "GPIO Key ESC"; 99 linux,code = <KEY_ESC>; 100 gpios = <&gpio_pca 6 GPIO_ACTIVE_LOW>; 101 }; 102 103 up { 104 label = "GPIO Key UP"; 105 linux,code = <KEY_UP>; 106 gpios = <&gpio_pca 7 GPIO_ACTIVE_LOW>; 107 }; 108 109 down { 110 label = "GPIO Key DOWN"; 111 linux,code = <KEY_DOWN>; 112 gpios = <&gpio_pca 8 GPIO_ACTIVE_LOW>; 113 }; 114 115 ok { 116 label = "GPIO Key OK"; 117 linux,code = <KEY_OK>; 118 gpios = <&gpio_pca 9 GPIO_ACTIVE_LOW>; 119 }; 120 121 f6 { 122 label = "GPIO Key F6"; 123 linux,code = <KEY_F6>; 124 gpios = <&gpio_pca 10 GPIO_ACTIVE_LOW>; 125 }; 126 127 f7 { 128 label = "GPIO Key F7"; 129 linux,code = <KEY_F7>; 130 gpios = <&gpio_pca 11 GPIO_ACTIVE_LOW>; 131 }; 132 133 f8 { 134 label = "GPIO Key F8"; 135 linux,code = <KEY_F8>; 136 gpios = <&gpio_pca 12 GPIO_ACTIVE_LOW>; 137 }; 138 139 f9 { 140 label = "GPIO Key F9"; 141 linux,code = <KEY_F9>; 142 gpios = <&gpio_pca 13 GPIO_ACTIVE_LOW>; 143 }; 144 145 f10 { 146 label = "GPIO Key F10"; 147 linux,code = <KEY_F10>; 148 gpios = <&gpio_pca 14 GPIO_ACTIVE_LOW>; 149 }; 150 151 }; 152 153 leds { 154 compatible = "gpio-leds"; 155 pinctrl-names = "default"; 156 pinctrl-0 = <&pinctrl_leds>; 157 158 led-0 { 159 label = "debug0"; 160 function = LED_FUNCTION_HEARTBEAT; 161 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; 162 linux,default-trigger = "heartbeat"; 163 }; 164 165 led-1 { 166 label = "debug1"; 167 function = LED_FUNCTION_DISK; 168 gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; 169 linux,default-trigger = "disk-activity"; 170 }; 171 172 led-2 { 173 label = "power_led"; 174 function = LED_FUNCTION_POWER; 175 gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; 176 default-state = "on"; 177 }; 178 }; 179 180 panel { 181 compatible = "kyo,tcg070wvlq", "lg,lb070wv8"; 182 backlight = <&backlight>; 183 power-supply = <®_3v3>; 184 185 port { 186 panel_in: endpoint { 187 remote-endpoint = <&lvds0_out>; 188 }; 189 }; 190 }; 191 192 clk50m_phy: phy-clock { 193 compatible = "fixed-clock"; 194 #clock-cells = <0>; 195 clock-frequency = <50000000>; 196 }; 197 198 reg_1v8: regulator-1v8 { 199 compatible = "regulator-fixed"; 200 regulator-name = "1v8"; 201 regulator-min-microvolt = <1800000>; 202 regulator-max-microvolt = <1800000>; 203 }; 204 205 reg_3v3: regulator-3v3 { 206 compatible = "regulator-fixed"; 207 regulator-name = "3v3"; 208 regulator-min-microvolt = <3300000>; 209 regulator-max-microvolt = <3300000>; 210 }; 211 212 reg_h1_vbus: regulator-h1-vbus { 213 compatible = "regulator-fixed"; 214 regulator-name = "h1-vbus"; 215 regulator-min-microvolt = <5000000>; 216 regulator-max-microvolt = <5000000>; 217 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; 218 enable-active-high; 219 }; 220 221 reg_otg_vbus: regulator-otg-vbus { 222 compatible = "regulator-fixed"; 223 regulator-name = "otg-vbus"; 224 regulator-min-microvolt = <5000000>; 225 regulator-max-microvolt = <5000000>; 226 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 227 enable-active-high; 228 }; 229 230 sound { 231 compatible = "simple-audio-card"; 232 simple-audio-card,name = "prti6q-sgtl5000"; 233 simple-audio-card,format = "i2s"; 234 simple-audio-card,widgets = 235 "Microphone", "Microphone Jack", 236 "Line", "Line In Jack", 237 "Headphone", "Headphone Jack", 238 "Speaker", "External Speaker"; 239 simple-audio-card,routing = 240 "MIC_IN", "Microphone Jack", 241 "LINE_IN", "Line In Jack", 242 "Headphone Jack", "HP_OUT", 243 "External Speaker", "LINE_OUT"; 244 245 simple-audio-card,cpu { 246 sound-dai = <&ssi1>; 247 system-clock-frequency = <0>; 248 }; 249 250 simple-audio-card,codec { 251 sound-dai = <&codec>; 252 bitclock-master; 253 frame-master; 254 }; 255 }; 256 }; 257 258 &audmux { 259 pinctrl-names = "default"; 260 pinctrl-0 = <&pinctrl_audmux>; 261 status = "okay"; 262 263 mux-ssi1 { 264 fsl,audmux-port = <0>; 265 fsl,port-config = < 266 IMX_AUDMUX_V2_PTCR_SYN 0 267 IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 268 IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 269 IMX_AUDMUX_V2_PTCR_TFSDIR 0 270 IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) 271 >; 272 }; 273 274 mux-pins3 { 275 fsl,audmux-port = <2>; 276 fsl,port-config = < 277 IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) 278 0 IMX_AUDMUX_V2_PDCR_TXRXEN 279 >; 280 }; 281 }; 282 283 &can1 { 284 pinctrl-names = "default"; 285 pinctrl-0 = <&pinctrl_can1>; 286 status = "okay"; 287 }; 288 289 &can2 { 290 pinctrl-names = "default"; 291 pinctrl-0 = <&pinctrl_can2>; 292 status = "okay"; 293 }; 294 295 &clks { 296 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>; 297 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; 298 }; 299 300 &ecspi1 { 301 cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&pinctrl_ecspi1>; 304 status = "okay"; 305 306 flash@0 { 307 compatible = "jedec,spi-nor"; 308 reg = <0>; 309 spi-max-frequency = <20000000>; 310 }; 311 }; 312 313 &fec { 314 pinctrl-names = "default"; 315 pinctrl-0 = <&pinctrl_enet>; 316 phy-mode = "rmii"; 317 clocks = <&clks IMX6QDL_CLK_ENET>, 318 <&clks IMX6QDL_CLK_ENET>, 319 <&clk50m_phy>; 320 clock-names = "ipg", "ahb", "ptp"; 321 phy-handle = <&rmii_phy>; 322 status = "okay"; 323 324 mdio { 325 #address-cells = <1>; 326 #size-cells = <0>; 327 328 /* Microchip KSZ8081RNA PHY */ 329 rmii_phy: ethernet-phy@0 { 330 reg = <0>; 331 interrupts-extended = <&gpio4 30 IRQ_TYPE_LEVEL_LOW>; 332 reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; 333 reset-assert-us = <10000>; 334 reset-deassert-us = <3000>; 335 }; 336 }; 337 }; 338 339 &gpio1 { 340 gpio-line-names = 341 "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", 342 "CAM2_MIRROR", "", "", "SMBALERT", 343 "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", 344 "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", 345 "SD1_DATA3", "", "", 346 "", "", "", "", "", "", "", ""; 347 }; 348 349 &gpio2 { 350 gpio-line-names = 351 "", "", "", "", "", "", "", "", 352 "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "REV_ID4", 353 "BOARD_ID0", "BOARD_ID1", "BOARD_ID2", 354 "", "", "", "", "", "", "", "ON_SWITCH", 355 "POWER_LED", "", "", "", "", "", "", ""; 356 }; 357 358 &gpio3 { 359 gpio-line-names = 360 "", "", "", "", "", "", "", "", 361 "", "", "", "", "", "", "", "", 362 "ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1", 363 "CPU_ON1_FB", "USB_EXT1_OC", "USB_EXT1_PWR", "YACO_IRQ", 364 "TSS_TXD", "TSS_RXD", "", "", "", "", "YACO_BOOT0", 365 "YACO_RESET"; 366 }; 367 368 &gpio4 { 369 gpio-line-names = 370 "", "", "", "", "", "", "", "", 371 "", "", "", "", "CAN1_SR", "CAN2_SR", "CAN2_TX", "CAN2_RX", 372 "", "", "DIP1_FB", "", "", "", "", "", 373 "CPU_LIGHT_ON", "", "ETH_RESET", "", "BL_EN", 374 "BL_PWM", "ETH_INTRP", ""; 375 }; 376 377 &gpio5 { 378 gpio-line-names = 379 "", "", "", "", "", "", "", "", 380 "", "", "", "", "", "", "", "", 381 "", "", "", "", "", "", "", "", 382 "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", 383 "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; 384 }; 385 386 &i2c1 { 387 clock-frequency = <100000>; 388 pinctrl-names = "default"; 389 pinctrl-0 = <&pinctrl_i2c1>; 390 status = "okay"; 391 392 codec: audio-codec@a { 393 compatible = "fsl,sgtl5000"; 394 reg = <0xa>; 395 #sound-dai-cells = <0>; 396 clocks = <&clks 201>; 397 VDDA-supply = <®_3v3>; 398 VDDIO-supply = <®_3v3>; 399 VDDD-supply = <®_1v8>; 400 }; 401 402 video@5c { 403 compatible = "ti,tvp5150"; 404 reg = <0x5c>; 405 #address-cells = <1>; 406 #size-cells = <0>; 407 408 port@0 { 409 reg = <0>; 410 411 tvp5150_comp0_in: endpoint { 412 remote-endpoint = <&comp0_out>; 413 }; 414 }; 415 416 /* Output port 2 is video output pad */ 417 port@2 { 418 reg = <2>; 419 tvp5151_to_ipu1_csi0_mux: endpoint { 420 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; 421 }; 422 }; 423 }; 424 425 gpio_pca: gpio@74 { 426 compatible = "nxp,pca9539"; 427 reg = <0x74>; 428 pinctrl-names = "default"; 429 pinctrl-0 = <&pinctrl_pca9539>; 430 interrupt-parent = <&gpio4>; 431 interrupts = <5 IRQ_TYPE_LEVEL_LOW>; 432 gpio-controller; 433 #gpio-cells = <2>; 434 }; 435 436 /* additional i2c devices are added automatically by the boot loader */ 437 }; 438 439 &i2c3 { 440 clock-frequency = <100000>; 441 pinctrl-names = "default"; 442 pinctrl-0 = <&pinctrl_i2c3>; 443 status = "okay"; 444 445 adc@49 { 446 compatible = "ti,ads1015"; 447 reg = <0x49>; 448 #address-cells = <1>; 449 #size-cells = <0>; 450 451 channel@4 { 452 reg = <4>; 453 ti,gain = <3>; 454 ti,datarate = <3>; 455 }; 456 457 channel@5 { 458 reg = <5>; 459 ti,gain = <3>; 460 ti,datarate = <3>; 461 }; 462 463 channel@6 { 464 reg = <6>; 465 ti,gain = <3>; 466 ti,datarate = <3>; 467 }; 468 469 channel@7 { 470 reg = <7>; 471 ti,gain = <3>; 472 ti,datarate = <3>; 473 }; 474 }; 475 476 rtc@51 { 477 compatible = "nxp,pcf8563"; 478 reg = <0x51>; 479 }; 480 481 temperature-sensor@70 { 482 compatible = "ti,tmp103"; 483 reg = <0x70>; 484 }; 485 }; 486 487 &ipu1_csi0 { 488 pinctrl-names = "default"; 489 pinctrl-0 = <&pinctrl_ipu1_csi0>; 490 status = "okay"; 491 }; 492 493 &ipu1_csi0_mux_from_parallel_sensor { 494 remote-endpoint = <&tvp5151_to_ipu1_csi0_mux>; 495 }; 496 497 &ldb { 498 status = "okay"; 499 500 lvds-channel@0 { 501 status = "okay"; 502 503 port@4 { 504 reg = <4>; 505 506 lvds0_out: endpoint { 507 remote-endpoint = <&panel_in>; 508 }; 509 }; 510 }; 511 }; 512 513 &pcie { 514 status = "okay"; 515 }; 516 517 &pwm1 { 518 pinctrl-names = "default"; 519 pinctrl-0 = <&pinctrl_pwm1>; 520 status = "okay"; 521 }; 522 523 &ssi1 { 524 #sound-dai-cells = <0>; 525 fsl,mode = "ac97-slave"; 526 status = "okay"; 527 }; 528 529 &uart1 { 530 pinctrl-names = "default"; 531 pinctrl-0 = <&pinctrl_uart1>; 532 status = "okay"; 533 }; 534 535 &uart2 { 536 pinctrl-names = "default"; 537 pinctrl-0 = <&pinctrl_uart2>; 538 status = "okay"; 539 }; 540 541 &uart3 { 542 pinctrl-names = "default"; 543 pinctrl-0 = <&pinctrl_uart3>; 544 status = "okay"; 545 }; 546 547 &uart4 { 548 pinctrl-names = "default"; 549 pinctrl-0 = <&pinctrl_uart4>; 550 status = "okay"; 551 }; 552 553 &uart5 { 554 pinctrl-names = "default"; 555 pinctrl-0 = <&pinctrl_uart5>; 556 status = "okay"; 557 }; 558 559 &usbh1 { 560 vbus-supply = <®_h1_vbus>; 561 pinctrl-names = "default"; 562 phy_type = "utmi"; 563 dr_mode = "host"; 564 status = "okay"; 565 }; 566 567 &usbotg { 568 vbus-supply = <®_otg_vbus>; 569 pinctrl-names = "default"; 570 pinctrl-0 = <&pinctrl_usbotg>; 571 phy_type = "utmi"; 572 dr_mode = "host"; 573 disable-over-current; 574 status = "okay"; 575 }; 576 577 &usdhc1 { 578 pinctrl-names = "default"; 579 pinctrl-0 = <&pinctrl_usdhc1>; 580 cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 581 no-1-8-v; 582 disable-wp; 583 cap-sd-highspeed; 584 no-mmc; 585 no-sdio; 586 status = "okay"; 587 }; 588 589 &usdhc3 { 590 pinctrl-names = "default"; 591 pinctrl-0 = <&pinctrl_usdhc3>; 592 bus-width = <8>; 593 no-1-8-v; 594 non-removable; 595 no-sd; 596 no-sdio; 597 status = "okay"; 598 }; 599 600 &iomuxc { 601 pinctrl-names = "default"; 602 pinctrl-0 = <&pinctrl_hog>; 603 604 pinctrl_audmux: audmuxgrp { 605 fsl,pins = < 606 /* SGTL5000 sys_mclk */ 607 MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 608 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 609 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 610 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 611 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 612 >; 613 }; 614 615 pinctrl_backlight: backlightgrp { 616 fsl,pins = < 617 MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 618 >; 619 }; 620 621 pinctrl_can1: can1grp { 622 fsl,pins = < 623 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 624 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 625 /* CAN1_SR */ 626 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008 627 /* CAN1_TERM */ 628 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b088 629 >; 630 }; 631 632 pinctrl_can2: can2grp { 633 fsl,pins = < 634 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 635 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 636 /* CAN2_SR */ 637 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13008 638 >; 639 }; 640 641 pinctrl_ecspi1: ecspi1grp { 642 fsl,pins = < 643 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 644 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 645 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 646 /* CS */ 647 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 648 >; 649 }; 650 651 pinctrl_enet: enetgrp { 652 fsl,pins = < 653 /* MX6QDL_ENET_PINGRP4 */ 654 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 655 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 656 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 657 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 658 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 659 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 660 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 661 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 662 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 663 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 664 /* Phy reset */ 665 MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 666 /* nINTRP */ 667 MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 668 >; 669 }; 670 671 pinctrl_gpiokeys: gpiokeygrp { 672 fsl,pins = < 673 /* nON_SWITCH */ 674 MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 675 >; 676 }; 677 678 pinctrl_hog: hoggrp { 679 fsl,pins = < 680 /* ITU656_nRESET */ 681 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 682 /* CAM1_MIRROR */ 683 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x130b0 684 /* CAM2_MIRROR */ 685 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 686 /* CAM_nDETECT */ 687 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 688 /* ISB_IN1 */ 689 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 690 /* ISB_nIN2 */ 691 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 692 /* WARN_LIGHT */ 693 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x100b0 694 /* ON2_FB */ 695 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 696 /* YACO_nIRQ */ 697 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 698 /* YACO_BOOT0 */ 699 MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x130b0 700 /* YACO_nRESET */ 701 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 702 /* FORCE_ON1 */ 703 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 704 /* AUDIO_nRESET */ 705 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0 706 /* ITU656_nPDN */ 707 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 708 709 /* HW revision detect */ 710 /* REV_ID0 */ 711 MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 712 /* REV_ID1 */ 713 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 714 /* REV_ID2 */ 715 MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 716 /* REV_ID3 */ 717 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 718 /* REV_ID4 */ 719 MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 720 721 /* New in HW revision 1 */ 722 /* ON1_FB */ 723 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0 724 /* DIP1_FB */ 725 MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 726 >; 727 }; 728 729 pinctrl_i2c1: i2c1grp { 730 fsl,pins = < 731 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 732 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 733 >; 734 }; 735 736 pinctrl_i2c3: i2c3grp { 737 fsl,pins = < 738 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 739 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 740 >; 741 }; 742 743 pinctrl_ipu1_csi0: ipu1csi0grp { 744 fsl,pins = < 745 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 746 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 747 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 748 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 749 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 750 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 751 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 752 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 753 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 754 >; 755 }; 756 757 pinctrl_leds: ledsgrp { 758 fsl,pins = < 759 /* DEBUG0 */ 760 MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b0 761 /* DEBUG1 */ 762 MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0 763 /* POWER_LED */ 764 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0 765 >; 766 }; 767 768 pinctrl_pca9539: pca9539 { 769 fsl,pins = < 770 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 771 >; 772 }; 773 774 pinctrl_pwm1: pwm1grp { 775 fsl,pins = < 776 MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 777 >; 778 }; 779 780 /* YaCO AUX Uart */ 781 pinctrl_uart1: uart1grp { 782 fsl,pins = < 783 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 784 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 785 >; 786 }; 787 788 pinctrl_uart2: uart2grp { 789 fsl,pins = < 790 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 791 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 792 >; 793 }; 794 795 /* YaCO Touchscreen UART */ 796 pinctrl_uart3: uart3grp { 797 fsl,pins = < 798 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 799 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 800 >; 801 }; 802 803 pinctrl_uart4: uart4grp { 804 fsl,pins = < 805 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 806 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 807 >; 808 }; 809 810 pinctrl_uart5: uart5grp { 811 fsl,pins = < 812 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 813 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 814 >; 815 }; 816 817 pinctrl_usbotg: usbotggrp { 818 fsl,pins = < 819 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 820 /* power enable, high active */ 821 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 822 >; 823 }; 824 825 pinctrl_usdhc1: usdhc1grp { 826 fsl,pins = < 827 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 828 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 829 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 830 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 831 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 832 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 833 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 834 >; 835 }; 836 837 pinctrl_usdhc3: usdhc3grp { 838 fsl,pins = < 839 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 840 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 841 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 842 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 843 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 844 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 845 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 846 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 847 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 848 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 849 MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 850 >; 851 }; 852 };
Cache object: f56b99e133fbfe0f14c3f7c455cccead
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