imx6dl.dtsi

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    1 // SPDX-License-Identifier: GPL-2.0
    2 //
    3 // Copyright 2013 Freescale Semiconductor, Inc.
    4 
    5 #include <dt-bindings/interrupt-controller/irq.h>
    6 #include "imx6dl-pinfunc.h"
    7 #include "imx6qdl.dtsi"
    8 
    9 / {
   10         aliases {
   11                 i2c3 = &i2c4;
   12         };
   13 
   14         cpus {
   15                 #address-cells = <1>;
   16                 #size-cells = <0>;
   17 
   18                 cpu0: cpu@0 {
   19                         compatible = "arm,cortex-a9";
   20                         device_type = "cpu";
   21                         reg = <0>;
   22                         next-level-cache = <&L2>;
   23                         operating-points = <
   24                                 /* kHz    uV */
   25                                 996000  1250000
   26                                 792000  1175000
   27                                 396000  1150000
   28                         >;
   29                         fsl,soc-operating-points = <
   30                                 /* ARM kHz  SOC-PU uV */
   31                                 996000  1175000
   32                                 792000  1175000
   33                                 396000  1175000
   34                         >;
   35                         clock-latency = <61036>; /* two CLK32 periods */
   36                         #cooling-cells = <2>;
   37                         clocks = <&clks IMX6QDL_CLK_ARM>,
   38                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
   39                                  <&clks IMX6QDL_CLK_STEP>,
   40                                  <&clks IMX6QDL_CLK_PLL1_SW>,
   41                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
   42                         clock-names = "arm", "pll2_pfd2_396m", "step",
   43                                       "pll1_sw", "pll1_sys";
   44                         arm-supply = <&reg_arm>;
   45                         pu-supply = <&reg_pu>;
   46                         soc-supply = <&reg_soc>;
   47                         nvmem-cells = <&cpu_speed_grade>;
   48                         nvmem-cell-names = "speed_grade";
   49                 };
   50 
   51                 cpu@1 {
   52                         compatible = "arm,cortex-a9";
   53                         device_type = "cpu";
   54                         reg = <1>;
   55                         next-level-cache = <&L2>;
   56                         operating-points = <
   57                                 /* kHz    uV */
   58                                 996000  1250000
   59                                 792000  1175000
   60                                 396000  1150000
   61                         >;
   62                         fsl,soc-operating-points = <
   63                                 /* ARM kHz  SOC-PU uV */
   64                                 996000  1175000
   65                                 792000  1175000
   66                                 396000  1175000
   67                         >;
   68                         clock-latency = <61036>; /* two CLK32 periods */
   69                         #cooling-cells = <2>;
   70                         clocks = <&clks IMX6QDL_CLK_ARM>,
   71                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
   72                                  <&clks IMX6QDL_CLK_STEP>,
   73                                  <&clks IMX6QDL_CLK_PLL1_SW>,
   74                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
   75                         clock-names = "arm", "pll2_pfd2_396m", "step",
   76                                       "pll1_sw", "pll1_sys";
   77                         arm-supply = <&reg_arm>;
   78                         pu-supply = <&reg_pu>;
   79                         soc-supply = <&reg_soc>;
   80                 };
   81         };
   82 
   83         soc: soc {
   84                 ocram: sram@900000 {
   85                         compatible = "mmio-sram";
   86                         reg = <0x00900000 0x20000>;
   87                         clocks = <&clks IMX6QDL_CLK_OCRAM>;
   88                 };
   89 
   90                 aips1: bus@2000000 {
   91                         pxp: pxp@20f0000 {
   92                                 reg = <0x020f0000 0x4000>;
   93                                 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
   94                         };
   95 
   96                         epdc: epdc@20f4000 {
   97                                 reg = <0x020f4000 0x4000>;
   98                                 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
   99                         };
  100                 };
  101 
  102                 aips2: bus@2100000 {
  103                         i2c4: i2c@21f8000 {
  104                                 #address-cells = <1>;
  105                                 #size-cells = <0>;
  106                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
  107                                 reg = <0x021f8000 0x4000>;
  108                                 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
  109                                 clocks = <&clks IMX6DL_CLK_I2C4>;
  110                                 status = "disabled";
  111                         };
  112                 };
  113         };
  114 
  115         capture-subsystem {
  116                 compatible = "fsl,imx-capture-subsystem";
  117                 ports = <&ipu1_csi0>, <&ipu1_csi1>;
  118         };
  119 
  120         display-subsystem {
  121                 compatible = "fsl,imx-display-subsystem";
  122                 ports = <&ipu1_di0>, <&ipu1_di1>;
  123         };
  124 };
  125 
  126 &gpio1 {
  127         gpio-ranges = <&iomuxc  0 131 2>, <&iomuxc  2 137 8>, <&iomuxc 10 189 2>,
  128                       <&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>,
  129                       <&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184 1>,
  130                       <&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188 1>,
  131                       <&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127 1>,
  132                       <&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130 1>,
  133                       <&iomuxc 30 129 1>, <&iomuxc 31 122 1>;
  134 };
  135 
  136 &gpio2 {
  137         gpio-ranges = <&iomuxc  0 161 8>, <&iomuxc  8 208 8>, <&iomuxc 16  74 1>,
  138                       <&iomuxc 17  73 1>, <&iomuxc 18  72 1>, <&iomuxc 19  71 1>,
  139                       <&iomuxc 20  70 1>, <&iomuxc 21  69 1>, <&iomuxc 22  68 1>,
  140                       <&iomuxc 23  79 2>, <&iomuxc 25 118 2>, <&iomuxc 27 117 1>,
  141                       <&iomuxc 28 113 4>;
  142 };
  143 
  144 &gpio3 {
  145         gpio-ranges = <&iomuxc  0 97  2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>,
  146                       <&iomuxc 16 81 16>;
  147 };
  148 
  149 &gpio4 {
  150         gpio-ranges = <&iomuxc  5 136 1>, <&iomuxc  6 145 1>, <&iomuxc  7 150 1>,
  151                       <&iomuxc  8 146 1>, <&iomuxc  9 151 1>, <&iomuxc 10 147 1>,
  152                       <&iomuxc 11 152 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153 1>,
  153                       <&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16  39 7>,
  154                       <&iomuxc 23  56 1>, <&iomuxc 24  61 7>, <&iomuxc 31  46 1>;
  155 };
  156 
  157 &gpio5 {
  158         gpio-ranges = <&iomuxc  0 120 1>, <&iomuxc  2 77 1>, <&iomuxc  4 76 1>,
  159                       <&iomuxc  5  47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37 1>,
  160                       <&iomuxc 19  36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38 1>,
  161                       <&iomuxc 22  29 6>, <&iomuxc 28 19 4>;
  162 };
  163 
  164 &gpio6 {
  165         gpio-ranges = <&iomuxc  0  23 6>, <&iomuxc  6  75 1>, <&iomuxc  7 156 1>,
  166                       <&iomuxc  8 155 1>, <&iomuxc  9 170 1>, <&iomuxc 10 169 1>,
  167                       <&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204 1>,
  168                       <&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177 4>,
  169                       <&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181 1>,
  170                       <&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31  78 1>;
  171 };
  172 
  173 &gpio7 {
  174         gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc  1 201 1>, <&iomuxc  2 196 1>,
  175                       <&iomuxc 3 195 1>, <&iomuxc  4 197 4>, <&iomuxc  8 205 1>,
  176                       <&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>;
  177 };
  178 
  179 &gpr {
  180         ipu1_csi0_mux {
  181                 compatible = "video-mux";
  182                 mux-controls = <&mux 0>;
  183                 #address-cells = <1>;
  184                 #size-cells = <0>;
  185 
  186                 port@0 {
  187                         reg = <0>;
  188 
  189                         ipu1_csi0_mux_from_mipi_vc0: endpoint {
  190                                 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
  191                         };
  192                 };
  193 
  194                 port@1 {
  195                         reg = <1>;
  196 
  197                         ipu1_csi0_mux_from_mipi_vc1: endpoint {
  198                                 remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>;
  199                         };
  200                 };
  201 
  202                 port@2 {
  203                         reg = <2>;
  204 
  205                         ipu1_csi0_mux_from_mipi_vc2: endpoint {
  206                                 remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>;
  207                         };
  208                 };
  209 
  210                 port@3 {
  211                         reg = <3>;
  212 
  213                         ipu1_csi0_mux_from_mipi_vc3: endpoint {
  214                                 remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>;
  215                         };
  216                 };
  217 
  218                 port@4 {
  219                         reg = <4>;
  220 
  221                         ipu1_csi0_mux_from_parallel_sensor: endpoint {
  222                         };
  223                 };
  224 
  225                 port@5 {
  226                         reg = <5>;
  227 
  228                         ipu1_csi0_mux_to_ipu1_csi0: endpoint {
  229                                 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
  230                         };
  231                 };
  232         };
  233 
  234         ipu1_csi1_mux {
  235                 compatible = "video-mux";
  236                 mux-controls = <&mux 1>;
  237                 #address-cells = <1>;
  238                 #size-cells = <0>;
  239 
  240                 port@0 {
  241                         reg = <0>;
  242 
  243                         ipu1_csi1_mux_from_mipi_vc0: endpoint {
  244                                 remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>;
  245                         };
  246                 };
  247 
  248                 port@1 {
  249                         reg = <1>;
  250 
  251                         ipu1_csi1_mux_from_mipi_vc1: endpoint {
  252                                 remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>;
  253                         };
  254                 };
  255 
  256                 port@2 {
  257                         reg = <2>;
  258 
  259                         ipu1_csi1_mux_from_mipi_vc2: endpoint {
  260                                 remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>;
  261                         };
  262                 };
  263 
  264                 port@3 {
  265                         reg = <3>;
  266 
  267                         ipu1_csi1_mux_from_mipi_vc3: endpoint {
  268                                 remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>;
  269                         };
  270                 };
  271 
  272                 port@4 {
  273                         reg = <4>;
  274 
  275                         ipu1_csi1_mux_from_parallel_sensor: endpoint {
  276                         };
  277                 };
  278 
  279                 port@5 {
  280                         reg = <5>;
  281 
  282                         ipu1_csi1_mux_to_ipu1_csi1: endpoint {
  283                                 remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>;
  284                         };
  285                 };
  286         };
  287 };
  288 
  289 &gpt {
  290         compatible = "fsl,imx6dl-gpt";
  291 };
  292 
  293 &hdmi {
  294         compatible = "fsl,imx6dl-hdmi";
  295 };
  296 
  297 &iomuxc {
  298         compatible = "fsl,imx6dl-iomuxc";
  299 };
  300 
  301 &ipu1_csi1 {
  302         ipu1_csi1_from_ipu1_csi1_mux: endpoint {
  303                 remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
  304         };
  305 };
  306 
  307 &ldb {
  308         clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
  309                  <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
  310                  <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
  311         clock-names = "di0_pll", "di1_pll",
  312                       "di0_sel", "di1_sel",
  313                       "di0", "di1";
  314 };
  315 
  316 &mipi_csi {
  317         port@1 {
  318                 reg = <1>;
  319                 #address-cells = <1>;
  320                 #size-cells = <0>;
  321 
  322                 mipi_vc0_to_ipu1_csi0_mux: endpoint@0 {
  323                         reg = <0>;
  324                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
  325                 };
  326 
  327                 mipi_vc0_to_ipu1_csi1_mux: endpoint@1 {
  328                         reg = <1>;
  329                         remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;
  330                 };
  331         };
  332 
  333         port@2 {
  334                 reg = <2>;
  335                 #address-cells = <1>;
  336                 #size-cells = <0>;
  337 
  338                 mipi_vc1_to_ipu1_csi0_mux: endpoint@0 {
  339                         reg = <0>;
  340                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>;
  341                 };
  342 
  343                 mipi_vc1_to_ipu1_csi1_mux: endpoint@1 {
  344                         reg = <1>;
  345                         remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>;
  346                 };
  347         };
  348 
  349         port@3 {
  350                 reg = <3>;
  351                 #address-cells = <1>;
  352                 #size-cells = <0>;
  353 
  354                 mipi_vc2_to_ipu1_csi0_mux: endpoint@0 {
  355                         reg = <0>;
  356                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>;
  357                 };
  358 
  359                 mipi_vc2_to_ipu1_csi1_mux: endpoint@1 {
  360                         reg = <1>;
  361                         remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>;
  362                 };
  363         };
  364 
  365         port@4 {
  366                 reg = <4>;
  367                 #address-cells = <1>;
  368                 #size-cells = <0>;
  369 
  370                 mipi_vc3_to_ipu1_csi0_mux: endpoint@0 {
  371                         reg = <0>;
  372                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>;
  373                 };
  374 
  375                 mipi_vc3_to_ipu1_csi1_mux: endpoint@1 {
  376                         reg = <1>;
  377                         remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>;
  378                 };
  379         };
  380 };
  381 
  382 &mux {
  383         mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */
  384                         <0x34 0x00000038>, /* IPU_CSI1_MUX */
  385                         <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
  386                         <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
  387                         <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
  388                         <0x28 0x00000003>, /* DCIC1_MUX_CTL */
  389                         <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
  390 };
  391 
  392 &vpu {
  393         compatible = "fsl,imx6dl-vpu", "cnm,coda960";
  394 };
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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm/imx6dl.dtsi

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sys/contrib/device-tree/src/arm/imx6dl.dtsi
