Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/imx6q-kp.dtsi
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1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Copyright 2018 4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de 5 */ 6 7 /dts-v1/; 8 9 #include "imx6q.dtsi" 10 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/pwm/pwm.h> 13 #include <dt-bindings/sound/fsl-imx-audmux.h> 14 15 / { 16 backlight_lcd: backlight-lcd { 17 compatible = "pwm-backlight"; 18 pwms = <&pwm1 0 5000000>; 19 brightness-levels = <0 255>; 20 num-interpolated-steps = <255>; 21 default-brightness-level = <250>; 22 }; 23 24 beeper { 25 compatible = "pwm-beeper"; 26 pwms = <&pwm2 0 500000>; 27 }; 28 29 lcd_display: display { 30 compatible = "fsl,imx-parallel-display"; 31 #address-cells = <1>; 32 #size-cells = <0>; 33 interface-pix-fmt = "rgb24"; 34 pinctrl-names = "default"; 35 pinctrl-0 = <&pinctrl_ipu1>; 36 37 port@0 { 38 reg = <0>; 39 40 lcd_display_in: endpoint { 41 remote-endpoint = <&ipu1_di0_disp0>; 42 }; 43 }; 44 45 port@1 { 46 reg = <1>; 47 48 lcd_display_out: endpoint { 49 remote-endpoint = <&lcd_panel_in>; 50 }; 51 }; 52 }; 53 54 lcd_panel: lcd-panel { 55 compatible = "auo,g070vvn01"; 56 backlight = <&backlight_lcd>; 57 power-supply = <®_display>; 58 59 port { 60 lcd_panel_in: endpoint { 61 remote-endpoint = <&lcd_display_out>; 62 }; 63 }; 64 }; 65 66 leds { 67 compatible = "gpio-leds"; 68 69 green { 70 label = "led1"; 71 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; 72 linux,default-trigger = "gpio"; 73 default-state = "off"; 74 }; 75 76 red { 77 label = "led0"; 78 gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; 79 linux,default-trigger = "gpio"; 80 default-state = "off"; 81 }; 82 }; 83 84 reg_3p3v: regulator-3p3v { 85 compatible = "regulator-fixed"; 86 regulator-name = "3P3V"; 87 regulator-min-microvolt = <3300000>; 88 regulator-max-microvolt = <3300000>; 89 regulator-always-on; 90 }; 91 92 reg_audio: regulator-audio { 93 compatible = "regulator-fixed"; 94 regulator-name = "sgtl5000-supply"; 95 gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>; 96 enable-active-high; 97 regulator-always-on; 98 }; 99 100 reg_display: regulator-display { 101 compatible = "regulator-fixed"; 102 regulator-name = "display-supply"; 103 regulator-min-microvolt = <3300000>; 104 regulator-max-microvolt = <3300000>; 105 regulator-always-on; 106 }; 107 108 reg_usb_h1_vbus: regulator-usb_h1_vbus { 109 compatible = "regulator-fixed"; 110 regulator-name = "usb_h1_vbus"; 111 regulator-min-microvolt = <5000000>; 112 regulator-max-microvolt = <5000000>; 113 enable-active-high; 114 }; 115 116 sound { 117 compatible = "simple-audio-card"; 118 simple-audio-card,name = "imx6q-sgtl5000-audio"; 119 simple-audio-card,format = "i2s"; 120 simple-audio-card,bitclock-master = <&codec_dai>; 121 simple-audio-card,frame-master = <&codec_dai>; 122 123 cpu_dai: simple-audio-card,cpu { 124 sound-dai = <&ssi1>; 125 }; 126 127 codec_dai: simple-audio-card,codec { 128 sound-dai = <&sgtl5000>; 129 }; 130 }; 131 }; 132 133 &audmux { 134 pinctrl-names = "default"; 135 pinctrl-0 = <&pinctrl_audmux>; 136 status = "okay"; 137 138 ssi1 { 139 fsl,audmux-port = <0>; 140 fsl,port-config = < 141 (IMX_AUDMUX_V2_PTCR_SYN | 142 IMX_AUDMUX_V2_PTCR_TFSEL(2) | 143 IMX_AUDMUX_V2_PTCR_TCSEL(2) | 144 IMX_AUDMUX_V2_PTCR_TFSDIR | 145 IMX_AUDMUX_V2_PTCR_TCLKDIR) 146 IMX_AUDMUX_V2_PDCR_RXDSEL(2) 147 >; 148 }; 149 150 aud3 { 151 fsl,audmux-port = <2>; 152 fsl,port-config = < 153 IMX_AUDMUX_V2_PTCR_SYN 154 IMX_AUDMUX_V2_PDCR_RXDSEL(0) 155 >; 156 }; 157 }; 158 159 &can1 { 160 pinctrl-names = "default"; 161 pinctrl-0 = <&pinctrl_flexcan1>; 162 }; 163 164 &can2 { 165 pinctrl-names = "default"; 166 pinctrl-0 = <&pinctrl_flexcan2>; 167 }; 168 169 &fec { 170 pinctrl-names = "default"; 171 pinctrl-0 = <&pinctrl_enet>; 172 phy-mode = "rgmii"; 173 fsl,magic-packet; 174 status = "okay"; 175 }; 176 177 &i2c1 { 178 clock-frequency = <400000>; 179 pinctrl-names = "default"; 180 pinctrl-0 = <&pinctrl_i2c1>; 181 status = "okay"; 182 183 touchscreen@5d { 184 compatible = "goodix,gt911"; 185 reg = <0x5d>; 186 pinctrl-names = "default"; 187 pinctrl-0 = <&pinctrl_ts>; 188 interrupt-parent = <&gpio1>; 189 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 190 irq-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; 191 reset-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; 192 }; 193 194 ds1307: rtc@32 { 195 compatible = "dallas,ds1307"; 196 reg = <0x32>; 197 }; 198 }; 199 200 &i2c2 { 201 clock-frequency = <400000>; 202 pinctrl-names = "default"; 203 pinctrl-0 = <&pinctrl_i2c2>; 204 status = "okay"; 205 206 sgtl5000: audio-codec@a { 207 compatible = "fsl,sgtl5000"; 208 #sound-dai-cells = <0>; 209 reg = <0x0a>; 210 pinctrl-names = "default"; 211 pinctrl-0 = <&pinctrl_codec>; 212 clocks = <&clks IMX6QDL_CLK_CKO>; 213 VDDA-supply = <®_3p3v>; 214 VDDIO-supply = <®_3p3v>; 215 }; 216 }; 217 218 &iomuxc { 219 pinctrl_audmux: audmuxgrp { 220 fsl,pins = < 221 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 222 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 223 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 224 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 225 >; 226 }; 227 228 pinctrl_codec: codecgrp { 229 fsl,pins = < 230 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 231 /* sgtl5000 sys_mclk clock routed to CLKO1 */ 232 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 233 >; 234 }; 235 236 pinctrl_enet: enetgrp { 237 fsl,pins = < 238 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 239 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 240 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 241 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 242 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 243 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 244 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 245 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 246 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 247 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 248 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 249 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 250 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 251 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 252 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 253 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 254 >; 255 }; 256 257 pinctrl_flexcan1: can1grp { 258 fsl,pins = < 259 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 260 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 261 >; 262 }; 263 264 pinctrl_flexcan2: can2grp { 265 fsl,pins = < 266 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 267 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 268 >; 269 }; 270 271 pinctrl_i2c1: i2c1grp { 272 fsl,pins = < 273 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 274 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 275 >; 276 }; 277 278 pinctrl_i2c2: i2c2grp { 279 fsl,pins = < 280 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 281 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 282 >; 283 }; 284 285 pinctrl_ipu1: ipu1grp { 286 fsl,pins = < 287 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 288 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 289 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 290 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 291 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 292 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 293 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 294 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 295 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 296 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 297 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 298 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 299 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 300 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 301 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 302 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 303 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 304 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 305 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 306 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 307 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 308 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 309 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 310 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 311 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 312 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 313 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 314 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 315 >; 316 }; 317 318 pinctrl_pwm1: pwm1grp { 319 fsl,pins = < 320 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 321 >; 322 }; 323 324 pinctrl_pwm2: pwm2grp { 325 fsl,pins = < 326 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 327 >; 328 }; 329 330 pinctrl_ts: tsgrp { 331 fsl,pins = < 332 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 333 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 334 >; 335 }; 336 337 pinctrl_uart1: uart1grp { 338 fsl,pins = < 339 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 340 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 341 >; 342 }; 343 344 pinctrl_uart2: uart2grp { 345 fsl,pins = < 346 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 347 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 348 MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1 349 MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1 350 >; 351 }; 352 353 pinctrl_usdhc2: usdhc2grp { 354 fsl,pins = < 355 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 356 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 357 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 358 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 359 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 360 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 361 >; 362 }; 363 364 pinctrl_usdhc4: usdhc4grp { 365 fsl,pins = < 366 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 367 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 368 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 369 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 370 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 371 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 372 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 373 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 374 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 375 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 376 >; 377 }; 378 }; 379 380 &pwm1 { 381 #pwm-cells = <2>; 382 pinctrl-names = "default"; 383 pinctrl-0 = <&pinctrl_pwm1>; 384 status = "okay"; 385 }; 386 387 &pwm2 { 388 #pwm-cells = <2>; 389 pinctrl-names = "default"; 390 pinctrl-0 = <&pinctrl_pwm2>; 391 status = "okay"; 392 }; 393 394 &ssi1 { 395 status = "okay"; 396 }; 397 398 &uart1 { 399 pinctrl-names = "default"; 400 pinctrl-0 = <&pinctrl_uart1>; 401 status = "okay"; 402 }; 403 404 &uart2 { 405 pinctrl-names = "default"; 406 pinctrl-0 = <&pinctrl_uart2>; 407 uart-has-rtscts; 408 }; 409 410 &usbh1 { 411 status = "okay"; 412 }; 413 414 &usdhc2 { 415 pinctrl-names = "default"; 416 pinctrl-0 = <&pinctrl_usdhc2>; 417 bus-width = <4>; 418 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; 419 status = "okay"; 420 }; 421 422 &usdhc4 { 423 pinctrl-names = "default"; 424 pinctrl-0 = <&pinctrl_usdhc4>; 425 bus-width = <8>; 426 non-removable; 427 no-1-8-v; 428 keep-power-in-suspend; 429 status = "okay"; 430 }; 431 432 &wdog1 { 433 status = "okay"; 434 };
Cache object: 80dbca9e0b8211f9a2b2496c1c4b2289
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