Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/imx6q-prti6q.dts
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1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 /* 3 * Copyright (c) 2014 Protonic Holland 4 */ 5 6 /dts-v1/; 7 #include "imx6q.dtsi" 8 #include "imx6qdl-prti6q.dtsi" 9 #include <dt-bindings/leds/common.h> 10 #include <dt-bindings/sound/fsl-imx-audmux.h> 11 12 / { 13 model = "Protonic PRTI6Q board"; 14 compatible = "prt,prti6q", "fsl,imx6q"; 15 16 memory@10000000 { 17 device_type = "memory"; 18 reg = <0x10000000 0xf0000000>; 19 }; 20 21 backlight_lcd: backlight-lcd { 22 compatible = "pwm-backlight"; 23 pinctrl-names = "default"; 24 pinctrl-0 = <&pinctrl_backlight>; 25 pwms = <&pwm1 0 5000000>; 26 brightness-levels = <0 16 64 255>; 27 num-interpolated-steps = <16>; 28 default-brightness-level = <1>; 29 power-supply = <®_3v3>; 30 enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; 31 }; 32 33 can_osc: can-osc { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <25000000>; 37 }; 38 39 leds { 40 compatible = "gpio-leds"; 41 pinctrl-names = "default"; 42 pinctrl-0 = <&pinctrl_leds>; 43 44 led-debug0 { 45 function = LED_FUNCTION_STATUS; 46 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; 47 linux,default-trigger = "heartbeat"; 48 }; 49 50 led-debug1 { 51 function = LED_FUNCTION_SD; 52 gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; 53 linux,default-trigger = "disk-activity"; 54 }; 55 }; 56 57 panel { 58 compatible = "kyo,tcg121xglp"; 59 backlight = <&backlight_lcd>; 60 61 port { 62 panel_in: endpoint { 63 remote-endpoint = <&lvds0_out>; 64 }; 65 }; 66 }; 67 68 reg_1v8: regulator-1v8 { 69 compatible = "regulator-fixed"; 70 regulator-name = "1v8"; 71 regulator-min-microvolt = <1800000>; 72 regulator-max-microvolt = <1800000>; 73 }; 74 75 reg_wifi: regulator-wifi { 76 compatible = "regulator-fixed"; 77 pinctrl-names = "default"; 78 pinctrl-0 = <&pinctrl_wifi_npd>; 79 enable-active-high; 80 gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; 81 regulator-max-microvolt = <1800000>; 82 regulator-min-microvolt = <1800000>; 83 regulator-name = "regulator-WL12xx"; 84 startup-delay-us = <70000>; 85 }; 86 87 sound { 88 compatible = "simple-audio-card"; 89 simple-audio-card,name = "prti6q-sgtl5000"; 90 simple-audio-card,format = "i2s"; 91 simple-audio-card,widgets = 92 "Microphone", "Microphone Jack", 93 "Line", "Line In Jack", 94 "Headphone", "Headphone Jack", 95 "Speaker", "External Speaker"; 96 simple-audio-card,routing = 97 "MIC_IN", "Microphone Jack", 98 "LINE_IN", "Line In Jack", 99 "Headphone Jack", "HP_OUT", 100 "External Speaker", "LINE_OUT"; 101 102 simple-audio-card,cpu { 103 sound-dai = <&ssi1>; 104 system-clock-frequency = <0>; 105 }; 106 107 simple-audio-card,codec { 108 sound-dai = <&sgtl5000>; 109 bitclock-master; 110 frame-master; 111 }; 112 }; 113 114 sound-spdif { 115 compatible = "fsl,imx-audio-spdif"; 116 model = "imx-spdif"; 117 spdif-controller = <&spdif>; 118 spdif-in; 119 spdif-out; 120 }; 121 }; 122 123 &audmux { 124 pinctrl-names = "default"; 125 pinctrl-0 = <&pinctrl_audmux>; 126 status = "okay"; 127 128 mux-ssi1 { 129 fsl,audmux-port = <0>; 130 fsl,port-config = < 131 IMX_AUDMUX_V2_PTCR_SYN 0 132 IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 133 IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 134 IMX_AUDMUX_V2_PTCR_TFSDIR 0 135 IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) 136 >; 137 }; 138 139 mux-pins3 { 140 fsl,audmux-port = <2>; 141 fsl,port-config = < 142 IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) 143 0 IMX_AUDMUX_V2_PDCR_TXRXEN 144 >; 145 }; 146 }; 147 148 &can1 { 149 pinctrl-names = "default"; 150 pinctrl-0 = <&pinctrl_can1>; 151 status = "okay"; 152 }; 153 154 &can2 { 155 pinctrl-names = "default"; 156 pinctrl-0 = <&pinctrl_can2>; 157 status = "okay"; 158 }; 159 160 &ecspi1 { 161 cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; 162 pinctrl-names = "default"; 163 pinctrl-0 = <&pinctrl_ecspi1>; 164 status = "okay"; 165 166 flash@0 { 167 compatible = "jedec,spi-nor"; 168 reg = <0>; 169 spi-max-frequency = <20000000>; 170 }; 171 }; 172 173 &ecspi2 { 174 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, <&gpio4 25 GPIO_ACTIVE_LOW>; 175 pinctrl-names = "default"; 176 pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; 177 status = "okay"; 178 179 can@0 { 180 compatible = "microchip,mcp2515"; 181 reg = <0>; 182 pinctrl-names = "default"; 183 pinctrl-0 = <&pinctrl_can3>; 184 clocks = <&can_osc>; 185 interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>; 186 spi-max-frequency = <5000000>; 187 }; 188 189 adc@1 { 190 compatible = "ti,adc128s052"; 191 reg = <1>; 192 spi-max-frequency = <2000000>; 193 vref-supply = <®_3v3>; 194 }; 195 }; 196 197 &ecspi3 { 198 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; 199 pinctrl-names = "default"; 200 pinctrl-0 = <&pinctrl_ecspi3>; 201 status = "okay"; 202 }; 203 204 &fec { 205 pinctrl-names = "default"; 206 pinctrl-0 = <&pinctrl_enet>; 207 phy-mode = "rgmii-id"; 208 phy-handle = <&rgmii_phy>; 209 status = "okay"; 210 211 mdio { 212 #address-cells = <1>; 213 #size-cells = <0>; 214 215 /* Microchip KSZ9031RNX PHY */ 216 rgmii_phy: ethernet-phy@0 { 217 reg = <0>; 218 interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; 219 reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; 220 reset-assert-us = <10000>; 221 reset-deassert-us = <300>; 222 }; 223 }; 224 }; 225 226 &hdmi { 227 pinctrl-names = "default"; 228 pinctrl-0 = <&pinctrl_hdmi>; 229 ddc-i2c-bus = <&i2c2>; 230 status = "okay"; 231 }; 232 233 &i2c1 { 234 sgtl5000: audio-codec@a { 235 compatible = "fsl,sgtl5000"; 236 reg = <0xa>; 237 #sound-dai-cells = <0>; 238 clocks = <&clks 201>; 239 VDDA-supply = <®_3v3>; 240 VDDIO-supply = <®_3v3>; 241 VDDD-supply = <®_1v8>; 242 }; 243 }; 244 245 /* DDC */ 246 &i2c2 { 247 clock-frequency = <100000>; 248 pinctrl-names = "default"; 249 pinctrl-0 = <&pinctrl_i2c2>; 250 status = "okay"; 251 }; 252 253 &i2c3 { 254 adc@49 { 255 compatible = "ti,ads1015"; 256 reg = <0x49>; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 260 /* can2_l */ 261 channel@4 { 262 reg = <4>; 263 ti,gain = <3>; 264 ti,datarate = <3>; 265 }; 266 267 /* can2_h */ 268 channel@5 { 269 reg = <5>; 270 ti,gain = <3>; 271 ti,datarate = <3>; 272 }; 273 274 /* can1_l */ 275 channel@6 { 276 reg = <6>; 277 ti,gain = <3>; 278 ti,datarate = <3>; 279 }; 280 281 /* can1_h */ 282 channel@7 { 283 reg = <7>; 284 ti,gain = <3>; 285 ti,datarate = <3>; 286 }; 287 }; 288 }; 289 290 &pcie { 291 status = "okay"; 292 }; 293 294 &pwm1 { 295 #pwm-cells = <2>; 296 pinctrl-names = "default"; 297 pinctrl-0 = <&pinctrl_pwm1>; 298 status = "okay"; 299 }; 300 301 &ldb { 302 status = "okay"; 303 304 lvds-channel@0 { 305 status = "okay"; 306 307 port@4 { 308 reg = <4>; 309 310 lvds0_out: endpoint { 311 remote-endpoint = <&panel_in>; 312 }; 313 }; 314 }; 315 }; 316 317 &sata { 318 status = "okay"; 319 }; 320 321 &snvs_poweroff { 322 status = "okay"; 323 }; 324 325 &spdif { 326 pinctrl-names = "default"; 327 pinctrl-0 = <&pinctrl_spdif>; 328 status = "okay"; 329 }; 330 331 &ssi1 { 332 #sound-dai-cells = <0>; 333 fsl,mode = "ac97-slave"; 334 status = "okay"; 335 }; 336 337 &uart2 { 338 pinctrl-names = "default"; 339 pinctrl-0 = <&pinctrl_uart2>; 340 status = "okay"; 341 }; 342 343 &uart5 { 344 pinctrl-names = "default"; 345 pinctrl-0 = <&pinctrl_uart5>; 346 status = "okay"; 347 }; 348 349 &usbotg { 350 pinctrl-0 = <&pinctrl_usbotg &pinctrl_usbotg_id>; 351 }; 352 353 &usdhc2 { 354 pinctrl-names = "default"; 355 pinctrl-0 = <&pinctrl_usdhc2>; 356 non-removable; 357 vmmc-supply = <®_wifi>; 358 cap-power-off-card; 359 keep-power-in-suspend; 360 status = "okay"; 361 362 wifi { 363 compatible = "ti,wl1271"; 364 pinctrl-names = "default"; 365 pinctrl-0 = <&pinctrl_wifi>; 366 interrupts-extended = <&gpio1 30 IRQ_TYPE_LEVEL_HIGH>; 367 ref-clock-frequency = "38400000"; 368 tcxo-clock-frequency = "19200000"; 369 }; 370 }; 371 372 &iomuxc { 373 pinctrl_audmux: audmuxgrp { 374 fsl,pins = < 375 MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 376 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 377 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 378 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 379 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 380 >; 381 }; 382 383 pinctrl_backlight: backlightgrp { 384 fsl,pins = < 385 MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 386 >; 387 }; 388 389 pinctrl_can2: can2grp { 390 fsl,pins = < 391 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b008 392 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b008 393 >; 394 }; 395 396 pinctrl_can3: can3grp { 397 fsl,pins = < 398 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 399 >; 400 }; 401 402 pinctrl_ecspi1: ecspi1grp { 403 fsl,pins = < 404 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 405 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 406 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 407 /* CS */ 408 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 409 >; 410 }; 411 412 pinctrl_ecspi2: ecspi2grp { 413 fsl,pins = < 414 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 415 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 416 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 417 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 418 >; 419 }; 420 421 pinctrl_ecspi2_cs: ecspi2csgrp { 422 fsl,pins = < 423 /* ADC128S022 CS */ 424 MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1 425 >; 426 }; 427 428 pinctrl_ecspi3: ecspi3grp { 429 fsl,pins = < 430 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 431 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 432 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 433 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 434 >; 435 }; 436 437 pinctrl_enet: enetgrp { 438 fsl,pins = < 439 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 440 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 441 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 442 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 443 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 444 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 445 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 446 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 447 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 448 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 449 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 450 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 451 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 452 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 453 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 454 455 /* Phy reset */ 456 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 457 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 458 >; 459 }; 460 461 pinctrl_hdmi: hdmigrp { 462 fsl,pins = < 463 /* NOTE: DDC is done via I2C2, so DON'T 464 * configure DDC pins for HDMI! 465 */ 466 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 467 >; 468 }; 469 470 /* DDC */ 471 pinctrl_i2c2: i2c2grp { 472 fsl,pins = < 473 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 474 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 475 >; 476 }; 477 478 pinctrl_leds: ledsgrp { 479 fsl,pins = < 480 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 481 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 482 >; 483 }; 484 485 pinctrl_pwm1: pwm1grp { 486 fsl,pins = < 487 MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 488 >; 489 }; 490 491 pinctrl_spdif: spdifgrp { 492 fsl,pins = < 493 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 494 MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0 495 >; 496 }; 497 498 pinctrl_uart2: uart2grp { 499 fsl,pins = < 500 MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 501 MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 502 MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 503 MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 504 >; 505 }; 506 507 pinctrl_uart5: uart5grp { 508 fsl,pins = < 509 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 510 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 511 >; 512 }; 513 514 pinctrl_usbotg_id: usbotgidgrp { 515 fsl,pins = < 516 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f058 517 >; 518 }; 519 520 pinctrl_usdhc2: usdhc2grp { 521 fsl,pins = < 522 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 523 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 524 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 525 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 526 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 527 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 528 >; 529 }; 530 531 pinctrl_wifi: wifigrp { 532 fsl,pins = < 533 /* WL12xx IRQ */ 534 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x10880 535 >; 536 }; 537 538 pinctrl_wifi_npd: wifinpd { 539 fsl,pins = < 540 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b8b0 541 >; 542 }; 543 };
Cache object: 3699869c1b20982880f911fe4dfa437f
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