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sys/contrib/device-tree/src/arm/imx6qdl-apalis.dtsi
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1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 /* 3 * Copyright 2014-2022 Toradex 4 * Copyright 2012 Freescale Semiconductor, Inc. 5 * Copyright 2011 Linaro Ltd. 6 */ 7 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/pwm/pwm.h> 10 11 / { 12 model = "Toradex Apalis iMX6Q/D Module"; 13 compatible = "toradex,apalis_imx6q", "fsl,imx6q"; 14 15 /* Will be filled by the bootloader */ 16 memory@10000000 { 17 device_type = "memory"; 18 reg = <0x10000000 0>; 19 }; 20 21 backlight: backlight { 22 compatible = "pwm-backlight"; 23 brightness-levels = <0 45 63 88 119 158 203 255>; 24 default-brightness-level = <4>; 25 enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; 26 pinctrl-names = "default"; 27 pinctrl-0 = <&pinctrl_gpio_bl_on>; 28 power-supply = <®_module_3v3>; 29 pwms = <&pwm4 0 5000000 PWM_POLARITY_INVERTED>; 30 status = "disabled"; 31 }; 32 33 clk_ov5640_osc: clk-ov5640-osc { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <24000000>; 37 }; 38 39 gpio-keys { 40 compatible = "gpio-keys"; 41 pinctrl-names = "default"; 42 pinctrl-0 = <&pinctrl_gpio_keys>; 43 44 wakeup { 45 debounce-interval = <10>; 46 gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; 47 label = "Wake-Up"; 48 linux,code = <KEY_WAKEUP>; 49 wakeup-source; 50 }; 51 }; 52 53 lcd_display: disp0 { 54 compatible = "fsl,imx-parallel-display"; 55 #address-cells = <1>; 56 #size-cells = <0>; 57 interface-pix-fmt = "rgb24"; 58 pinctrl-names = "default"; 59 pinctrl-0 = <&pinctrl_ipu1_lcdif>; 60 status = "disabled"; 61 62 port@0 { 63 reg = <0>; 64 65 lcd_display_in: endpoint { 66 remote-endpoint = <&ipu1_di1_disp1>; 67 }; 68 }; 69 70 port@1 { 71 reg = <1>; 72 73 lcd_display_out: endpoint { 74 remote-endpoint = <&lcd_panel_in>; 75 }; 76 }; 77 }; 78 79 panel_dpi: panel-dpi { 80 compatible = "edt,et057090dhu"; 81 backlight = <&backlight>; 82 83 status = "disabled"; 84 85 port { 86 lcd_panel_in: endpoint { 87 remote-endpoint = <&lcd_display_out>; 88 }; 89 }; 90 }; 91 92 panel_lvds: panel-lvds { 93 compatible = "panel-lvds"; 94 backlight = <&backlight>; 95 status = "disabled"; 96 97 port { 98 lvds_panel_in: endpoint { 99 remote-endpoint = <&lvds0_out>; 100 }; 101 }; 102 }; 103 104 reg_module_3v3: regulator-module-3v3 { 105 compatible = "regulator-fixed"; 106 regulator-always-on; 107 regulator-max-microvolt = <3300000>; 108 regulator-min-microvolt = <3300000>; 109 regulator-name = "+V3.3"; 110 }; 111 112 reg_module_3v3_audio: regulator-module-3v3-audio { 113 compatible = "regulator-fixed"; 114 regulator-always-on; 115 regulator-max-microvolt = <3300000>; 116 regulator-min-microvolt = <3300000>; 117 regulator-name = "+V3.3_AUDIO"; 118 }; 119 120 reg_ov5640_1v8_d_o_vdd: regulator-ov5640-1v8-d-o-vdd { 121 compatible = "regulator-fixed"; 122 regulator-always-on; 123 regulator-max-microvolt = <1800000>; 124 regulator-min-microvolt = <1800000>; 125 regulator-name = "DOVDD/DVDD_1.8V"; 126 /* Note: The CSI module uses on-board 3.3V_SW supply */ 127 vin-supply = <®_module_3v3>; 128 }; 129 130 reg_ov5640_2v8_a_vdd: regulator-ov5640-2v8-a-vdd { 131 compatible = "regulator-fixed"; 132 regulator-always-on; 133 regulator-max-microvolt = <2800000>; 134 regulator-min-microvolt = <2800000>; 135 regulator-name = "AVDD/AFVDD_2.8V"; 136 /* Note: The CSI module uses on-board 3.3V_SW supply */ 137 vin-supply = <®_module_3v3>; 138 }; 139 140 reg_usb_otg_vbus: regulator-usb-otg-vbus { 141 compatible = "regulator-fixed"; 142 enable-active-high; 143 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>; 146 regulator-max-microvolt = <5000000>; 147 regulator-min-microvolt = <5000000>; 148 regulator-name = "usb_otg_vbus"; 149 status = "disabled"; 150 }; 151 152 /* on module USB hub */ 153 reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub { 154 compatible = "regulator-fixed"; 155 enable-active-high; 156 gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>; 157 pinctrl-names = "default"; 158 pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>; 159 regulator-max-microvolt = <5000000>; 160 regulator-min-microvolt = <5000000>; 161 regulator-name = "usb_host_vbus_hub"; 162 startup-delay-us = <2000>; 163 status = "okay"; 164 }; 165 166 reg_usb_host_vbus: regulator-usb-host-vbus { 167 compatible = "regulator-fixed"; 168 enable-active-high; 169 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; 170 pinctrl-names = "default"; 171 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; 172 regulator-max-microvolt = <5000000>; 173 regulator-min-microvolt = <5000000>; 174 regulator-name = "usb_host_vbus"; 175 vin-supply = <®_usb_host_vbus_hub>; 176 status = "disabled"; 177 }; 178 179 sound { 180 compatible = "fsl,imx-audio-sgtl5000"; 181 audio-codec = <&codec>; 182 audio-routing = 183 "LINE_IN", "Line In Jack", 184 "MIC_IN", "Mic Jack", 185 "Mic Jack", "Mic Bias", 186 "Headphone Jack", "HP_OUT"; 187 model = "imx6q-apalis-sgtl5000"; 188 mux-ext-port = <4>; 189 mux-int-port = <1>; 190 ssi-controller = <&ssi1>; 191 }; 192 193 sound_spdif: sound-spdif { 194 compatible = "fsl,imx-audio-spdif"; 195 spdif-controller = <&spdif>; 196 spdif-in; 197 spdif-out; 198 model = "imx-spdif"; 199 status = "disabled"; 200 }; 201 }; 202 203 &audmux { 204 pinctrl-names = "default"; 205 pinctrl-0 = <&pinctrl_audmux>; 206 status = "okay"; 207 }; 208 209 &can1 { 210 pinctrl-names = "default", "sleep"; 211 pinctrl-0 = <&pinctrl_flexcan1_default>; 212 pinctrl-1 = <&pinctrl_flexcan1_sleep>; 213 status = "disabled"; 214 }; 215 216 &can2 { 217 pinctrl-names = "default", "sleep"; 218 pinctrl-0 = <&pinctrl_flexcan2_default>; 219 pinctrl-1 = <&pinctrl_flexcan2_sleep>; 220 status = "disabled"; 221 }; 222 223 &clks { 224 fsl,pmic-stby-poweroff; 225 }; 226 227 /* Apalis SPI1 */ 228 &ecspi1 { 229 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; 230 pinctrl-names = "default"; 231 pinctrl-0 = <&pinctrl_ecspi1>; 232 status = "disabled"; 233 }; 234 235 /* Apalis SPI2 */ 236 &ecspi2 { 237 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; 238 pinctrl-names = "default"; 239 pinctrl-0 = <&pinctrl_ecspi2>; 240 status = "disabled"; 241 }; 242 243 &gpio1 { 244 gpio-line-names = "MXM3_84", 245 "MXM3_4", 246 "MXM3_15/GPIO7", 247 "MXM3_96", 248 "MXM3_37", 249 "", 250 "MXM3_17/GPIO8", 251 "MXM3_14", 252 "MXM3_12", 253 "MXM3_2", 254 "MXM3_184", 255 "MXM3_180", 256 "MXM3_178", 257 "MXM3_176", 258 "MXM3_188", 259 "MXM3_186", 260 "MXM3_160", 261 "MXM3_162", 262 "MXM3_150", 263 "MXM3_144", 264 "MXM3_154", 265 "MXM3_146", 266 "", 267 "", 268 "MXM3_72"; 269 }; 270 271 &gpio2 { 272 gpio-line-names = "MXM3_148", 273 "MXM3_152", 274 "MXM3_156", 275 "MXM3_158", 276 "MXM3_1/GPIO1", 277 "MXM3_3/GPIO2", 278 "MXM3_5/GPIO3", 279 "MXM3_7/GPIO4", 280 "MXM3_95", 281 "MXM3_6", 282 "MXM3_8", 283 "MXM3_123", 284 "MXM3_126", 285 "MXM3_128", 286 "MXM3_130", 287 "MXM3_132", 288 "MXM3_253", 289 "MXM3_251", 290 "MXM3_283", 291 "MXM3_281", 292 "MXM3_279", 293 "MXM3_277", 294 "MXM3_243", 295 "MXM3_235", 296 "MXM3_231", 297 "MXM3_229", 298 "MXM3_233", 299 "MXM3_198", 300 "MXM3_275", 301 "MXM3_273", 302 "MXM3_207", 303 "MXM3_122"; 304 }; 305 306 &gpio3 { 307 gpio-line-names = "MXM3_271", 308 "MXM3_269", 309 "MXM3_301", 310 "MXM3_299", 311 "MXM3_297", 312 "MXM3_295", 313 "MXM3_293", 314 "MXM3_291", 315 "MXM3_289", 316 "MXM3_287", 317 "MXM3_249", 318 "MXM3_247", 319 "MXM3_245", 320 "MXM3_286", 321 "MXM3_239", 322 "MXM3_35", 323 "MXM3_205", 324 "MXM3_203", 325 "MXM3_201", 326 "MXM3_116", 327 "MXM3_114", 328 "MXM3_262", 329 "MXM3_274", 330 "MXM3_124", 331 "MXM3_110", 332 "MXM3_120", 333 "MXM3_263", 334 "MXM3_265", 335 "", 336 "MXM3_135", 337 "MXM3_261", 338 "MXM3_259"; 339 }; 340 341 &gpio4 { 342 gpio-line-names = "", 343 "", 344 "", 345 "", 346 "", 347 "MXM3_194", 348 "MXM3_136", 349 "MXM3_134", 350 "MXM3_140", 351 "MXM3_138", 352 "", 353 "MXM3_220", 354 "", 355 "", 356 "MXM3_18", 357 "MXM3_16", 358 "", 359 "", 360 "MXM3_214", 361 "MXM3_216", 362 "MXM3_164"; 363 }; 364 365 &gpio5 { 366 gpio-line-names = "MXM3_159", 367 "", 368 "", 369 "", 370 "MXM3_257", 371 "", 372 "", 373 "", 374 "", 375 "", 376 "MXM3_200", 377 "MXM3_196", 378 "MXM3_204", 379 "MXM3_202", 380 "", 381 "", 382 "", 383 "", 384 "MXM3_191", 385 "MXM3_197", 386 "MXM3_77", 387 "MXM3_195", 388 "MXM3_221", 389 "MXM3_225", 390 "MXM3_223", 391 "MXM3_227", 392 "MXM3_209", 393 "MXM3_211", 394 "MXM3_118", 395 "MXM3_112", 396 "MXM3_187", 397 "MXM3_185"; 398 }; 399 400 &gpio6 { 401 gpio-line-names = "MXM3_183", 402 "MXM3_181", 403 "MXM3_179", 404 "MXM3_177", 405 "MXM3_175", 406 "MXM3_173", 407 "MXM3_255", 408 "MXM3_83", 409 "MXM3_91", 410 "MXM3_13/GPIO6", 411 "MXM3_11/GPIO5", 412 "MXM3_79", 413 "", 414 "", 415 "MXM3_190", 416 "MXM3_193", 417 "MXM3_89"; 418 }; 419 420 &gpio7 { 421 gpio-line-names = "", 422 "", 423 "", 424 "", 425 "", 426 "", 427 "", 428 "", 429 "", 430 "MXM3_99", 431 "MXM3_85", 432 "MXM3_217", 433 "MXM3_215"; 434 }; 435 436 &gpr { 437 ipu1_csi0_mux { 438 #address-cells = <1>; 439 #size-cells = <0>; 440 status = "disabled"; 441 442 port@1 { 443 reg = <1>; 444 ipu1_csi0_mux_from_parallel_sensor: endpoint { 445 remote-endpoint = <&adv7280_to_ipu1_csi0_mux>; 446 }; 447 }; 448 }; 449 }; 450 451 &fec { 452 pinctrl-names = "default"; 453 pinctrl-0 = <&pinctrl_enet>; 454 phy-mode = "rgmii-id"; 455 phy-handle = <ðphy>; 456 phy-reset-duration = <10>; 457 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; 458 status = "okay"; 459 460 mdio { 461 #address-cells = <1>; 462 #size-cells = <0>; 463 464 ethphy: ethernet-phy@7 { 465 interrupt-parent = <&gpio1>; 466 interrupts = <30 IRQ_TYPE_LEVEL_LOW>; 467 reg = <7>; 468 }; 469 }; 470 }; 471 472 &hdmi { 473 pinctrl-names = "default"; 474 pinctrl-0 = <&pinctrl_hdmi_ddc &pinctrl_hdmi_cec>; 475 status = "disabled"; 476 }; 477 478 /* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ 479 &i2c1 { 480 clock-frequency = <100000>; 481 pinctrl-names = "default", "gpio"; 482 pinctrl-0 = <&pinctrl_i2c1>; 483 pinctrl-1 = <&pinctrl_i2c1_gpio>; 484 scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 485 sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 486 status = "disabled"; 487 488 atmel_mxt_ts: touchscreen@4a { 489 compatible = "atmel,maxtouch"; 490 /* These GPIOs are muxed with the iomuxc node */ 491 interrupt-parent = <&gpio6>; 492 interrupts = <10 IRQ_TYPE_EDGE_FALLING>; /* MXM3_11 */ 493 reg = <0x4a>; 494 reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; /* MXM3_13 */ 495 status = "disabled"; 496 }; 497 }; 498 499 /* 500 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and 501 * touch screen controller 502 */ 503 &i2c2 { 504 clock-frequency = <100000>; 505 pinctrl-names = "default", "gpio"; 506 pinctrl-0 = <&pinctrl_i2c2>; 507 pinctrl-1 = <&pinctrl_i2c2_gpio>; 508 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 509 sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 510 status = "okay"; 511 512 pmic: pmic@8 { 513 compatible = "fsl,pfuze100"; 514 fsl,pmic-stby-poweroff; 515 reg = <0x08>; 516 517 regulators { 518 sw1a_reg: sw1ab { 519 regulator-always-on; 520 regulator-boot-on; 521 regulator-max-microvolt = <1875000>; 522 regulator-min-microvolt = <300000>; 523 regulator-ramp-delay = <6250>; 524 }; 525 526 sw1c_reg: sw1c { 527 regulator-always-on; 528 regulator-boot-on; 529 regulator-max-microvolt = <1875000>; 530 regulator-min-microvolt = <300000>; 531 regulator-ramp-delay = <6250>; 532 }; 533 534 sw3a_reg: sw3a { 535 regulator-always-on; 536 regulator-boot-on; 537 regulator-max-microvolt = <1975000>; 538 regulator-min-microvolt = <400000>; 539 }; 540 541 swbst_reg: swbst { 542 regulator-always-on; 543 regulator-boot-on; 544 regulator-max-microvolt = <5150000>; 545 regulator-min-microvolt = <5000000>; 546 }; 547 548 snvs_reg: vsnvs { 549 regulator-always-on; 550 regulator-boot-on; 551 regulator-max-microvolt = <3000000>; 552 regulator-min-microvolt = <1000000>; 553 }; 554 555 vref_reg: vrefddr { 556 regulator-always-on; 557 regulator-boot-on; 558 }; 559 560 vgen1_reg: vgen1 { 561 regulator-always-on; 562 regulator-boot-on; 563 regulator-max-microvolt = <1550000>; 564 regulator-min-microvolt = <800000>; 565 }; 566 567 vgen2_reg: vgen2 { 568 regulator-always-on; 569 regulator-boot-on; 570 regulator-max-microvolt = <1550000>; 571 regulator-min-microvolt = <800000>; 572 }; 573 574 vgen3_reg: vgen3 { 575 regulator-always-on; 576 regulator-boot-on; 577 regulator-max-microvolt = <3300000>; 578 regulator-min-microvolt = <1800000>; 579 }; 580 581 vgen4_reg: vgen4 { 582 regulator-always-on; 583 regulator-boot-on; 584 regulator-max-microvolt = <1800000>; 585 regulator-min-microvolt = <1800000>; 586 }; 587 588 vgen5_reg: vgen5 { 589 regulator-always-on; 590 regulator-boot-on; 591 regulator-max-microvolt = <3300000>; 592 regulator-min-microvolt = <1800000>; 593 }; 594 595 vgen6_reg: vgen6 { 596 regulator-always-on; 597 regulator-boot-on; 598 regulator-max-microvolt = <3300000>; 599 regulator-min-microvolt = <1800000>; 600 }; 601 }; 602 }; 603 604 codec: sgtl5000@a { 605 compatible = "fsl,sgtl5000"; 606 #sound-dai-cells = <0>; 607 clocks = <&clks IMX6QDL_CLK_CKO>; 608 pinctrl-names = "default"; 609 pinctrl-0 = <&pinctrl_sgtl5000>; 610 reg = <0x0a>; 611 VDDA-supply = <®_module_3v3_audio>; 612 VDDIO-supply = <®_module_3v3>; 613 VDDD-supply = <&vgen4_reg>; 614 }; 615 616 /* STMPE811 touch screen controller */ 617 stmpe811@41 { 618 compatible = "st,stmpe811"; 619 blocks = <0x5>; 620 id = <0>; 621 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 622 interrupt-controller; 623 interrupt-parent = <&gpio4>; 624 irq-trigger = <0x1>; 625 pinctrl-names = "default"; 626 pinctrl-0 = <&pinctrl_touch_int>; 627 reg = <0x41>; 628 /* 3.25 MHz ADC clock speed */ 629 st,adc-freq = <1>; 630 /* 12-bit ADC */ 631 st,mod-12b = <1>; 632 /* internal ADC reference */ 633 st,ref-sel = <0>; 634 /* ADC conversion time: 80 clocks */ 635 st,sample-time = <4>; 636 637 stmpe_ts: stmpe_touchscreen { 638 compatible = "st,stmpe-ts"; 639 /* 8 sample average control */ 640 st,ave-ctrl = <3>; 641 /* 7 length fractional part in z */ 642 st,fraction-z = <7>; 643 /* 644 * 50 mA typical 80 mA max touchscreen drivers 645 * current limit value 646 */ 647 st,i-drive = <1>; 648 /* 1 ms panel driver settling time */ 649 st,settling = <3>; 650 /* 5 ms touch detect interrupt delay */ 651 st,touch-det-delay = <5>; 652 status = "disabled"; 653 }; 654 655 stmpe_adc: stmpe_adc { 656 compatible = "st,stmpe-adc"; 657 #io-channel-cells = <1>; 658 /* forbid to use ADC channels 3-0 (touch) */ 659 st,norequest-mask = <0x0F>; 660 }; 661 }; 662 }; 663 664 /* 665 * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier 666 * board) 667 */ 668 &i2c3 { 669 clock-frequency = <100000>; 670 pinctrl-names = "default", "gpio"; 671 pinctrl-0 = <&pinctrl_i2c3>; 672 pinctrl-1 = <&pinctrl_i2c3_gpio>; 673 scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 674 sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 675 status = "disabled"; 676 677 adv_7280: adv7280@21 { 678 compatible = "adi,adv7280"; 679 adv,force-bt656-4; 680 pinctrl-names = "default"; 681 pinctrl-0 = <&pinctrl_ipu1_csi0>; 682 reg = <0x21>; 683 status = "disabled"; 684 685 port { 686 adv7280_to_ipu1_csi0_mux: endpoint { 687 bus-width = <8>; 688 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; 689 }; 690 }; 691 }; 692 693 ov5640_csi_cam: ov5640_mipi@3c { 694 compatible = "ovti,ov5640"; 695 AVDD-supply = <®_ov5640_2v8_a_vdd>; 696 DOVDD-supply = <®_ov5640_1v8_d_o_vdd>; 697 DVDD-supply = <®_ov5640_1v8_d_o_vdd>; 698 clock-names = "xclk"; 699 clocks = <&clks IMX6QDL_CLK_CKO2>; 700 pinctrl-names = "default"; 701 pinctrl-0 = <&pinctrl_cam_mclk>; 702 /* These GPIOs are muxed with the iomuxc node */ 703 powerdown-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; 704 reg = <0x3c>; 705 reset-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; 706 status = "disabled"; 707 708 port { 709 ov5640_to_mipi_csi2: endpoint { 710 clock-lanes = <0>; 711 data-lanes = <1 2>; 712 remote-endpoint = <&mipi_csi_from_ov5640>; 713 }; 714 }; 715 }; 716 }; 717 718 &ipu1_di1_disp1 { 719 remote-endpoint = <&lcd_display_in>; 720 }; 721 722 &ldb { 723 lvds-channel@0 { 724 port@4 { 725 reg = <4>; 726 727 lvds0_out: endpoint { 728 remote-endpoint = <&lvds_panel_in>; 729 }; 730 }; 731 }; 732 733 lvds-channel@1 { 734 fsl,data-mapping = "spwg"; 735 fsl,data-width = <18>; 736 737 port@4 { 738 reg = <4>; 739 740 lvds1_out: endpoint { 741 }; 742 }; 743 }; 744 }; 745 746 &mipi_csi { 747 #address-cells = <1>; 748 #size-cells = <0>; 749 status = "disabled"; 750 751 port@0 { 752 reg = <0>; 753 754 mipi_csi_from_ov5640: endpoint { 755 clock-lanes = <0>; 756 data-lanes = <1 2>; 757 remote-endpoint = <&ov5640_to_mipi_csi2>; 758 }; 759 }; 760 }; 761 762 &pwm1 { 763 pinctrl-names = "default"; 764 pinctrl-0 = <&pinctrl_pwm1>; 765 status = "disabled"; 766 }; 767 768 &pwm2 { 769 pinctrl-names = "default"; 770 pinctrl-0 = <&pinctrl_pwm2>; 771 status = "disabled"; 772 }; 773 774 &pwm3 { 775 pinctrl-names = "default"; 776 pinctrl-0 = <&pinctrl_pwm3>; 777 status = "disabled"; 778 }; 779 780 &pwm4 { 781 pinctrl-names = "default"; 782 pinctrl-0 = <&pinctrl_pwm4>; 783 status = "disabled"; 784 }; 785 786 &spdif { 787 pinctrl-names = "default"; 788 pinctrl-0 = <&pinctrl_spdif>; 789 status = "disabled"; 790 }; 791 792 &ssi1 { 793 status = "okay"; 794 }; 795 796 &uart1 { 797 fsl,dte-mode; 798 pinctrl-names = "default"; 799 pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; 800 uart-has-rtscts; 801 status = "disabled"; 802 }; 803 804 &uart2 { 805 fsl,dte-mode; 806 pinctrl-names = "default"; 807 pinctrl-0 = <&pinctrl_uart2_dte>; 808 uart-has-rtscts; 809 status = "disabled"; 810 }; 811 812 &uart4 { 813 fsl,dte-mode; 814 pinctrl-names = "default"; 815 pinctrl-0 = <&pinctrl_uart4_dte>; 816 status = "disabled"; 817 }; 818 819 &uart5 { 820 fsl,dte-mode; 821 pinctrl-names = "default"; 822 pinctrl-0 = <&pinctrl_uart5_dte>; 823 status = "disabled"; 824 }; 825 826 &usbotg { 827 disable-over-current; 828 pinctrl-names = "default"; 829 pinctrl-0 = <&pinctrl_usbotg>; 830 status = "disabled"; 831 }; 832 833 /* MMC1 */ 834 &usdhc1 { 835 bus-width = <8>; 836 cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; 837 disable-wp; 838 no-1-8-v; 839 pinctrl-names = "default"; 840 pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>; 841 vqmmc-supply = <®_module_3v3>; 842 status = "disabled"; 843 }; 844 845 /* SD1 */ 846 &usdhc2 { 847 bus-width = <4>; 848 disable-wp; 849 no-1-8-v; 850 pinctrl-names = "default"; 851 pinctrl-0 = <&pinctrl_usdhc2>; 852 vqmmc-supply = <®_module_3v3>; 853 status = "disabled"; 854 }; 855 856 /* eMMC */ 857 &usdhc3 { 858 bus-width = <8>; 859 no-1-8-v; 860 non-removable; 861 pinctrl-names = "default"; 862 pinctrl-0 = <&pinctrl_usdhc3>; 863 vqmmc-supply = <®_module_3v3>; 864 status = "okay"; 865 }; 866 867 &weim { 868 status = "disabled"; 869 }; 870 871 &iomuxc { 872 /* Mux the Apalis GPIOs */ 873 pinctrl-names = "default"; 874 pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2 875 &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4 876 &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6 877 &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8 878 >; 879 880 pinctrl_apalis_gpio1: apalisgpio1grp { 881 fsl,pins = < 882 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0 883 >; 884 }; 885 886 pinctrl_apalis_gpio2: apalisgpio2grp { 887 fsl,pins = < 888 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0 889 >; 890 }; 891 892 pinctrl_apalis_gpio3: apalisgpio3grp { 893 fsl,pins = < 894 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0 895 >; 896 }; 897 898 pinctrl_apalis_gpio4: apalisgpio4grp { 899 fsl,pins = < 900 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0 901 >; 902 }; 903 904 pinctrl_apalis_gpio5: apalisgpio5grp { 905 fsl,pins = < 906 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0 907 >; 908 }; 909 910 pinctrl_apalis_gpio6: apalisgpio6grp { 911 fsl,pins = < 912 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0 913 >; 914 }; 915 916 pinctrl_apalis_gpio7: apalisgpio7grp { 917 fsl,pins = < 918 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0 919 >; 920 }; 921 922 pinctrl_apalis_gpio8: apalisgpio8grp { 923 fsl,pins = < 924 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0 925 >; 926 }; 927 928 pinctrl_audmux: audmuxgrp { 929 fsl,pins = < 930 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 931 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 932 MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 933 MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 934 >; 935 }; 936 937 pinctrl_cam_mclk: cammclkgrp { 938 fsl,pins = < 939 /* CAM sys_mclk */ 940 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0 941 >; 942 }; 943 944 pinctrl_ecspi1: ecspi1grp { 945 fsl,pins = < 946 MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1 947 MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1 948 MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1 949 /* SPI1 cs */ 950 MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000b1 951 >; 952 }; 953 954 pinctrl_ecspi2: ecspi2grp { 955 fsl,pins = < 956 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 957 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 958 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 959 /* SPI2 cs */ 960 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 961 >; 962 }; 963 964 pinctrl_enet: enetgrp { 965 fsl,pins = < 966 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 967 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 968 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 969 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 970 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 971 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 972 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 973 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 974 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 975 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 976 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 977 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 978 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 979 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 980 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 981 /* Ethernet PHY reset */ 982 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0 983 /* Ethernet PHY interrupt */ 984 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x000b1 985 >; 986 }; 987 988 pinctrl_flexcan1_default: flexcan1defgrp { 989 fsl,pins = < 990 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 991 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 992 >; 993 }; 994 995 pinctrl_flexcan1_sleep: flexcan1slpgrp { 996 fsl,pins = < 997 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0 998 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0 999 >; 1000 }; 1001 1002 pinctrl_flexcan2_default: flexcan2defgrp { 1003 fsl,pins = < 1004 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 1005 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 1006 >; 1007 }; 1008 pinctrl_flexcan2_sleep: flexcan2slpgrp { 1009 fsl,pins = < 1010 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0 1011 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0 1012 >; 1013 }; 1014 1015 pinctrl_gpio_bl_on: gpioblongrp { 1016 fsl,pins = < 1017 MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 1018 >; 1019 }; 1020 1021 pinctrl_gpio_keys: gpio1io04grp { 1022 fsl,pins = < 1023 /* Power button */ 1024 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 1025 >; 1026 }; 1027 1028 pinctrl_hdmi_cec: hdmicecgrp { 1029 fsl,pins = < 1030 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 1031 >; 1032 }; 1033 1034 pinctrl_hdmi_ddc: hdmiddcgrp { 1035 fsl,pins = < 1036 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 1037 MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1 1038 >; 1039 }; 1040 1041 pinctrl_i2c1: i2c1grp { 1042 fsl,pins = < 1043 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 1044 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 1045 >; 1046 }; 1047 1048 pinctrl_i2c1_gpio: i2c1gpiogrp { 1049 fsl,pins = < 1050 MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b8b1 1051 MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b8b1 1052 >; 1053 }; 1054 1055 pinctrl_i2c2: i2c2grp { 1056 fsl,pins = < 1057 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 1058 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 1059 >; 1060 }; 1061 1062 pinctrl_i2c2_gpio: i2c2gpiogrp { 1063 fsl,pins = < 1064 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 1065 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 1066 >; 1067 }; 1068 1069 pinctrl_i2c3: i2c3grp { 1070 fsl,pins = < 1071 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 1072 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 1073 >; 1074 }; 1075 1076 pinctrl_i2c3_gpio: i2c3gpiogrp { 1077 fsl,pins = < 1078 MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1 1079 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1 1080 >; 1081 }; 1082 1083 pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel camera */ 1084 fsl,pins = < 1085 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0xb0b1 1086 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0xb0b1 1087 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0xb0b1 1088 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0xb0b1 1089 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0xb0b1 1090 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0xb0b1 1091 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0xb0b1 1092 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0xb0b1 1093 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1 1094 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0xb0b1 1095 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0xb0b1 1096 >; 1097 }; 1098 1099 pinctrl_ipu1_lcdif: ipu1lcdifgrp { 1100 fsl,pins = < 1101 MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x61 1102 /* DE */ 1103 MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x61 1104 /* HSync */ 1105 MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x61 1106 /* VSync */ 1107 MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x61 1108 MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x61 1109 MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x61 1110 MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x61 1111 MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x61 1112 MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x61 1113 MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x61 1114 MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x61 1115 MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x61 1116 MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x61 1117 MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x61 1118 MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x61 1119 MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x61 1120 MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x61 1121 MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x61 1122 MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x61 1123 MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x61 1124 MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x61 1125 MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x61 1126 MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x61 1127 MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x61 1128 MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x61 1129 MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x61 1130 MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x61 1131 MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x61 1132 >; 1133 }; 1134 1135 pinctrl_ipu2_vdac: ipu2vdacgrp { 1136 fsl,pins = < 1137 MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xd1 1138 MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0xd1 1139 MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0xd1 1140 MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0xd1 1141 MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0xf9 1142 MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0xf9 1143 MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0xf9 1144 MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0xf9 1145 MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0xf9 1146 MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0xf9 1147 MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0xf9 1148 MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0xf9 1149 MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0xf9 1150 MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0xf9 1151 MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0xf9 1152 MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0xf9 1153 MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0xf9 1154 MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0xf9 1155 MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0xf9 1156 MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0xf9 1157 >; 1158 }; 1159 1160 pinctrl_mmc_cd: mmccdgrp { 1161 fsl,pins = < 1162 /* MMC1 CD */ 1163 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0 1164 >; 1165 }; 1166 1167 pinctrl_pwm1: pwm1grp { 1168 fsl,pins = < 1169 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 1170 >; 1171 }; 1172 1173 pinctrl_pwm2: pwm2grp { 1174 fsl,pins = < 1175 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 1176 >; 1177 }; 1178 1179 pinctrl_pwm3: pwm3grp { 1180 fsl,pins = < 1181 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 1182 >; 1183 }; 1184 1185 pinctrl_pwm4: pwm4grp { 1186 fsl,pins = < 1187 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 1188 >; 1189 }; 1190 1191 pinctrl_regulator_usbh_pwr: regusbhpwrgrp { 1192 fsl,pins = < 1193 /* USBH_EN */ 1194 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058 1195 >; 1196 }; 1197 1198 pinctrl_regulator_usbhub_pwr: regusbhubpwrgrp { 1199 fsl,pins = < 1200 /* USBH_HUB_EN */ 1201 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058 1202 >; 1203 }; 1204 1205 pinctrl_regulator_usbotg_pwr: regusbotgpwrgrp { 1206 fsl,pins = < 1207 /* USBO1 power en */ 1208 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058 1209 >; 1210 }; 1211 1212 pinctrl_reset_moci: resetmocigrp { 1213 fsl,pins = < 1214 /* RESET_MOCI control */ 1215 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058 1216 >; 1217 }; 1218 1219 pinctrl_sd_cd: sdcdgrp { 1220 fsl,pins = < 1221 /* SD1 CD */ 1222 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0 1223 >; 1224 }; 1225 1226 pinctrl_sgtl5000: sgtl5000grp { 1227 fsl,pins = < 1228 MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 1229 >; 1230 }; 1231 1232 pinctrl_spdif: spdifgrp { 1233 fsl,pins = < 1234 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 1235 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 1236 >; 1237 }; 1238 1239 pinctrl_touch_int: touchintgrp { 1240 fsl,pins = < 1241 /* STMPE811 interrupt */ 1242 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 1243 >; 1244 }; 1245 1246 /* Additional DTR, DSR, DCD */ 1247 pinctrl_uart1_ctrl: uart1ctrlgrp { 1248 fsl,pins = < 1249 MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 1250 MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 1251 MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 1252 >; 1253 }; 1254 1255 pinctrl_uart1_dce: uart1dcegrp { 1256 fsl,pins = < 1257 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 1258 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 1259 >; 1260 }; 1261 1262 /* DTE mode */ 1263 pinctrl_uart1_dte: uart1dtegrp { 1264 fsl,pins = < 1265 MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 1266 MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 1267 MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 1268 MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 1269 >; 1270 }; 1271 1272 pinctrl_uart2_dce: uart2dcegrp { 1273 fsl,pins = < 1274 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 1275 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 1276 >; 1277 }; 1278 1279 /* DTE mode */ 1280 pinctrl_uart2_dte: uart2dtegrp { 1281 fsl,pins = < 1282 MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 1283 MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 1284 MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 1285 MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 1286 >; 1287 }; 1288 1289 pinctrl_uart4_dce: uart4dcegrp { 1290 fsl,pins = < 1291 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 1292 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 1293 >; 1294 }; 1295 1296 /* DTE mode */ 1297 pinctrl_uart4_dte: uart4dtegrp { 1298 fsl,pins = < 1299 MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1 1300 MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1 1301 >; 1302 }; 1303 1304 pinctrl_uart5_dce: uart5dcegrp { 1305 fsl,pins = < 1306 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 1307 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 1308 >; 1309 }; 1310 1311 /* DTE mode */ 1312 pinctrl_uart5_dte: uart5dtegrp { 1313 fsl,pins = < 1314 MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1 1315 MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1 1316 >; 1317 }; 1318 1319 pinctrl_usbotg: usbotggrp { 1320 fsl,pins = < 1321 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 1322 >; 1323 }; 1324 1325 pinctrl_usdhc1_4bit: usdhc1-4bitgrp { 1326 fsl,pins = < 1327 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 1328 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 1329 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 1330 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 1331 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 1332 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 1333 >; 1334 }; 1335 1336 pinctrl_usdhc1_8bit: usdhc1-8bitgrp { 1337 fsl,pins = < 1338 MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071 1339 MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071 1340 MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071 1341 MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071 1342 >; 1343 }; 1344 1345 pinctrl_usdhc2: usdhc2grp { 1346 fsl,pins = < 1347 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 1348 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 1349 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 1350 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 1351 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 1352 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 1353 >; 1354 }; 1355 1356 pinctrl_usdhc3: usdhc3grp { 1357 fsl,pins = < 1358 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 1359 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 1360 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 1361 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 1362 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 1363 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 1364 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 1365 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 1366 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 1367 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 1368 /* eMMC reset */ 1369 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 1370 >; 1371 }; 1372 };
Cache object: d18552348d67d9f6165d85cc4650e146
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