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sys/contrib/device-tree/src/arm/imx6qdl-colibri.dtsi
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1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 2 /* 3 * Copyright 2014-2022 Toradex 4 * Copyright 2012 Freescale Semiconductor, Inc. 5 * Copyright 2011 Linaro Ltd. 6 */ 7 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/pwm/pwm.h> 10 11 / { 12 model = "Toradex Colibri iMX6DL/S Module"; 13 compatible = "toradex,colibri_imx6dl", "fsl,imx6dl"; 14 15 backlight: backlight { 16 compatible = "pwm-backlight"; 17 brightness-levels = <0 45 63 88 119 158 203 255>; 18 default-brightness-level = <4>; 19 enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ 20 pinctrl-names = "default"; 21 pinctrl-0 = <&pinctrl_gpio_bl_on>; 22 power-supply = <®_module_3v3>; 23 pwms = <&pwm3 0 5000000 PWM_POLARITY_INVERTED>; 24 status = "disabled"; 25 }; 26 27 gpio-keys { 28 compatible = "gpio-keys"; 29 pinctrl-names = "default"; 30 pinctrl-0 = <&pinctrl_gpio_keys>; 31 32 wakeup { 33 debounce-interval = <10>; 34 gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */ 35 label = "Wake-Up"; 36 linux,code = <KEY_WAKEUP>; 37 wakeup-source; 38 }; 39 }; 40 41 lcd_display: disp0 { 42 compatible = "fsl,imx-parallel-display"; 43 interface-pix-fmt = "bgr666"; 44 pinctrl-names = "default"; 45 pinctrl-0 = <&pinctrl_ipu1_lcdif>; 46 status = "disabled"; 47 48 #address-cells = <1>; 49 #size-cells = <0>; 50 51 port@0 { 52 reg = <0>; 53 54 lcd_display_in: endpoint { 55 remote-endpoint = <&ipu1_di0_disp0>; 56 }; 57 }; 58 59 port@1 { 60 reg = <1>; 61 62 lcd_display_out: endpoint { 63 remote-endpoint = <&lcd_panel_in>; 64 }; 65 }; 66 }; 67 68 /* Will be filled by the bootloader */ 69 memory@10000000 { 70 device_type = "memory"; 71 reg = <0x10000000 0>; 72 }; 73 74 panel_dpi: panel-dpi { 75 /* 76 * edt,et057090dhu: EDT 5.7" LCD TFT 77 * edt,et070080dh6: EDT 7.0" LCD TFT 78 */ 79 compatible = "edt,et057090dhu"; 80 backlight = <&backlight>; 81 status = "disabled"; 82 83 port { 84 lcd_panel_in: endpoint { 85 remote-endpoint = <&lcd_display_out>; 86 }; 87 }; 88 }; 89 90 reg_module_3v3: regulator-module-3v3 { 91 compatible = "regulator-fixed"; 92 regulator-name = "+V3.3"; 93 regulator-min-microvolt = <3300000>; 94 regulator-max-microvolt = <3300000>; 95 regulator-always-on; 96 }; 97 98 reg_module_3v3_audio: regulator-module-3v3-audio { 99 compatible = "regulator-fixed"; 100 regulator-name = "+V3.3_AUDIO"; 101 regulator-min-microvolt = <3300000>; 102 regulator-max-microvolt = <3300000>; 103 regulator-always-on; 104 }; 105 106 reg_usb_host_vbus: regulator-usb-host-vbus { 107 compatible = "regulator-fixed"; 108 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */ 109 pinctrl-names = "default"; 110 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; 111 regulator-max-microvolt = <5000000>; 112 regulator-min-microvolt = <5000000>; 113 regulator-name = "usb_host_vbus"; 114 status = "disabled"; 115 }; 116 117 sound { 118 compatible = "fsl,imx-audio-sgtl5000"; 119 audio-codec = <&codec>; 120 audio-routing = 121 "Headphone Jack", "HP_OUT", 122 "LINE_IN", "Line In Jack", 123 "MIC_IN", "Mic Jack", 124 "Mic Jack", "Mic Bias"; 125 model = "imx6dl-colibri-sgtl5000"; 126 mux-int-port = <1>; 127 mux-ext-port = <5>; 128 ssi-controller = <&ssi1>; 129 }; 130 131 /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */ 132 sound_spdif: sound-spdif { 133 compatible = "fsl,imx-audio-spdif"; 134 spdif-controller = <&spdif>; 135 spdif-in; 136 spdif-out; 137 model = "imx-spdif"; 138 status = "disabled"; 139 }; 140 }; 141 142 &audmux { 143 pinctrl-names = "default"; 144 pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>; 145 status = "okay"; 146 }; 147 148 /* Optional on SODIMM 55/63 */ 149 &can1 { 150 pinctrl-names = "default"; 151 pinctrl-0 = <&pinctrl_flexcan1>; 152 status = "disabled"; 153 }; 154 155 /* Optional on SODIMM 178/188 */ 156 &can2 { 157 pinctrl-names = "default"; 158 pinctrl-0 = <&pinctrl_flexcan2>; 159 status = "disabled"; 160 }; 161 162 &clks { 163 fsl,pmic-stby-poweroff; 164 }; 165 166 /* Colibri SSP */ 167 &ecspi4 { 168 cs-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; 169 pinctrl-names = "default"; 170 pinctrl-0 = <&pinctrl_ecspi4>; 171 status = "disabled"; 172 }; 173 174 &fec { 175 phy-mode = "rmii"; 176 phy-handle = <ðphy>; 177 pinctrl-names = "default"; 178 pinctrl-0 = <&pinctrl_enet>; 179 status = "okay"; 180 181 mdio { 182 #address-cells = <1>; 183 #size-cells = <0>; 184 185 ethphy: ethernet-phy@0 { 186 reg = <0>; 187 micrel,led-mode = <0>; 188 }; 189 }; 190 }; 191 192 &gpio1 { 193 gpio-line-names = "", 194 "SODIMM_67", 195 "SODIMM_180", 196 "SODIMM_196", 197 "SODIMM_174", 198 "SODIMM_176", 199 "SODIMM_194", 200 "SODIMM_55", 201 "SODIMM_63", 202 "SODIMM_28", 203 "SODIMM_93", 204 "SODIMM_69", 205 "SODIMM_99", 206 "SODIMM_130", 207 "SODIMM_106", 208 "SODIMM_98", 209 "SODIMM_192", 210 "SODIMM_49", 211 "SODIMM_190", 212 "SODIMM_51", 213 "SODIMM_47", 214 "SODIMM_53", 215 "", 216 "SODIMM_22"; 217 }; 218 219 &gpio2 { 220 gpio-line-names = "SODIMM_132", 221 "SODIMM_134", 222 "SODIMM_135", 223 "SODIMM_133", 224 "SODIMM_102", 225 "SODIMM_43", 226 "SODIMM_127", 227 "SODIMM_37", 228 "SODIMM_104", 229 "SODIMM_59", 230 "SODIMM_30", 231 "SODIMM_100", 232 "SODIMM_38", 233 "SODIMM_34", 234 "SODIMM_32", 235 "SODIMM_36", 236 "SODIMM_59", 237 "SODIMM_67", 238 "SODIMM_97", 239 "SODIMM_79", 240 "SODIMM_103", 241 "SODIMM_101", 242 "SODIMM_45", 243 "SODIMM_105", 244 "SODIMM_107", 245 "SODIMM_91", 246 "SODIMM_89", 247 "SODIMM_150", 248 "SODIMM_126", 249 "SODIMM_128", 250 "", 251 "SODIMM_94"; 252 }; 253 254 &gpio3 { 255 gpio-line-names = "SODIMM_111", 256 "SODIMM_113", 257 "SODIMM_115", 258 "SODIMM_117", 259 "SODIMM_119", 260 "SODIMM_121", 261 "SODIMM_123", 262 "SODIMM_125", 263 "SODIMM_110", 264 "SODIMM_112", 265 "SODIMM_114", 266 "SODIMM_116", 267 "SODIMM_118", 268 "SODIMM_120", 269 "SODIMM_122", 270 "SODIMM_124", 271 "", 272 "SODIMM_96", 273 "SODIMM_77", 274 "SODIMM_25", 275 "SODIMM_27", 276 "SODIMM_88", 277 "SODIMM_90", 278 "SODIMM_31", 279 "SODIMM_23", 280 "SODIMM_29", 281 "SODIMM_71", 282 "SODIMM_73", 283 "SODIMM_92", 284 "SODIMM_81", 285 "SODIMM_131", 286 "SODIMM_129"; 287 }; 288 289 &gpio4 { 290 gpio-line-names = "", 291 "", 292 "", 293 "", 294 "", 295 "SODIMM_168", 296 "", 297 "", 298 "", 299 "", 300 "SODIMM_184", 301 "SODIMM_186", 302 "HDMI_15", 303 "HDMI_16", 304 "SODIMM_178", 305 "SODIMM_188", 306 "SODIMM_56", 307 "SODIMM_44", 308 "SODIMM_68", 309 "SODIMM_82", 310 "SODIMM_24", 311 "SODIMM_76", 312 "SODIMM_70", 313 "SODIMM_60", 314 "SODIMM_58", 315 "SODIMM_78", 316 "SODIMM_72", 317 "SODIMM_80", 318 "SODIMM_46", 319 "SODIMM_62", 320 "SODIMM_48", 321 "SODIMM_74"; 322 }; 323 324 &gpio5 { 325 gpio-line-names = "SODIMM_95", 326 "", 327 "SODIMM_86", 328 "", 329 "SODIMM_65", 330 "SODIMM_50", 331 "SODIMM_52", 332 "SODIMM_54", 333 "SODIMM_66", 334 "SODIMM_64", 335 "SODIMM_57", 336 "SODIMM_61", 337 "SODIMM_136", 338 "SODIMM_138", 339 "SODIMM_140", 340 "SODIMM_142", 341 "SODIMM_144", 342 "SODIMM_146", 343 "SODIMM_172", 344 "SODIMM_170", 345 "SODIMM_149", 346 "SODIMM_151", 347 "SODIMM_153", 348 "SODIMM_155", 349 "SODIMM_157", 350 "SODIMM_159", 351 "SODIMM_161", 352 "SODIMM_163", 353 "SODIMM_33", 354 "SODIMM_35", 355 "SODIMM_165", 356 "SODIMM_167"; 357 }; 358 359 &gpio6 { 360 gpio-line-names = "SODIMM_169", 361 "SODIMM_171", 362 "SODIMM_173", 363 "SODIMM_175", 364 "SODIMM_177", 365 "SODIMM_179", 366 "SODIMM_85", 367 "SODIMM_166", 368 "SODIMM_160", 369 "SODIMM_162", 370 "SODIMM_158", 371 "SODIMM_164", 372 "", 373 "", 374 "SODIMM_156", 375 "SODIMM_75", 376 "SODIMM_154", 377 "", 378 "", 379 "", 380 "", 381 "", 382 "", 383 "", 384 "", 385 "", 386 "", 387 "", 388 "", 389 "", 390 "", 391 "SODIMM_152"; 392 }; 393 394 &gpio7 { 395 gpio-line-names = "", 396 "", 397 "", 398 "", 399 "", 400 "", 401 "", 402 "", 403 "", 404 "SODIMM_19", 405 "SODIMM_21", 406 "", 407 "SODIMM_137"; 408 }; 409 410 &hdmi { 411 pinctrl-names = "default"; 412 pinctrl-0 = <&pinctrl_hdmi_ddc>; 413 status = "disabled"; 414 }; 415 416 /* 417 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and 418 * touch screen controller 419 */ 420 &i2c2 { 421 clock-frequency = <100000>; 422 pinctrl-names = "default", "gpio"; 423 pinctrl-0 = <&pinctrl_i2c2>; 424 pinctrl-1 = <&pinctrl_i2c2_gpio>; 425 scl-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 426 sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 427 status = "okay"; 428 429 pmic: pmic@8 { 430 compatible = "fsl,pfuze100"; 431 fsl,pmic-stby-poweroff; 432 reg = <0x08>; 433 434 regulators { 435 sw1a_reg: sw1ab { 436 regulator-always-on; 437 regulator-boot-on; 438 regulator-max-microvolt = <1875000>; 439 regulator-min-microvolt = <300000>; 440 regulator-ramp-delay = <6250>; 441 }; 442 443 sw1c_reg: sw1c { 444 regulator-always-on; 445 regulator-boot-on; 446 regulator-max-microvolt = <1875000>; 447 regulator-min-microvolt = <300000>; 448 regulator-ramp-delay = <6250>; 449 }; 450 451 sw3a_reg: sw3a { 452 regulator-always-on; 453 regulator-boot-on; 454 regulator-max-microvolt = <1975000>; 455 regulator-min-microvolt = <400000>; 456 }; 457 458 swbst_reg: swbst { 459 regulator-always-on; 460 regulator-boot-on; 461 regulator-max-microvolt = <5150000>; 462 regulator-min-microvolt = <5000000>; 463 }; 464 465 snvs_reg: vsnvs { 466 regulator-always-on; 467 regulator-boot-on; 468 regulator-max-microvolt = <3000000>; 469 regulator-min-microvolt = <1000000>; 470 }; 471 472 vref_reg: vrefddr { 473 regulator-always-on; 474 regulator-boot-on; 475 }; 476 477 /* vgen1: unused */ 478 479 vgen2_reg: vgen2 { 480 regulator-always-on; 481 regulator-boot-on; 482 regulator-max-microvolt = <1550000>; 483 regulator-min-microvolt = <800000>; 484 }; 485 486 /* 487 * +V3.3_1.8_SD1 coming off VGEN3 and supplying 488 * the i.MX 6 NVCC_SD1. 489 */ 490 vgen3_reg: vgen3 { 491 regulator-always-on; 492 regulator-boot-on; 493 regulator-max-microvolt = <3300000>; 494 regulator-min-microvolt = <1800000>; 495 }; 496 497 vgen4_reg: vgen4 { 498 regulator-always-on; 499 regulator-boot-on; 500 regulator-max-microvolt = <1800000>; 501 regulator-min-microvolt = <1800000>; 502 }; 503 504 vgen5_reg: vgen5 { 505 regulator-always-on; 506 regulator-boot-on; 507 regulator-max-microvolt = <3300000>; 508 regulator-min-microvolt = <1800000>; 509 }; 510 511 vgen6_reg: vgen6 { 512 regulator-always-on; 513 regulator-boot-on; 514 regulator-max-microvolt = <3300000>; 515 regulator-min-microvolt = <1800000>; 516 }; 517 }; 518 }; 519 520 codec: sgtl5000@a { 521 compatible = "fsl,sgtl5000"; 522 clocks = <&clks IMX6QDL_CLK_CKO>; 523 lrclk-strength = <3>; 524 pinctrl-names = "default"; 525 pinctrl-0 = <&pinctrl_sgtl5000>; 526 reg = <0x0a>; 527 #sound-dai-cells = <0>; 528 VDDA-supply = <®_module_3v3_audio>; 529 VDDIO-supply = <®_module_3v3>; 530 VDDD-supply = <&vgen4_reg>; 531 }; 532 533 /* STMPE811 touch screen controller */ 534 stmpe811@41 { 535 compatible = "st,stmpe811"; 536 blocks = <0x5>; 537 interrupts = <20 IRQ_TYPE_LEVEL_LOW>; 538 interrupt-parent = <&gpio6>; 539 interrupt-controller; 540 id = <0>; 541 irq-trigger = <0x1>; 542 pinctrl-names = "default"; 543 pinctrl-0 = <&pinctrl_touch_int>; 544 reg = <0x41>; 545 /* 3.25 MHz ADC clock speed */ 546 st,adc-freq = <1>; 547 /* 12-bit ADC */ 548 st,mod-12b = <1>; 549 /* internal ADC reference */ 550 st,ref-sel = <0>; 551 /* ADC converstion time: 80 clocks */ 552 st,sample-time = <4>; 553 554 stmpe_ts: stmpe_touchscreen { 555 compatible = "st,stmpe-ts"; 556 /* 8 sample average control */ 557 st,ave-ctrl = <3>; 558 /* 7 length fractional part in z */ 559 st,fraction-z = <7>; 560 /* 561 * 50 mA typical 80 mA max touchscreen drivers 562 * current limit value 563 */ 564 st,i-drive = <1>; 565 /* 1 ms panel driver settling time */ 566 st,settling = <3>; 567 /* 5 ms touch detect interrupt delay */ 568 st,touch-det-delay = <5>; 569 status = "disabled"; 570 }; 571 572 stmpe_adc: stmpe_adc { 573 compatible = "st,stmpe-adc"; 574 /* forbid to use ADC channels 3-0 (touch) */ 575 st,norequest-mask = <0x0F>; 576 }; 577 }; 578 }; 579 580 /* 581 * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) 582 */ 583 &i2c3 { 584 clock-frequency = <100000>; 585 pinctrl-names = "default", "gpio"; 586 pinctrl-0 = <&pinctrl_i2c3>; 587 pinctrl-1 = <&pinctrl_i2c3_gpio>; 588 scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 589 sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 590 status = "disabled"; 591 592 atmel_mxt_ts: touchscreen@4a { 593 compatible = "atmel,maxtouch"; 594 interrupt-parent = <&gpio2>; 595 interrupts = <24 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */ 596 pinctrl-names = "default"; 597 pinctrl-0 = <&pinctrl_atmel_conn>; 598 reg = <0x4a>; 599 reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* SODIMM 106 */ 600 status = "disabled"; 601 }; 602 }; 603 604 &ipu1_di0_disp0 { 605 remote-endpoint = <&lcd_display_in>; 606 }; 607 608 /* Colibri PWM<B> */ 609 &pwm1 { 610 pinctrl-names = "default"; 611 pinctrl-0 = <&pinctrl_pwm1>; 612 status = "disabled"; 613 }; 614 615 /* Colibri PWM<D> */ 616 &pwm2 { 617 pinctrl-names = "default"; 618 pinctrl-0 = <&pinctrl_pwm2>; 619 status = "disabled"; 620 }; 621 622 /* Colibri PWM<A> */ 623 &pwm3 { 624 pinctrl-names = "default"; 625 pinctrl-0 = <&pinctrl_pwm3>; 626 status = "disabled"; 627 }; 628 629 /* Colibri PWM<C> */ 630 &pwm4 { 631 pinctrl-names = "default"; 632 pinctrl-0 = <&pinctrl_pwm4>; 633 status = "disabled"; 634 }; 635 636 /* Optional S/PDIF out on SODIMM 137 */ 637 &spdif { 638 pinctrl-names = "default"; 639 pinctrl-0 = <&pinctrl_spdif>; 640 status = "disabled"; 641 }; 642 643 &ssi1 { 644 status = "okay"; 645 }; 646 647 /* Colibri UART_A */ 648 &uart1 { 649 fsl,dte-mode; 650 pinctrl-names = "default"; 651 pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; 652 uart-has-rtscts; 653 status = "disabled"; 654 }; 655 656 /* Colibri UART_B */ 657 &uart2 { 658 fsl,dte-mode; 659 pinctrl-names = "default"; 660 pinctrl-0 = <&pinctrl_uart2_dte>; 661 uart-has-rtscts; 662 status = "disabled"; 663 }; 664 665 /* Colibri UART_C */ 666 &uart3 { 667 fsl,dte-mode; 668 pinctrl-names = "default"; 669 pinctrl-0 = <&pinctrl_uart3_dte>; 670 status = "disabled"; 671 }; 672 673 &usbotg { 674 disable-over-current; 675 dr_mode = "peripheral"; 676 status = "disabled"; 677 }; 678 679 /* Colibri MMC */ 680 &usdhc1 { 681 cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ 682 bus-width = <4>; 683 no-1-8-v; 684 disable-wp; 685 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 686 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; 687 pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>; 688 pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>; 689 pinctrl-3 = <&pinctrl_usdhc1_sleep &pinctrl_mmc_cd_sleep>; 690 vmmc-supply = <®_module_3v3>; 691 vqmmc-supply = <&vgen3_reg>; 692 status = "disabled"; 693 }; 694 695 /* eMMC */ 696 &usdhc3 { 697 bus-width = <8>; 698 no-1-8-v; 699 non-removable; 700 pinctrl-names = "default"; 701 pinctrl-0 = <&pinctrl_usdhc3>; 702 vqmmc-supply = <®_module_3v3>; 703 status = "okay"; 704 }; 705 706 &weim { 707 pinctrl-names = "default"; 708 pinctrl-0 = <&pinctrl_weim_sram &pinctrl_weim_cs0 709 &pinctrl_weim_cs1 &pinctrl_weim_cs2 710 &pinctrl_weim_rdnwr &pinctrl_weim_npwe>; 711 #address-cells = <2>; 712 #size-cells = <1>; 713 status = "disabled"; 714 }; 715 716 &iomuxc { 717 pinctrl-names = "default"; 718 pinctrl-0 = <&pinctrl_usbh_oc_1>; 719 720 /* Atmel MXT touchsceen + Capacitive Touch Adapter */ 721 /* NOTE: This pin group conflicts with pin groups 722 * pinctrl_pwm1/pinctrl_pwm4. Don't use them simultaneously. 723 */ 724 pinctrl_atmel_adap: atmeladaptergrp { 725 fsl,pins = < 726 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0xb0b1 /* SODIMM 28 */ 727 MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0xb0b1 /* SODIMM 30 */ 728 >; 729 }; 730 731 /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */ 732 /* NOTE: This pin group conflicts with pin groups pinctrl_weim_cs1 and 733 * pinctrl_weim_cs2. Don't use them simultaneously. 734 */ 735 pinctrl_atmel_conn: atmelconnectorgrp { 736 fsl,pins = < 737 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0xb0b1 /* SODIMM_107 */ 738 MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0xb0b1 /* SODIMM_106 */ 739 >; 740 }; 741 742 pinctrl_audmux: audmuxgrp { 743 fsl,pins = < 744 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 745 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0 746 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 747 MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 748 >; 749 }; 750 751 pinctrl_cam_mclk: cammclkgrp { 752 fsl,pins = < 753 /* Parallel Camera CAM sys_mclk */ 754 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0 755 >; 756 }; 757 758 /* CSI pins used as GPIOs */ 759 pinctrl_csi_gpio_1: csigpio1grp { 760 fsl,pins = < 761 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 762 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 763 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0 764 MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 765 MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0 766 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 767 MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 768 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 769 MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x1b0b0 770 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 771 MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 772 MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 773 >; 774 }; 775 776 pinctrl_csi_gpio_2: csigpio2grp { 777 fsl,pins = < 778 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 779 >; 780 }; 781 782 pinctrl_ecspi4: ecspi4grp { 783 fsl,pins = < 784 /* SPI CS */ 785 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1 786 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 787 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 788 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 789 >; 790 }; 791 792 pinctrl_enet: enetgrp { 793 fsl,pins = < 794 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 795 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 796 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 797 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 798 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 799 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 800 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 801 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 802 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 803 MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0) 804 >; 805 }; 806 807 pinctrl_flexcan1: flexcan1grp { 808 fsl,pins = < 809 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 810 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 811 >; 812 }; 813 814 pinctrl_flexcan2: flexcan2grp { 815 fsl,pins = < 816 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 817 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 818 >; 819 }; 820 821 pinctrl_gpio_1: gpio1grp { 822 fsl,pins = < 823 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 824 MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b0 825 MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 826 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 827 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 828 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 829 MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 830 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 831 >; 832 }; 833 pinctrl_gpio_2: gpio2grp { 834 fsl,pins = < 835 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 836 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 837 >; 838 }; 839 840 pinctrl_gpio_bl_on: gpioblongrp { 841 fsl,pins = < 842 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 843 >; 844 }; 845 846 pinctrl_gpio_keys: gpiokeysgrp { 847 fsl,pins = < 848 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 849 >; 850 }; 851 852 pinctrl_hdmi_ddc: hdmiddcgrp { 853 fsl,pins = < 854 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 855 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 856 >; 857 }; 858 859 pinctrl_i2c2: i2c2grp { 860 fsl,pins = < 861 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 862 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 863 >; 864 }; 865 866 pinctrl_i2c2_gpio: i2c2gpiogrp { 867 fsl,pins = < 868 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1 869 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1 870 >; 871 }; 872 873 pinctrl_i2c3: i2c3grp { 874 fsl,pins = < 875 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 876 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 877 >; 878 }; 879 880 pinctrl_i2c3_gpio: i2c3gpiogrp { 881 fsl,pins = < 882 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1 883 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 884 >; 885 }; 886 887 pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */ 888 fsl,pins = < 889 MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1 890 MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1 891 MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1 892 MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1 893 MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1 894 MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1 895 MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1 896 MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0xb0b1 897 MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0xb0b1 898 MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1 899 MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1 900 /* Disable PWM pins on camera interface */ 901 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40 902 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40 903 >; 904 }; 905 906 pinctrl_ipu1_lcdif: ipu1lcdifgrp { 907 fsl,pins = < 908 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xa1 909 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xa1 910 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xa1 911 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xa1 912 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xa1 913 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xa1 914 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xa1 915 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xa1 916 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xa1 917 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xa1 918 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xa1 919 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xa1 920 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xa1 921 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xa1 922 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xa1 923 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xa1 924 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xa1 925 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xa1 926 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xa1 927 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xa1 928 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xa1 929 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1 930 >; 931 }; 932 933 pinctrl_lvds_transceiver: lvdstxgrp { 934 fsl,pins = < 935 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x03030 /* SODIMM 95 */ 936 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0b030 /* SODIMM 55 */ 937 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x03030 /* SODIMM 63 */ 938 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x03030 /* SODIMM 99 */ 939 >; 940 }; 941 942 pinctrl_mic_gnd: micgndgrp { 943 fsl,pins = < 944 /* Controls Mic GND, PU or '1' pull Mic GND to GND */ 945 MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0 946 >; 947 }; 948 949 pinctrl_mmc_cd: mmccdgrp { 950 fsl,pins = < 951 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1 952 >; 953 }; 954 955 pinctrl_mmc_cd_sleep: mmccdslpgrp { 956 fsl,pins = < 957 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0 958 >; 959 }; 960 961 pinctrl_pwm1: pwm1grp { 962 fsl,pins = < 963 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 964 >; 965 }; 966 967 pinctrl_pwm2: pwm2grp { 968 fsl,pins = < 969 MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040 970 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 971 >; 972 }; 973 974 pinctrl_pwm3: pwm3grp { 975 fsl,pins = < 976 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040 977 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 978 >; 979 }; 980 981 pinctrl_pwm4: pwm4grp { 982 fsl,pins = < 983 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 984 >; 985 }; 986 987 pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp { 988 fsl,pins = < 989 /* USBH_EN */ 990 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058 991 >; 992 }; 993 994 pinctrl_sgtl5000: sgtl5000grp { 995 fsl,pins = < 996 /* SGTL5000 sys_mclk */ 997 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 998 >; 999 }; 1000 1001 pinctrl_spdif: spdifgrp { 1002 fsl,pins = < 1003 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 1004 >; 1005 }; 1006 1007 pinctrl_touch_int: gpiotouchintgrp { 1008 fsl,pins = < 1009 /* STMPE811 interrupt */ 1010 MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0 1011 >; 1012 }; 1013 1014 pinctrl_uart1_dce: uart1dcegrp { 1015 fsl,pins = < 1016 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 1017 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 1018 >; 1019 }; 1020 1021 /* DTE mode */ 1022 pinctrl_uart1_dte: uart1dtegrp { 1023 fsl,pins = < 1024 MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 1025 MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 1026 MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 1027 MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 1028 >; 1029 }; 1030 1031 /* Additional DTR, DSR, DCD */ 1032 pinctrl_uart1_ctrl: uart1ctrlgrp { 1033 fsl,pins = < 1034 MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 1035 MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 1036 MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 1037 >; 1038 }; 1039 1040 pinctrl_uart2_dte: uart2dtegrp { 1041 fsl,pins = < 1042 MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 1043 MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 1044 MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 1045 MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 1046 >; 1047 }; 1048 1049 pinctrl_uart3_dte: uart3dtegrp { 1050 fsl,pins = < 1051 MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1 1052 MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1 1053 >; 1054 }; 1055 1056 pinctrl_usbc_det: usbcdetgrp { 1057 fsl,pins = < 1058 /* USBC_DET */ 1059 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 1060 /* USBC_DET_OVERWRITE */ 1061 MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058 1062 /* USBC_DET_EN */ 1063 MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058 1064 >; 1065 }; 1066 1067 pinctrl_usbc_id_1: usbcid1grp { 1068 fsl,pins = < 1069 /* USBC_ID */ 1070 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 1071 >; 1072 }; 1073 1074 pinctrl_usbh_oc_1: usbhoc1grp { 1075 fsl,pins = < 1076 /* USBH_OC */ 1077 MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 1078 >; 1079 }; 1080 1081 pinctrl_usdhc1: usdhc1grp { 1082 fsl,pins = < 1083 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 1084 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 1085 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 1086 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 1087 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 1088 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 1089 >; 1090 }; 1091 1092 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1093 fsl,pins = < 1094 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1 1095 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1 1096 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1 1097 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1 1098 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1 1099 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1 1100 >; 1101 }; 1102 1103 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1104 fsl,pins = < 1105 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1 1106 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1 1107 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1 1108 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1 1109 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1 1110 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1 1111 >; 1112 }; 1113 1114 /* avoid backfeeding with removed card power */ 1115 pinctrl_usdhc1_sleep: usdhc1sleepgrp { 1116 fsl,pins = < 1117 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x3000 1118 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x3000 1119 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x3000 1120 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x3000 1121 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x3000 1122 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x3000 1123 >; 1124 }; 1125 1126 pinctrl_usdhc3: usdhc3grp { 1127 fsl,pins = < 1128 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 1129 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 1130 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 1131 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 1132 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 1133 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 1134 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 1135 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 1136 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 1137 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 1138 /* eMMC reset */ 1139 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 1140 >; 1141 }; 1142 1143 pinctrl_weim_cs0: weimcs0grp { 1144 fsl,pins = < 1145 /* nEXT_CS0 */ 1146 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 1147 >; 1148 }; 1149 1150 pinctrl_weim_cs1: weimcs1grp { 1151 fsl,pins = < 1152 /* nEXT_CS1 */ 1153 MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1 1154 >; 1155 }; 1156 1157 pinctrl_weim_cs2: weimcs2grp { 1158 fsl,pins = < 1159 /* nEXT_CS2 */ 1160 MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1 1161 >; 1162 }; 1163 1164 /* ADDRESS[16:18] [25] used as GPIO */ 1165 pinctrl_weim_gpio_1: weimgpio1grp { 1166 fsl,pins = < 1167 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 1168 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 1169 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 1170 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 1171 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 1172 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 1173 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 1174 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 1175 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 1176 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 1177 >; 1178 }; 1179 1180 /* ADDRESS[19:24] used as GPIO */ 1181 pinctrl_weim_gpio_2: weimgpio2grp { 1182 fsl,pins = < 1183 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 1184 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 1185 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 1186 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 1187 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 1188 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 1189 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 1190 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 1191 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 1192 >; 1193 }; 1194 1195 /* DATA[16:31] used as GPIO */ 1196 pinctrl_weim_gpio_3: weimgpio3grp { 1197 fsl,pins = < 1198 MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0 1199 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 1200 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 1201 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 1202 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 1203 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 1204 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 1205 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 1206 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 1207 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0 1208 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 1209 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 1210 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 1211 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 1212 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 1213 >; 1214 }; 1215 1216 /* DQM[0:3] used as GPIO */ 1217 pinctrl_weim_gpio_4: weimgpio4grp { 1218 fsl,pins = < 1219 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 1220 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 1221 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 1222 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 1223 >; 1224 }; 1225 1226 /* RDY used as GPIO */ 1227 pinctrl_weim_gpio_5: weimgpio5grp { 1228 fsl,pins = < 1229 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 1230 >; 1231 }; 1232 1233 /* ADDRESS[16] DATA[30] used as GPIO */ 1234 pinctrl_weim_gpio_6: weimgpio6grp { 1235 fsl,pins = < 1236 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 1237 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 1238 >; 1239 }; 1240 1241 pinctrl_weim_npwe: weimnpwegrp { 1242 fsl,pins = < 1243 MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0 1244 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040 1245 >; 1246 }; 1247 1248 pinctrl_weim_sram: weimsramgrp { 1249 fsl,pins = < 1250 /* Data */ 1251 MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0 1252 MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0 1253 MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0 1254 MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0 1255 MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0 1256 MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0 1257 MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0 1258 MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0 1259 MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0 1260 MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0 1261 MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0 1262 MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0 1263 MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0 1264 MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0 1265 MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0 1266 MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0 1267 /* Address */ 1268 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 1269 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 1270 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 1271 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 1272 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 1273 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 1274 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 1275 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 1276 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 1277 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 1278 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 1279 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 1280 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 1281 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 1282 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 1283 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 1284 /* Ctrl */ 1285 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 1286 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 1287 >; 1288 }; 1289 1290 pinctrl_weim_rdnwr: weimrdnwrgrp { 1291 fsl,pins = < 1292 MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0 1293 MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040 1294 >; 1295 }; 1296 };
Cache object: 7822f61c477d03d457dae06085876647
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