Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/contrib/device-tree/src/arm/imx6qdl-gw51xx.dtsi
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1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2013 Gateworks Corporation 4 */ 5 6 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/input/linux-event-codes.h> 8 #include <dt-bindings/interrupt-controller/irq.h> 9 10 / { 11 /* these are used by bootloader for disabling nodes */ 12 aliases { 13 led0 = &led0; 14 led1 = &led1; 15 nand = &gpmi; 16 usb0 = &usbh1; 17 usb1 = &usbotg; 18 }; 19 20 chosen { 21 bootargs = "console=ttymxc1,115200"; 22 }; 23 24 gpio-keys { 25 compatible = "gpio-keys"; 26 27 user-pb { 28 label = "user_pb"; 29 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; 30 linux,code = <BTN_0>; 31 }; 32 33 user-pb1x { 34 label = "user_pb1x"; 35 linux,code = <BTN_1>; 36 interrupt-parent = <&gsc>; 37 interrupts = <0>; 38 }; 39 40 key-erased { 41 label = "key-erased"; 42 linux,code = <BTN_2>; 43 interrupt-parent = <&gsc>; 44 interrupts = <1>; 45 }; 46 47 eeprom-wp { 48 label = "eeprom_wp"; 49 linux,code = <BTN_3>; 50 interrupt-parent = <&gsc>; 51 interrupts = <2>; 52 }; 53 54 tamper { 55 label = "tamper"; 56 linux,code = <BTN_4>; 57 interrupt-parent = <&gsc>; 58 interrupts = <5>; 59 }; 60 61 switch-hold { 62 label = "switch_hold"; 63 linux,code = <BTN_5>; 64 interrupt-parent = <&gsc>; 65 interrupts = <7>; 66 }; 67 }; 68 69 leds { 70 compatible = "gpio-leds"; 71 pinctrl-names = "default"; 72 pinctrl-0 = <&pinctrl_gpio_leds>; 73 74 led0: user1 { 75 label = "user1"; 76 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 77 default-state = "on"; 78 linux,default-trigger = "heartbeat"; 79 }; 80 81 led1: user2 { 82 label = "user2"; 83 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 84 default-state = "off"; 85 }; 86 }; 87 88 memory@10000000 { 89 device_type = "memory"; 90 reg = <0x10000000 0x20000000>; 91 }; 92 93 pps { 94 compatible = "pps-gpio"; 95 pinctrl-names = "default"; 96 pinctrl-0 = <&pinctrl_pps>; 97 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 98 status = "okay"; 99 }; 100 101 reg_3p3v: regulator-3p3v { 102 compatible = "regulator-fixed"; 103 regulator-name = "3P3V"; 104 regulator-min-microvolt = <3300000>; 105 regulator-max-microvolt = <3300000>; 106 regulator-always-on; 107 }; 108 109 reg_5p0v: regulator-5p0v { 110 compatible = "regulator-fixed"; 111 regulator-name = "5P0V"; 112 regulator-min-microvolt = <5000000>; 113 regulator-max-microvolt = <5000000>; 114 regulator-always-on; 115 }; 116 117 reg_usb_otg_vbus: regulator-usb-otg-vbus { 118 compatible = "regulator-fixed"; 119 regulator-name = "usb_otg_vbus"; 120 regulator-min-microvolt = <5000000>; 121 regulator-max-microvolt = <5000000>; 122 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 123 enable-active-high; 124 }; 125 }; 126 127 &fec { 128 pinctrl-names = "default"; 129 pinctrl-0 = <&pinctrl_enet>; 130 phy-mode = "rgmii-id"; 131 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; 132 status = "okay"; 133 }; 134 135 &gpmi { 136 pinctrl-names = "default"; 137 pinctrl-0 = <&pinctrl_gpmi_nand>; 138 status = "okay"; 139 }; 140 141 &hdmi { 142 ddc-i2c-bus = <&i2c3>; 143 status = "okay"; 144 }; 145 146 &i2c1 { 147 clock-frequency = <100000>; 148 pinctrl-names = "default"; 149 pinctrl-0 = <&pinctrl_i2c1>; 150 status = "okay"; 151 152 gsc: gsc@20 { 153 compatible = "gw,gsc"; 154 reg = <0x20>; 155 interrupt-parent = <&gpio1>; 156 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 157 interrupt-controller; 158 #interrupt-cells = <1>; 159 #size-cells = <0>; 160 161 adc { 162 compatible = "gw,gsc-adc"; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 166 channel@0 { 167 gw,mode = <0>; 168 reg = <0x00>; 169 label = "temp"; 170 }; 171 172 channel@2 { 173 gw,mode = <1>; 174 reg = <0x02>; 175 label = "vdd_vin"; 176 }; 177 178 channel@5 { 179 gw,mode = <1>; 180 reg = <0x05>; 181 label = "vdd_3p3"; 182 }; 183 184 channel@8 { 185 gw,mode = <1>; 186 reg = <0x08>; 187 label = "vdd_bat"; 188 }; 189 190 channel@b { 191 gw,mode = <1>; 192 reg = <0x0b>; 193 label = "vdd_5p0"; 194 }; 195 196 channel@e { 197 gw,mode = <1>; 198 reg = <0xe>; 199 label = "vdd_arm"; 200 }; 201 202 channel@11 { 203 gw,mode = <1>; 204 reg = <0x11>; 205 label = "vdd_soc"; 206 }; 207 208 channel@14 { 209 gw,mode = <1>; 210 reg = <0x14>; 211 label = "vdd_3p0"; 212 }; 213 214 channel@17 { 215 gw,mode = <1>; 216 reg = <0x17>; 217 label = "vdd_1p5"; 218 }; 219 220 channel@1d { 221 gw,mode = <1>; 222 reg = <0x1d>; 223 label = "vdd_1p8"; 224 }; 225 226 channel@20 { 227 gw,mode = <1>; 228 reg = <0x20>; 229 label = "vdd_an1"; 230 }; 231 232 channel@23 { 233 gw,mode = <1>; 234 reg = <0x23>; 235 label = "vdd_2p5"; 236 }; 237 }; 238 }; 239 240 gsc_gpio: gpio@23 { 241 compatible = "nxp,pca9555"; 242 reg = <0x23>; 243 gpio-controller; 244 #gpio-cells = <2>; 245 interrupt-parent = <&gsc>; 246 interrupts = <4>; 247 }; 248 249 eeprom1: eeprom@50 { 250 compatible = "atmel,24c02"; 251 reg = <0x50>; 252 pagesize = <16>; 253 }; 254 255 eeprom2: eeprom@51 { 256 compatible = "atmel,24c02"; 257 reg = <0x51>; 258 pagesize = <16>; 259 }; 260 261 eeprom3: eeprom@52 { 262 compatible = "atmel,24c02"; 263 reg = <0x52>; 264 pagesize = <16>; 265 }; 266 267 eeprom4: eeprom@53 { 268 compatible = "atmel,24c02"; 269 reg = <0x53>; 270 pagesize = <16>; 271 }; 272 273 rtc: ds1672@68 { 274 compatible = "dallas,ds1672"; 275 reg = <0x68>; 276 }; 277 }; 278 279 &i2c2 { 280 clock-frequency = <100000>; 281 pinctrl-names = "default"; 282 pinctrl-0 = <&pinctrl_i2c2>; 283 status = "okay"; 284 285 ltc3676: pmic@3c { 286 compatible = "lltc,ltc3676"; 287 reg = <0x3c>; 288 pinctrl-names = "default"; 289 pinctrl-0 = <&pinctrl_pmic>; 290 interrupt-parent = <&gpio1>; 291 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 292 293 regulators { 294 /* VDD_SOC (1+R1/R2 = 1.635) */ 295 reg_vdd_soc: sw1 { 296 regulator-name = "vddsoc"; 297 regulator-min-microvolt = <674400>; 298 regulator-max-microvolt = <1308000>; 299 lltc,fb-voltage-divider = <127000 200000>; 300 regulator-ramp-delay = <7000>; 301 regulator-boot-on; 302 regulator-always-on; 303 }; 304 305 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ 306 reg_1p8v: sw2 { 307 regulator-name = "vdd1p8"; 308 regulator-min-microvolt = <1033310>; 309 regulator-max-microvolt = <2004000>; 310 lltc,fb-voltage-divider = <301000 200000>; 311 regulator-ramp-delay = <7000>; 312 regulator-boot-on; 313 regulator-always-on; 314 }; 315 316 /* VDD_ARM (1+R1/R2 = 1.635) */ 317 reg_vdd_arm: sw3 { 318 regulator-name = "vddarm"; 319 regulator-min-microvolt = <674400>; 320 regulator-max-microvolt = <1308000>; 321 lltc,fb-voltage-divider = <127000 200000>; 322 regulator-ramp-delay = <7000>; 323 regulator-boot-on; 324 regulator-always-on; 325 }; 326 327 /* VDD_DDR (1+R1/R2 = 2.105) */ 328 reg_vdd_ddr: sw4 { 329 regulator-name = "vddddr"; 330 regulator-min-microvolt = <868310>; 331 regulator-max-microvolt = <1684000>; 332 lltc,fb-voltage-divider = <221000 200000>; 333 regulator-ramp-delay = <7000>; 334 regulator-boot-on; 335 regulator-always-on; 336 }; 337 338 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ 339 reg_2p5v: ldo2 { 340 regulator-name = "vdd2p5"; 341 regulator-min-microvolt = <2490375>; 342 regulator-max-microvolt = <2490375>; 343 lltc,fb-voltage-divider = <487000 200000>; 344 regulator-boot-on; 345 regulator-always-on; 346 }; 347 348 /* VDD_HIGH (1+R1/R2 = 4.17) */ 349 reg_3p0v: ldo4 { 350 regulator-name = "vdd3p0"; 351 regulator-min-microvolt = <3023250>; 352 regulator-max-microvolt = <3023250>; 353 lltc,fb-voltage-divider = <634000 200000>; 354 regulator-boot-on; 355 regulator-always-on; 356 }; 357 }; 358 }; 359 }; 360 361 &i2c3 { 362 clock-frequency = <100000>; 363 pinctrl-names = "default"; 364 pinctrl-0 = <&pinctrl_i2c3>; 365 status = "okay"; 366 367 adv7180: camera@20 { 368 compatible = "adi,adv7180"; 369 pinctrl-names = "default"; 370 pinctrl-0 = <&pinctrl_adv7180>; 371 reg = <0x20>; 372 powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; 373 interrupt-parent = <&gpio5>; 374 interrupts = <23 IRQ_TYPE_LEVEL_LOW>; 375 376 port { 377 adv7180_to_ipu1_csi0_mux: endpoint { 378 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; 379 bus-width = <8>; 380 }; 381 }; 382 }; 383 }; 384 385 &ipu1_csi0_from_ipu1_csi0_mux { 386 bus-width = <8>; 387 }; 388 389 &ipu1_csi0_mux_from_parallel_sensor { 390 remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; 391 bus-width = <8>; 392 }; 393 394 &ipu1_csi0 { 395 pinctrl-names = "default"; 396 pinctrl-0 = <&pinctrl_ipu1_csi0>; 397 }; 398 399 &pcie { 400 pinctrl-names = "default"; 401 pinctrl-0 = <&pinctrl_pcie>; 402 reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; 403 status = "okay"; 404 }; 405 406 &pwm2 { 407 pinctrl-names = "default"; 408 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 409 status = "disabled"; 410 }; 411 412 &pwm3 { 413 pinctrl-names = "default"; 414 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 415 status = "disabled"; 416 }; 417 418 &pwm4 { 419 pinctrl-names = "default"; 420 pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ 421 status = "disabled"; 422 }; 423 424 &uart1 { 425 pinctrl-names = "default"; 426 pinctrl-0 = <&pinctrl_uart1>; 427 status = "okay"; 428 }; 429 430 &uart2 { 431 pinctrl-names = "default"; 432 pinctrl-0 = <&pinctrl_uart2>; 433 status = "okay"; 434 }; 435 436 &uart3 { 437 pinctrl-names = "default"; 438 pinctrl-0 = <&pinctrl_uart3>; 439 status = "okay"; 440 }; 441 442 &uart5 { 443 pinctrl-names = "default"; 444 pinctrl-0 = <&pinctrl_uart5>; 445 status = "okay"; 446 }; 447 448 &usbotg { 449 vbus-supply = <®_usb_otg_vbus>; 450 pinctrl-names = "default"; 451 pinctrl-0 = <&pinctrl_usbotg>; 452 disable-over-current; 453 status = "okay"; 454 }; 455 456 &usbh1 { 457 status = "okay"; 458 }; 459 460 &wdog1 { 461 pinctrl-names = "default"; 462 pinctrl-0 = <&pinctrl_wdog>; 463 fsl,ext-reset-output; 464 }; 465 466 &iomuxc { 467 pinctrl_adv7180: adv7180grp { 468 fsl,pins = < 469 MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0 470 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0 471 >; 472 }; 473 474 pinctrl_enet: enetgrp { 475 fsl,pins = < 476 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 477 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 478 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 479 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 480 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 481 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 482 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 483 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 484 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 485 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 486 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 487 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 488 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 489 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 490 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 491 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 492 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ 493 >; 494 }; 495 496 pinctrl_gpio_leds: gpioledsgrp { 497 fsl,pins = < 498 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 499 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 500 >; 501 }; 502 503 pinctrl_gpmi_nand: gpminandgrp { 504 fsl,pins = < 505 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 506 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 507 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 508 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 509 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 510 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 511 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 512 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 513 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 514 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 515 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 516 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 517 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 518 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 519 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 520 >; 521 }; 522 523 pinctrl_i2c1: i2c1grp { 524 fsl,pins = < 525 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 526 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 527 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */ 528 >; 529 }; 530 531 pinctrl_i2c2: i2c2grp { 532 fsl,pins = < 533 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 534 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 535 >; 536 }; 537 538 pinctrl_i2c3: i2c3grp { 539 fsl,pins = < 540 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 541 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 542 >; 543 }; 544 545 pinctrl_ipu1_csi0: ipu1csi0grp { 546 fsl,pins = < 547 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 548 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 549 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 550 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 551 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 552 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 553 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 554 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 555 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 556 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 557 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 558 >; 559 }; 560 561 pinctrl_pcie: pciegrp { 562 fsl,pins = < 563 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 564 >; 565 }; 566 567 pinctrl_pmic: pmicgrp { 568 fsl,pins = < 569 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 570 >; 571 }; 572 573 pinctrl_pps: ppsgrp { 574 fsl,pins = < 575 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 576 >; 577 }; 578 579 pinctrl_pwm2: pwm2grp { 580 fsl,pins = < 581 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 582 >; 583 }; 584 585 pinctrl_pwm3: pwm3grp { 586 fsl,pins = < 587 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 588 >; 589 }; 590 591 pinctrl_pwm4: pwm4grp { 592 fsl,pins = < 593 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 594 >; 595 }; 596 597 pinctrl_uart1: uart1grp { 598 fsl,pins = < 599 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 600 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 601 >; 602 }; 603 604 pinctrl_uart2: uart2grp { 605 fsl,pins = < 606 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 607 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 608 >; 609 }; 610 611 pinctrl_uart3: uart3grp { 612 fsl,pins = < 613 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 614 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 615 >; 616 }; 617 618 pinctrl_uart5: uart5grp { 619 fsl,pins = < 620 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 621 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 622 >; 623 }; 624 625 pinctrl_usbotg: usbotggrp { 626 fsl,pins = < 627 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 628 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ 629 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x17059 630 >; 631 }; 632 633 pinctrl_wdog: wdoggrp { 634 fsl,pins = < 635 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 636 >; 637 }; 638 };
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