Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/imx6qdl-gw5912.dtsi
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1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2019 Gateworks Corporation 4 */ 5 6 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/input/linux-event-codes.h> 8 #include <dt-bindings/interrupt-controller/irq.h> 9 10 / { 11 /* these are used by bootloader for disabling nodes */ 12 aliases { 13 led0 = &led0; 14 led1 = &led1; 15 led2 = &led2; 16 nand = &gpmi; 17 usb0 = &usbh1; 18 usb1 = &usbotg; 19 }; 20 21 chosen { 22 stdout-path = &uart2; 23 }; 24 25 gpio-keys { 26 compatible = "gpio-keys"; 27 28 user-pb { 29 label = "user_pb"; 30 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; 31 linux,code = <BTN_0>; 32 }; 33 34 user-pb1x { 35 label = "user_pb1x"; 36 linux,code = <BTN_1>; 37 interrupt-parent = <&gsc>; 38 interrupts = <0>; 39 }; 40 41 key-erased { 42 label = "key-erased"; 43 linux,code = <BTN_2>; 44 interrupt-parent = <&gsc>; 45 interrupts = <1>; 46 }; 47 48 eeprom-wp { 49 label = "eeprom_wp"; 50 linux,code = <BTN_3>; 51 interrupt-parent = <&gsc>; 52 interrupts = <2>; 53 }; 54 55 tamper { 56 label = "tamper"; 57 linux,code = <BTN_4>; 58 interrupt-parent = <&gsc>; 59 interrupts = <5>; 60 }; 61 62 switch-hold { 63 label = "switch_hold"; 64 linux,code = <BTN_5>; 65 interrupt-parent = <&gsc>; 66 interrupts = <7>; 67 }; 68 }; 69 70 leds { 71 compatible = "gpio-leds"; 72 pinctrl-names = "default"; 73 pinctrl-0 = <&pinctrl_gpio_leds>; 74 75 led0: user1 { 76 label = "user1"; 77 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 78 default-state = "on"; 79 linux,default-trigger = "heartbeat"; 80 }; 81 82 led1: user2 { 83 label = "user2"; 84 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 85 default-state = "off"; 86 }; 87 88 led2: user3 { 89 label = "user3"; 90 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ 91 default-state = "off"; 92 }; 93 }; 94 95 memory@10000000 { 96 device_type = "memory"; 97 reg = <0x10000000 0x40000000>; 98 }; 99 100 pps { 101 compatible = "pps-gpio"; 102 pinctrl-names = "default"; 103 pinctrl-0 = <&pinctrl_pps>; 104 gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; 105 }; 106 107 reg_3p3v: regulator-3p3v { 108 compatible = "regulator-fixed"; 109 regulator-name = "3P3V"; 110 regulator-min-microvolt = <3300000>; 111 regulator-max-microvolt = <3300000>; 112 regulator-always-on; 113 }; 114 115 reg_usb_vbus: regulator-5p0v { 116 compatible = "regulator-fixed"; 117 regulator-name = "usb_vbus"; 118 regulator-min-microvolt = <5000000>; 119 regulator-max-microvolt = <5000000>; 120 regulator-always-on; 121 }; 122 }; 123 124 &can1 { 125 pinctrl-names = "default"; 126 pinctrl-0 = <&pinctrl_flexcan1>; 127 status = "okay"; 128 }; 129 130 &ecspi2 { 131 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; 132 pinctrl-names = "default"; 133 pinctrl-0 = <&pinctrl_ecspi2>; 134 status = "okay"; 135 }; 136 137 &fec { 138 pinctrl-names = "default"; 139 pinctrl-0 = <&pinctrl_enet>; 140 phy-mode = "rgmii-id"; 141 status = "okay"; 142 }; 143 144 &gpmi { 145 pinctrl-names = "default"; 146 pinctrl-0 = <&pinctrl_gpmi_nand>; 147 status = "okay"; 148 }; 149 150 &i2c1 { 151 clock-frequency = <100000>; 152 pinctrl-names = "default"; 153 pinctrl-0 = <&pinctrl_i2c1>; 154 status = "okay"; 155 156 gsc: gsc@20 { 157 compatible = "gw,gsc"; 158 reg = <0x20>; 159 interrupt-parent = <&gpio1>; 160 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 161 interrupt-controller; 162 #interrupt-cells = <1>; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 166 adc { 167 compatible = "gw,gsc-adc"; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 171 channel@0 { 172 gw,mode = <0>; 173 reg = <0x00>; 174 label = "temp"; 175 }; 176 177 channel@2 { 178 gw,mode = <1>; 179 reg = <0x02>; 180 label = "vdd_vin"; 181 }; 182 183 channel@5 { 184 gw,mode = <1>; 185 reg = <0x05>; 186 label = "vdd_3p3"; 187 }; 188 189 channel@8 { 190 gw,mode = <1>; 191 reg = <0x08>; 192 label = "vdd_bat"; 193 }; 194 195 channel@b { 196 gw,mode = <1>; 197 reg = <0x0b>; 198 label = "vdd_5p0"; 199 }; 200 201 channel@e { 202 gw,mode = <1>; 203 reg = <0xe>; 204 label = "vdd_arm"; 205 }; 206 207 channel@11 { 208 gw,mode = <1>; 209 reg = <0x11>; 210 label = "vdd_soc"; 211 }; 212 213 channel@14 { 214 gw,mode = <1>; 215 reg = <0x14>; 216 label = "vdd_3p0"; 217 }; 218 219 channel@17 { 220 gw,mode = <1>; 221 reg = <0x17>; 222 label = "vdd_1p5"; 223 }; 224 225 channel@1d { 226 gw,mode = <1>; 227 reg = <0x1d>; 228 label = "vdd_1p8"; 229 }; 230 231 channel@20 { 232 gw,mode = <1>; 233 reg = <0x20>; 234 label = "vdd_1p0"; 235 }; 236 237 channel@23 { 238 gw,mode = <1>; 239 reg = <0x23>; 240 label = "vdd_2p5"; 241 }; 242 }; 243 244 fan-controller@a { 245 compatible = "gw,gsc-fan"; 246 #address-cells = <1>; 247 #size-cells = <0>; 248 reg = <0x0a>; 249 }; 250 }; 251 252 gsc_gpio: gpio@23 { 253 compatible = "nxp,pca9555"; 254 reg = <0x23>; 255 gpio-controller; 256 #gpio-cells = <2>; 257 interrupt-parent = <&gsc>; 258 interrupts = <4>; 259 }; 260 261 eeprom@50 { 262 compatible = "atmel,24c02"; 263 reg = <0x50>; 264 pagesize = <16>; 265 }; 266 267 eeprom@51 { 268 compatible = "atmel,24c02"; 269 reg = <0x51>; 270 pagesize = <16>; 271 }; 272 273 eeprom@52 { 274 compatible = "atmel,24c02"; 275 reg = <0x52>; 276 pagesize = <16>; 277 }; 278 279 eeprom@53 { 280 compatible = "atmel,24c02"; 281 reg = <0x53>; 282 pagesize = <16>; 283 }; 284 285 rtc@68 { 286 compatible = "dallas,ds1672"; 287 reg = <0x68>; 288 }; 289 }; 290 291 &i2c2 { 292 clock-frequency = <100000>; 293 pinctrl-names = "default"; 294 pinctrl-0 = <&pinctrl_i2c2>; 295 status = "okay"; 296 }; 297 298 &i2c3 { 299 clock-frequency = <100000>; 300 pinctrl-names = "default"; 301 pinctrl-0 = <&pinctrl_i2c3>; 302 status = "okay"; 303 304 accel@19 { 305 pinctrl-names = "default"; 306 pinctrl-0 = <&pinctrl_accel>; 307 compatible = "st,lis2de12"; 308 reg = <0x19>; 309 st,drdy-int-pin = <1>; 310 interrupt-parent = <&gpio7>; 311 interrupts = <13 0>; 312 interrupt-names = "INT1"; 313 }; 314 }; 315 316 &pcie { 317 pinctrl-names = "default"; 318 pinctrl-0 = <&pinctrl_pcie>; 319 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; 320 status = "okay"; 321 }; 322 323 &pwm1 { 324 pinctrl-names = "default"; 325 pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */ 326 status = "disabled"; 327 }; 328 329 &pwm2 { 330 pinctrl-names = "default"; 331 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 332 status = "disabled"; 333 }; 334 335 &pwm3 { 336 pinctrl-names = "default"; 337 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 338 status = "disabled"; 339 }; 340 341 &pwm4 { 342 pinctrl-names = "default"; 343 pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ 344 status = "disabled"; 345 }; 346 347 &uart1 { 348 pinctrl-names = "default"; 349 pinctrl-0 = <&pinctrl_uart1>; 350 rts-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>; 351 status = "okay"; 352 }; 353 354 &uart2 { 355 pinctrl-names = "default"; 356 pinctrl-0 = <&pinctrl_uart2>; 357 status = "okay"; 358 }; 359 360 &uart5 { 361 pinctrl-names = "default"; 362 pinctrl-0 = <&pinctrl_uart5>; 363 status = "okay"; 364 }; 365 366 &usbotg { 367 vbus-supply = <®_usb_vbus>; 368 pinctrl-names = "default"; 369 pinctrl-0 = <&pinctrl_usbotg>; 370 disable-over-current; 371 dr_mode = "host"; 372 status = "okay"; 373 }; 374 375 &usbh1 { 376 vbus-supply = <®_usb_vbus>; 377 status = "okay"; 378 }; 379 380 &usdhc3 { 381 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 382 pinctrl-0 = <&pinctrl_usdhc3>; 383 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 384 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 385 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; 386 vmmc-supply = <®_3p3v>; 387 no-1-8-v; /* firmware will remove if board revision supports */ 388 status = "okay"; 389 }; 390 391 &wdog1 { 392 status = "disabled"; 393 }; 394 395 &wdog2 { 396 pinctrl-names = "default"; 397 pinctrl-0 = <&pinctrl_wdog>; 398 fsl,ext-reset-output; 399 status = "okay"; 400 }; 401 402 &iomuxc { 403 pinctrl_accel: accelmuxgrp { 404 fsl,pins = < 405 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1 406 >; 407 }; 408 409 pinctrl_enet: enetgrp { 410 fsl,pins = < 411 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 412 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 413 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 414 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 415 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 416 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 417 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 418 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 419 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 420 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 421 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 422 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 423 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 424 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 425 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 426 >; 427 }; 428 429 pinctrl_ecspi2: escpi2grp { 430 fsl,pins = < 431 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 432 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 433 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 434 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 435 >; 436 }; 437 438 pinctrl_flexcan1: flexcan1grp { 439 fsl,pins = < 440 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 441 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 442 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 443 >; 444 }; 445 446 pinctrl_gpio_leds: gpioledsgrp { 447 fsl,pins = < 448 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 449 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 450 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 451 >; 452 }; 453 454 pinctrl_gpmi_nand: gpminandgrp { 455 fsl,pins = < 456 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 457 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 458 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 459 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 460 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 461 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 462 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 463 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 464 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 465 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 466 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 467 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 468 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 469 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 470 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 471 >; 472 }; 473 474 pinctrl_i2c1: i2c1grp { 475 fsl,pins = < 476 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 477 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 478 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 479 >; 480 }; 481 482 pinctrl_i2c2: i2c2grp { 483 fsl,pins = < 484 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 485 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 486 >; 487 }; 488 489 pinctrl_i2c3: i2c3grp { 490 fsl,pins = < 491 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 492 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 493 >; 494 }; 495 496 pinctrl_pcie: pciegrp { 497 fsl,pins = < 498 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 499 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 500 >; 501 }; 502 503 pinctrl_pps: ppsgrp { 504 fsl,pins = < 505 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1 506 >; 507 }; 508 509 pinctrl_pwm1: pwm1grp { 510 fsl,pins = < 511 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 512 >; 513 }; 514 515 pinctrl_pwm2: pwm2grp { 516 fsl,pins = < 517 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 518 >; 519 }; 520 521 pinctrl_pwm3: pwm3grp { 522 fsl,pins = < 523 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 524 >; 525 }; 526 527 pinctrl_pwm4: pwm4grp { 528 fsl,pins = < 529 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 530 >; 531 }; 532 533 pinctrl_uart1: uart1grp { 534 fsl,pins = < 535 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 536 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 537 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b1 538 >; 539 }; 540 541 pinctrl_uart2: uart2grp { 542 fsl,pins = < 543 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 544 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 545 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b1 546 >; 547 }; 548 549 pinctrl_uart5: uart5grp { 550 fsl,pins = < 551 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 552 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 553 >; 554 }; 555 556 pinctrl_usbotg: usbotggrp { 557 fsl,pins = < 558 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 559 >; 560 }; 561 562 pinctrl_usdhc3: usdhc3grp { 563 fsl,pins = < 564 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 565 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 566 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 567 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 568 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 569 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 570 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ 571 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 572 >; 573 }; 574 575 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 576 fsl,pins = < 577 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 578 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 579 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 580 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 581 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 582 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 583 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ 584 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 585 >; 586 }; 587 588 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 589 fsl,pins = < 590 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 591 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 592 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 593 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 594 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 595 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 596 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ 597 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 598 >; 599 }; 600 601 pinctrl_wdog: wdoggrp { 602 fsl,pins = < 603 MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0 604 >; 605 }; 606 };
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