Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/imx6qdl-icore-rqs.dtsi
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 // SPDX-License-Identifier: GPL-2.0 OR X11 2 /* 3 * Copyright (C) 2015 Amarula Solutions B.V. 4 * Copyright (C) 2015 Engicam S.r.l. 5 */ 6 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/clock/imx6qdl-clock.h> 9 #include <dt-bindings/sound/fsl-imx-audmux.h> 10 11 / { 12 memory@10000000 { 13 device_type = "memory"; 14 reg = <0x10000000 0x80000000>; 15 }; 16 17 reg_1p8v: regulator-1p8v { 18 compatible = "regulator-fixed"; 19 regulator-name = "1P8V"; 20 regulator-min-microvolt = <1800000>; 21 regulator-max-microvolt = <1800000>; 22 regulator-boot-on; 23 regulator-always-on; 24 }; 25 26 reg_2p5v: regulator-2p5v { 27 compatible = "regulator-fixed"; 28 regulator-name = "2P5V"; 29 regulator-min-microvolt = <2500000>; 30 regulator-max-microvolt = <2500000>; 31 regulator-boot-on; 32 regulator-always-on; 33 }; 34 35 reg_3p3v: regulator-3p3v { 36 compatible = "regulator-fixed"; 37 regulator-name = "3P3V"; 38 regulator-min-microvolt = <3300000>; 39 regulator-max-microvolt = <3300000>; 40 regulator-boot-on; 41 regulator-always-on; 42 }; 43 44 reg_sd3_vmmc: regulator-sd3-vmmc { 45 compatible = "regulator-fixed"; 46 regulator-name = "P3V3_SD3_SWITCHED"; 47 regulator-min-microvolt = <3300000>; 48 regulator-max-microvolt = <3300000>; 49 gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; 50 enable-active-high; 51 }; 52 53 reg_sd4_vmmc: regulator-sd4-vmmc { 54 compatible = "regulator-fixed"; 55 regulator-name = "P3V3_SD4_SWITCHED"; 56 regulator-min-microvolt = <3300000>; 57 regulator-max-microvolt = <3300000>; 58 regulator-boot-on; 59 regulator-always-on; 60 }; 61 62 reg_usb_h1_vbus: regulator-usb-h1-vbus { 63 compatible = "regulator-fixed"; 64 regulator-name = "usb_h1_vbus"; 65 regulator-min-microvolt = <5000000>; 66 regulator-max-microvolt = <5000000>; 67 regulator-boot-on; 68 regulator-always-on; 69 }; 70 71 reg_usb_otg_vbus: regulator-usb-otg-vbus { 72 compatible = "regulator-fixed"; 73 regulator-name = "usb_otg_vbus"; 74 regulator-min-microvolt = <5000000>; 75 regulator-max-microvolt = <5000000>; 76 regulator-boot-on; 77 regulator-always-on; 78 }; 79 80 usb_hub: usb-hub { 81 compatible = "smsc,usb3503a"; 82 pinctrl-names = "default"; 83 pinctrl-0 = <&pinctrl_usbhub>; 84 reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; 85 clocks = <&clks IMX6QDL_CLK_LVDS2_GATE>; 86 clock-names = "refclk"; 87 }; 88 89 sound { 90 compatible = "simple-audio-card"; 91 simple-audio-card,name = "imx6qdl-icore-rqs-sgtl5000"; 92 simple-audio-card,format = "i2s"; 93 simple-audio-card,bitclock-master = <&dailink_master>; 94 simple-audio-card,frame-master = <&dailink_master>; 95 simple-audio-card,widgets = 96 "Microphone", "Mic Jack", 97 "Headphone", "Headphone Jack", 98 "Line", "Line In Jack", 99 "Speaker", "Line Out Jack", 100 "Speaker", "Ext Spk"; 101 simple-audio-card,routing = 102 "MIC_IN", "Mic Jack", 103 "Mic Jack", "Mic Bias", 104 "Headphone Jack", "HP_OUT"; 105 106 simple-audio-card,cpu { 107 sound-dai = <&ssi1>; 108 }; 109 110 dailink_master: simple-audio-card,codec { 111 sound-dai = <&sgtl5000>; 112 }; 113 }; 114 }; 115 116 &audmux { 117 pinctrl-names = "default"; 118 pinctrl-0 = <&pinctrl_audmux>; 119 status = "okay"; 120 121 audmux_ssi1 { 122 fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>; 123 fsl,port-config = < 124 (IMX_AUDMUX_V2_PTCR_TFSDIR | 125 IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) | 126 IMX_AUDMUX_V2_PTCR_TCLKDIR | 127 IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) | 128 IMX_AUDMUX_V2_PTCR_SYN) 129 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4) 130 >; 131 }; 132 133 audmux_aud4 { 134 fsl,audmux-port = <MX51_AUDMUX_PORT4>; 135 fsl,port-config = < 136 IMX_AUDMUX_V2_PTCR_SYN 137 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) 138 >; 139 }; 140 }; 141 142 &can1 { 143 pinctrl-names = "default"; 144 pinctrl-0 = <&pinctrl_can1>; 145 xceiver-supply = <®_3p3v>; 146 status = "okay"; 147 }; 148 149 &can2 { 150 pinctrl-names = "default"; 151 pinctrl-0 = <&pinctrl_can2>; 152 xceiver-supply = <®_3p3v>; 153 status = "okay"; 154 }; 155 156 &clks { 157 assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>; 158 assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>; 159 }; 160 161 &fec { 162 pinctrl-names = "default"; 163 pinctrl-0 = <&pinctrl_enet>; 164 phy-handle = <ð_phy>; 165 phy-mode = "rgmii"; 166 status = "okay"; 167 168 mdio { 169 #address-cells = <1>; 170 #size-cells = <0>; 171 172 eth_phy: ethernet-phy@0 { 173 reg = <0x0>; 174 rxc-skew-ps = <1140>; 175 txc-skew-ps = <1140>; 176 txen-skew-ps = <600>; 177 rxdv-skew-ps = <240>; 178 rxd0-skew-ps = <420>; 179 rxd1-skew-ps = <600>; 180 rxd2-skew-ps = <420>; 181 rxd3-skew-ps = <240>; 182 txd0-skew-ps = <60>; 183 txd1-skew-ps = <60>; 184 txd2-skew-ps = <60>; 185 txd3-skew-ps = <240>; 186 }; 187 }; 188 }; 189 190 &i2c1 { 191 clock-frequency = <100000>; 192 pinctrl-names = "default"; 193 pinctrl-0 = <&pinctrl_i2c1>; 194 status = "okay"; 195 }; 196 197 &i2c2 { 198 clock-frequency = <100000>; 199 pinctrl-names = "default"; 200 pinctrl-0 = <&pinctrl_i2c2>; 201 status = "okay"; 202 }; 203 204 &i2c3 { 205 pinctrl-names = "default"; 206 pinctrl-0 = <&pinctrl_i2c3>; 207 status = "okay"; 208 209 sgtl5000: codec@a { 210 #sound-dai-cells = <0>; 211 compatible = "fsl,sgtl5000"; 212 reg = <0x0a>; 213 clocks = <&clks IMX6QDL_CLK_CKO>; 214 VDDA-supply = <®_2p5v>; 215 VDDIO-supply = <®_3p3v>; 216 VDDD-supply = <®_1p8v>; 217 }; 218 }; 219 220 &pcie { 221 pinctrl-names = "default"; 222 pinctrl-0 = <&pinctrl_pcie>; 223 reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>; 224 status = "okay"; 225 }; 226 227 &ssi1 { 228 fsl,mode = "i2s-slave"; 229 status = "okay"; 230 }; 231 232 &uart4 { 233 pinctrl-names = "default"; 234 pinctrl-0 = <&pinctrl_uart4>; 235 status = "okay"; 236 }; 237 238 &usbh1 { 239 vbus-supply = <®_usb_h1_vbus>; 240 disable-over-current; 241 clocks = <&clks IMX6QDL_CLK_USBOH3>; 242 status = "okay"; 243 }; 244 245 &usbotg { 246 vbus-supply = <®_usb_otg_vbus>; 247 pinctrl-names = "default"; 248 pinctrl-0 = <&pinctrl_usbotg>; 249 disable-over-current; 250 status = "okay"; 251 }; 252 253 &usdhc1 { 254 pinctrl-names = "default"; 255 pinctrl-0 = <&pinctrl_usdhc1>; 256 no-1-8-v; 257 status = "okay"; 258 }; 259 260 &usdhc3 { 261 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 262 pinctrl-0 = <&pinctrl_usdhc3>; 263 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 264 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 265 vmcc-supply = <®_sd3_vmmc>; 266 cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 267 bus-width = <4>; 268 no-1-8-v; 269 status = "okay"; 270 }; 271 272 &usdhc4 { 273 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 274 pinctrl-0 = <&pinctrl_usdhc4>; 275 pinctrl-1 = <&pinctrl_usdhc4_100mhz>; 276 pinctrl-2 = <&pinctrl_usdhc4_200mhz>; 277 vmcc-supply = <®_sd4_vmmc>; 278 bus-width = <8>; 279 no-1-8-v; 280 non-removable; 281 status = "okay"; 282 }; 283 284 &iomuxc { 285 pinctrl_audmux: audmuxgrp { 286 fsl,pins = < 287 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 288 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0 289 MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 290 MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 291 >; 292 }; 293 294 pinctrl_enet: enetgrp { 295 fsl,pins = < 296 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 297 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 298 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 299 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 300 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 301 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 302 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 303 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 304 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 305 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 306 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 307 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 308 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 309 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 310 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 311 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 312 >; 313 }; 314 315 pinctrl_can1: can1grp { 316 fsl,pins = < 317 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020 318 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020 319 >; 320 }; 321 322 pinctrl_can2: can2grp { 323 fsl,pins = < 324 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020 325 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020 326 >; 327 }; 328 329 pinctrl_i2c1: i2c1grp { 330 fsl,pins = < 331 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 332 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 333 >; 334 }; 335 336 pinctrl_i2c2: i2c2grp { 337 fsl,pins = < 338 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 339 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 340 >; 341 }; 342 343 pinctrl_i2c3: i2c3grp { 344 fsl,pins = < 345 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 346 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 347 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 348 >; 349 }; 350 351 pinctrl_pcie: pciegrp { 352 fsl,pins = < 353 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f059 /* PCIe Reset */ 354 >; 355 }; 356 357 pinctrl_uart4: uart4grp { 358 fsl,pins = < 359 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 360 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 361 >; 362 }; 363 364 pinctrl_usbhub: usbhubgrp { 365 fsl,pins = < 366 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1f059 /* HUB USB Reset */ 367 >; 368 }; 369 370 pinctrl_usbotg: usbotggrp { 371 fsl,pins = < 372 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 373 >; 374 }; 375 376 pinctrl_usdhc1: usdhc1grp { 377 fsl,pins = < 378 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 379 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 380 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 381 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 382 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 383 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 384 >; 385 }; 386 387 pinctrl_usdhc3: usdhc3grp { 388 fsl,pins = < 389 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17070 390 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10070 391 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17070 392 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17070 393 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17070 394 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17070 395 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1f059 /* CD */ 396 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f059 /* PWR */ 397 >; 398 }; 399 400 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { 401 fsl,pins = < 402 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B1 403 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B1 404 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B1 405 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B1 406 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B1 407 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B1 408 >; 409 }; 410 411 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { 412 fsl,pins = < 413 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9 414 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9 415 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9 416 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9 417 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9 418 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9 419 >; 420 }; 421 422 pinctrl_usdhc4: usdhc4grp { 423 fsl,pins = < 424 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17070 425 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10070 426 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17070 427 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17070 428 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17070 429 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17070 430 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17070 431 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17070 432 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17070 433 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17070 434 >; 435 }; 436 437 pinctrl_usdhc4_100mhz: usdhc4grp_100mhz { 438 fsl,pins = < 439 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170B1 440 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100B1 441 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170B1 442 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170B1 443 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170B1 444 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170B1 445 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170B1 446 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170B1 447 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170B1 448 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170B1 449 >; 450 }; 451 452 pinctrl_usdhc4_200mhz: usdhc4grp_200mhz { 453 fsl,pins = < 454 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170F9 455 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100F9 456 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170F9 457 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170F9 458 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170F9 459 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170F9 460 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170F9 461 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170F9 462 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170F9 463 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170F9 464 >; 465 }; 466 };
Cache object: 06325d4555807db6b09560c9e2d307d7
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]