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sys/contrib/device-tree/src/arm/imx6qdl-kontron-samx6i.dtsi
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1 // SPDX-License-Identifier: GPL-2.0 OR X11 2 /* 3 * Copyright 2017 (C) Priit Laes <plaes@plaes.org> 4 * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr@pengutronix.de> 5 * Copyright 2019 (C) Pengutronix, Marco Felsch <kernel@pengutronix.de> 6 * 7 * Based on initial work by Nikita Yushchenko <nyushchenko at dev.rtsoft.ru> 8 */ 9 10 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/sound/fsl-imx-audmux.h> 12 13 / { 14 reg_1p0v_s0: regulator-1p0v-s0 { 15 compatible = "regulator-fixed"; 16 regulator-name = "V_1V0_S0"; 17 regulator-min-microvolt = <1000000>; 18 regulator-max-microvolt = <1000000>; 19 regulator-always-on; 20 regulator-boot-on; 21 vin-supply = <®_smarc_suppy>; 22 }; 23 24 reg_1p35v_vcoredig_s5: regulator-1p35v-vcoredig-s5 { 25 compatible = "regulator-fixed"; 26 regulator-name = "V_1V35_VCOREDIG_S5"; 27 regulator-min-microvolt = <1350000>; 28 regulator-max-microvolt = <1350000>; 29 regulator-always-on; 30 regulator-boot-on; 31 vin-supply = <®_3p3v_s5>; 32 }; 33 34 reg_1p8v_s5: regulator-1p8v-s5 { 35 compatible = "regulator-fixed"; 36 regulator-name = "V_1V8_S5"; 37 regulator-min-microvolt = <1800000>; 38 regulator-max-microvolt = <1800000>; 39 regulator-always-on; 40 regulator-boot-on; 41 vin-supply = <®_3p3v_s5>; 42 }; 43 44 reg_3p3v_s0: regulator-3p3v-s0 { 45 compatible = "regulator-fixed"; 46 regulator-name = "V_3V3_S0"; 47 regulator-min-microvolt = <3300000>; 48 regulator-max-microvolt = <3300000>; 49 regulator-always-on; 50 regulator-boot-on; 51 vin-supply = <®_3p3v_s5>; 52 }; 53 54 reg_3p3v_s5: regulator-3p3v-s5 { 55 compatible = "regulator-fixed"; 56 regulator-name = "V_3V3_S5"; 57 regulator-min-microvolt = <3300000>; 58 regulator-max-microvolt = <3300000>; 59 regulator-always-on; 60 regulator-boot-on; 61 vin-supply = <®_smarc_suppy>; 62 }; 63 64 reg_smarc_lcdbklt: regulator-smarc-lcdbklt { 65 compatible = "regulator-fixed"; 66 pinctrl-names = "default"; 67 pinctrl-0 = <&pinctrl_lcdbklt_en>; 68 regulator-name = "LCD_BKLT_EN"; 69 regulator-min-microvolt = <1800000>; 70 regulator-max-microvolt = <1800000>; 71 gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>; 72 enable-active-high; 73 }; 74 75 reg_smarc_lcdvdd: regulator-smarc-lcdvdd { 76 compatible = "regulator-fixed"; 77 pinctrl-names = "default"; 78 pinctrl-0 = <&pinctrl_lcdvdd_en>; 79 regulator-name = "LCD_VDD_EN"; 80 regulator-min-microvolt = <1800000>; 81 regulator-max-microvolt = <1800000>; 82 gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; 83 enable-active-high; 84 }; 85 86 reg_smarc_rtc: regulator-smarc-rtc { 87 compatible = "regulator-fixed"; 88 regulator-name = "V_IN_RTC_BATT"; 89 regulator-min-microvolt = <3300000>; 90 regulator-max-microvolt = <3300000>; 91 regulator-always-on; 92 regulator-boot-on; 93 }; 94 95 /* Module supply range can be 3.00V ... 5.25V */ 96 reg_smarc_suppy: regulator-smarc-supply { 97 compatible = "regulator-fixed"; 98 regulator-name = "V_IN_WIDE"; 99 regulator-min-microvolt = <5000000>; 100 regulator-max-microvolt = <5000000>; 101 regulator-always-on; 102 regulator-boot-on; 103 }; 104 105 lcd: lcd { 106 #address-cells = <1>; 107 #size-cells = <0>; 108 compatible = "fsl,imx-parallel-display"; 109 pinctrl-names = "default"; 110 pinctrl-0 = <&pinctrl_lcd>; 111 status = "disabled"; 112 113 port@0 { 114 reg = <0>; 115 116 lcd_in: endpoint { 117 }; 118 }; 119 120 port@1 { 121 reg = <1>; 122 123 lcd_out: endpoint { 124 }; 125 }; 126 }; 127 128 lcd_backlight: lcd-backlight { 129 compatible = "pwm-backlight"; 130 pwms = <&pwm4 0 5000000 0>; 131 pwm-names = "LCD_BKLT_PWM"; 132 133 brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; 134 default-brightness-level = <4>; 135 136 power-supply = <®_smarc_lcdbklt>; 137 status = "disabled"; 138 }; 139 140 i2c_intern: i2c-gpio-intern { 141 compatible = "i2c-gpio"; 142 pinctrl-names = "default"; 143 pinctrl-0 = <&pinctrl_i2c_gpio_intern>; 144 sda-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 145 scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 146 i2c-gpio,delay-us = <2>; /* ~100 kHz */ 147 #address-cells = <1>; 148 #size-cells = <0>; 149 }; 150 151 i2c_lcd: i2c-gpio-lcd { 152 compatible = "i2c-gpio"; 153 pinctrl-names = "default"; 154 pinctrl-0 = <&pinctrl_i2c_gpio_lcd>; 155 sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 156 scl-gpios = <&gpio1 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 157 i2c-gpio,delay-us = <2>; /* ~100 kHz */ 158 #address-cells = <1>; 159 #size-cells = <0>; 160 status = "disabled"; 161 }; 162 163 i2c_cam: i2c-gpio-cam { 164 compatible = "i2c-gpio"; 165 pinctrl-names = "default"; 166 pinctrl-0 = <&pinctrl_i2c_gpio_cam>; 167 sda-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 168 scl-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 169 i2c-gpio,delay-us = <2>; /* ~100 kHz */ 170 #address-cells = <1>; 171 #size-cells = <0>; 172 status = "disabled"; 173 }; 174 }; 175 176 /* I2S0, I2S1 */ 177 &audmux { 178 pinctrl-names = "default"; 179 pinctrl-0 = <&pinctrl_audmux>; 180 181 audmux_ssi1 { 182 fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>; 183 fsl,port-config = < 184 (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT3) | 185 IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT3) | 186 IMX_AUDMUX_V2_PTCR_SYN | 187 IMX_AUDMUX_V2_PTCR_TFSDIR | 188 IMX_AUDMUX_V2_PTCR_TCLKDIR) 189 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT3) 190 >; 191 }; 192 193 audmux_adu3 { 194 fsl,audmux-port = <MX51_AUDMUX_PORT3>; 195 fsl,port-config = < 196 IMX_AUDMUX_V2_PTCR_SYN 197 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) 198 >; 199 }; 200 201 audmux_ssi2 { 202 fsl,audmux-port = <MX51_AUDMUX_PORT2_SSI1>; 203 fsl,port-config = < 204 (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) | 205 IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) | 206 IMX_AUDMUX_V2_PTCR_SYN | 207 IMX_AUDMUX_V2_PTCR_TFSDIR | 208 IMX_AUDMUX_V2_PTCR_TCLKDIR) 209 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4) 210 >; 211 }; 212 213 audmux_adu4 { 214 fsl,audmux-port = <MX51_AUDMUX_PORT4>; 215 fsl,port-config = < 216 IMX_AUDMUX_V2_PTCR_SYN 217 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT2_SSI1) 218 >; 219 }; 220 }; 221 222 /* CAN0 */ 223 &can1 { 224 pinctrl-names = "default"; 225 pinctrl-0 = <&pinctrl_flexcan1>; 226 }; 227 228 /* CAN1 */ 229 &can2 { 230 pinctrl-names = "default"; 231 pinctrl-0 = <&pinctrl_flexcan2>; 232 }; 233 234 /* SPI1 */ 235 &ecspi2 { 236 pinctrl-names = "default"; 237 pinctrl-0 = <&pinctrl_ecspi2>; 238 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, 239 <&gpio2 27 GPIO_ACTIVE_LOW>; 240 }; 241 242 /* SPI0 */ 243 &ecspi4 { 244 pinctrl-names = "default"; 245 pinctrl-0 = <&pinctrl_ecspi4>; 246 cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>, 247 <&gpio3 29 GPIO_ACTIVE_LOW>; 248 status = "okay"; 249 250 /* default boot source: workaround #1 for errata ERR006282 */ 251 smarc_flash: flash@0 { 252 compatible = "jedec,spi-nor"; 253 reg = <0>; 254 spi-max-frequency = <20000000>; 255 }; 256 }; 257 258 /* GBE */ 259 &fec { 260 pinctrl-names = "default"; 261 pinctrl-0 = <&pinctrl_enet>; 262 phy-mode = "rgmii"; 263 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; 264 }; 265 266 &i2c_intern { 267 pmic@8 { 268 compatible = "fsl,pfuze100"; 269 reg = <0x08>; 270 271 regulators { 272 reg_v_core_s0: sw1ab { 273 regulator-name = "V_CORE_S0"; 274 regulator-min-microvolt = <300000>; 275 regulator-max-microvolt = <1875000>; 276 regulator-boot-on; 277 regulator-always-on; 278 }; 279 280 reg_vddsoc_s0: sw1c { 281 regulator-name = "V_VDDSOC_S0"; 282 regulator-min-microvolt = <300000>; 283 regulator-max-microvolt = <1875000>; 284 regulator-boot-on; 285 regulator-always-on; 286 }; 287 288 reg_3p15v_s0: sw2 { 289 regulator-name = "V_3V15_S0"; 290 regulator-min-microvolt = <800000>; 291 regulator-max-microvolt = <3300000>; 292 regulator-boot-on; 293 regulator-always-on; 294 }; 295 296 /* sw3a/b is used in dual mode, but driver does not 297 * support it. Although, there's no need to control 298 * DDR power - so just leaving dummy entries for sw3a 299 * and sw3b for now. 300 */ 301 sw3a { 302 regulator-min-microvolt = <400000>; 303 regulator-max-microvolt = <1975000>; 304 regulator-boot-on; 305 regulator-always-on; 306 }; 307 308 sw3b { 309 regulator-min-microvolt = <400000>; 310 regulator-max-microvolt = <1975000>; 311 regulator-boot-on; 312 regulator-always-on; 313 }; 314 315 reg_1p8v_s0: sw4 { 316 regulator-name = "V_1V8_S0"; 317 regulator-min-microvolt = <800000>; 318 regulator-max-microvolt = <3300000>; 319 regulator-boot-on; 320 regulator-always-on; 321 }; 322 323 /* Regulator for USB */ 324 reg_5p0v_s0: swbst { 325 regulator-name = "V_5V0_S0"; 326 regulator-min-microvolt = <5000000>; 327 regulator-max-microvolt = <5150000>; 328 regulator-boot-on; 329 }; 330 331 reg_vsnvs: vsnvs { 332 regulator-min-microvolt = <1000000>; 333 regulator-max-microvolt = <3000000>; 334 regulator-boot-on; 335 regulator-always-on; 336 }; 337 338 reg_vrefddr: vrefddr { 339 regulator-boot-on; 340 regulator-always-on; 341 }; 342 343 /* 344 * Per schematics, of all VGEN's, only VGEN5 has some 345 * usage ... but even that - over DNI resistor 346 */ 347 vgen1 { 348 regulator-min-microvolt = <800000>; 349 regulator-max-microvolt = <1550000>; 350 }; 351 352 vgen2 { 353 regulator-min-microvolt = <800000>; 354 regulator-max-microvolt = <1550000>; 355 }; 356 357 vgen3 { 358 regulator-min-microvolt = <1800000>; 359 regulator-max-microvolt = <3300000>; 360 }; 361 362 vgen4 { 363 regulator-min-microvolt = <1800000>; 364 regulator-max-microvolt = <3300000>; 365 }; 366 367 reg_2p5v_s0: vgen5 { 368 regulator-name = "V_2V5_S0"; 369 regulator-min-microvolt = <1800000>; 370 regulator-max-microvolt = <3300000>; 371 }; 372 373 vgen6 { 374 regulator-min-microvolt = <1800000>; 375 regulator-max-microvolt = <3300000>; 376 }; 377 }; 378 }; 379 }; 380 381 /* I2C_GP */ 382 &i2c1 { 383 clock-frequency = <375000>; 384 pinctrl-names = "default"; 385 pinctrl-0 = <&pinctrl_i2c1>; 386 }; 387 388 /* HDMI_CTRL */ 389 &i2c2 { 390 clock-frequency = <375000>; 391 pinctrl-names = "default"; 392 pinctrl-0 = <&pinctrl_i2c2>; 393 }; 394 395 /* I2C_PM */ 396 &i2c3 { 397 clock-frequency = <375000>; 398 pinctrl-names = "default"; 399 pinctrl-0 = <&pinctrl_i2c3>; 400 status = "okay"; 401 402 smarc_eeprom: eeprom@50 { 403 compatible = "atmel,24c32"; 404 reg = <0x50>; 405 pagesize = <32>; 406 }; 407 }; 408 409 &iomuxc { 410 pinctrl-names = "default"; 411 pinctrl-0 = <&pinctrl_mgmt_gpios &pinctrl_gpio>; 412 413 pinctrl_audmux: audmuxgrp { 414 fsl,pins = < 415 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 416 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130b0 417 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 418 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 419 420 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 421 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 422 MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 423 MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 424 425 /* AUDIO MCLK */ 426 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x000b0 427 >; 428 }; 429 430 pinctrl_ecspi2: ecspi2grp { 431 fsl,pins = < 432 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 433 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 434 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 435 436 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0 /* CS0 */ 437 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 /* CS1 */ 438 >; 439 }; 440 441 pinctrl_ecspi4: ecspi4grp { 442 fsl,pins = < 443 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 444 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 445 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 446 447 /* SPI_IMX_CS2# - connected to internal flash */ 448 MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0 449 /* SPI_IMX_CS0# - connected to SMARC SPI0_CS0# */ 450 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 451 >; 452 }; 453 454 pinctrl_flexcan1: flexcan1grp { 455 fsl,pins = < 456 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 457 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 458 >; 459 }; 460 461 pinctrl_flexcan2: flexcan2grp { 462 fsl,pins = < 463 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 464 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 465 >; 466 }; 467 468 pinctrl_gpio: gpiogrp { 469 fsl,pins = < 470 MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b0 /* GPIO0 / CAM0_PWR# */ 471 MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b0 /* GPIO1 / CAM1_PWR# */ 472 MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b0 /* GPIO2 / CAM0_RST# */ 473 MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b0 /* GPIO3 / CAM1_RST# */ 474 MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b0 /* GPIO4 / HDA_RST# */ 475 MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b0 /* GPIO5 / PWM_OUT */ 476 MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b0 /* GPIO6 / TACHIN */ 477 MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b0 /* GPIO7 / PCAM_FLD */ 478 MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b0 /* GPIO8 / CAN0_ERR# */ 479 MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b0 /* GPIO9 / CAN1_ERR# */ 480 MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b0 /* GPIO10 */ 481 MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b0 /* GPIO11 */ 482 >; 483 }; 484 485 pinctrl_enet: enetgrp { 486 fsl,pins = < 487 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 488 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 489 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 490 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 491 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 492 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 493 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 494 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 495 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 496 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 497 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 498 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 499 500 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 501 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 502 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 503 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* RST_GBE0_PHY# */ 504 >; 505 }; 506 507 pinctrl_i2c_gpio_cam: i2c-gpiocamgrp { 508 fsl,pins = < 509 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* SCL */ 510 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* SDA */ 511 >; 512 }; 513 514 pinctrl_i2c_gpio_intern: i2c-gpiointerngrp { 515 fsl,pins = < 516 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* SCL */ 517 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* SDA */ 518 >; 519 }; 520 521 pinctrl_i2c_gpio_lcd: i2c-gpiolcdgrp { 522 fsl,pins = < 523 MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 /* SCL */ 524 MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b0 /* SDA */ 525 >; 526 }; 527 528 pinctrl_i2c1: i2c1grp { 529 fsl,pins = < 530 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 531 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 532 >; 533 }; 534 535 pinctrl_i2c2: i2c2grp { 536 fsl,pins = < 537 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 538 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 539 >; 540 }; 541 542 pinctrl_i2c3: i2c3grp { 543 fsl,pins = < 544 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 545 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 546 >; 547 }; 548 549 pinctrl_lcd: lcdgrp { 550 fsl,pins = < 551 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100f1 552 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100f1 553 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100f1 554 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100f1 555 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100f1 556 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100f1 557 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100f1 558 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100f1 559 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100f1 560 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100f1 561 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100f1 562 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100f1 563 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100f1 564 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100f1 565 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100f1 566 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100f1 567 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100f1 568 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100f1 569 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x100f1 570 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x100f1 571 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x100f1 572 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x100f1 573 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x100f1 574 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x100f1 575 576 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f1 577 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100f1 /* DE */ 578 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100f1 /* HSYNC */ 579 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100f1 /* VSYNC */ 580 >; 581 }; 582 583 pinctrl_lcdbklt_en: lcdbkltengrp { 584 fsl,pins = < 585 MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b1 586 >; 587 }; 588 589 pinctrl_lcdvdd_en: lcdvddengrp { 590 fsl,pins = < 591 MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 592 >; 593 }; 594 595 pinctrl_mipi_csi: mipi-csigrp { 596 fsl,pins = < 597 MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x000b0 /* CSI0/1 MCLK */ 598 >; 599 }; 600 601 pinctrl_mgmt_gpios: mgmt-gpiosgrp { 602 fsl,pins = < 603 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 /* LID# */ 604 MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x1b0b0 /* SLEEP# */ 605 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* CHARGING# */ 606 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* CHARGER_PRSNT# */ 607 MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0 /* CARRIER_STBY# */ 608 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* BATLOW# */ 609 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0 /* TEST# */ 610 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 /* VDD_IO_SEL_D# */ 611 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 /* POWER_BTN# */ 612 >; 613 }; 614 615 pinctrl_pcie: pciegrp { 616 fsl,pins = < 617 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 /* PCI_A_PRSNT# */ 618 MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 /* RST_PCIE_A# */ 619 MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 /* PCIE_WAKE# */ 620 >; 621 }; 622 623 pinctrl_pwm4: pwm4grp { 624 fsl,pins = < 625 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 626 >; 627 }; 628 629 pinctrl_uart1: uart1grp { 630 fsl,pins = < 631 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 632 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 633 MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 634 MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1 635 >; 636 }; 637 638 pinctrl_uart2: uart2grp { 639 fsl,pins = < 640 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 641 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 642 >; 643 }; 644 645 pinctrl_uart4: uart4grp { 646 fsl,pins = < 647 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 648 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 649 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 650 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 651 >; 652 }; 653 654 pinctrl_uart5: uart5grp { 655 fsl,pins = < 656 MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 657 MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 658 >; 659 }; 660 661 pinctrl_usbotg: usbotggrp { 662 fsl,pins = < 663 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1f8b0 664 /* power, oc muxed but not used by the driver */ 665 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 /* USB power */ 666 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 /* USB OC */ 667 >; 668 }; 669 670 pinctrl_usdhc3: usdhc3grp { 671 fsl,pins = < 672 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x17059 673 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 674 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 675 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 676 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 677 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 678 679 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 /* CD */ 680 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 /* WP */ 681 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PWR_EN */ 682 >; 683 }; 684 685 pinctrl_usdhc4: usdhc4grp { 686 fsl,pins = < 687 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 688 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 689 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 690 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 691 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 692 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 693 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 694 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 695 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 696 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 697 >; 698 }; 699 700 pinctrl_wdog1: wdog1rp { 701 fsl,pins = < 702 MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 703 >; 704 }; 705 }; 706 707 &mipi_csi { 708 pinctrl-names = "default"; 709 pinctrl-0 = <&pinctrl_mipi_csi>; 710 }; 711 712 &pcie { 713 pinctrl-names = "default"; 714 pinctrl-0 = <&pinctrl_pcie>; 715 wake-up-gpio = <&gpio6 18 GPIO_ACTIVE_HIGH>; 716 reset-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>; 717 }; 718 719 /* LCD_BKLT_PWM */ 720 &pwm4 { 721 pinctrl-names = "default"; 722 pinctrl-0 = <&pinctrl_pwm4>; 723 }; 724 725 ®_arm { 726 vin-supply = <®_v_core_s0>; 727 }; 728 729 ®_pu { 730 vin-supply = <®_vddsoc_s0>; 731 }; 732 733 ®_soc { 734 vin-supply = <®_vddsoc_s0>; 735 }; 736 737 /* SER0 */ 738 &uart1 { 739 pinctrl-names = "default"; 740 pinctrl-0 = <&pinctrl_uart1>; 741 uart-has-rtscts; 742 }; 743 744 /* SER1 */ 745 &uart2 { 746 pinctrl-names = "default"; 747 pinctrl-0 = <&pinctrl_uart2>; 748 }; 749 750 /* SER2 */ 751 &uart4 { 752 pinctrl-names = "default"; 753 pinctrl-0 = <&pinctrl_uart4>; 754 uart-has-rtscts; 755 }; 756 757 /* SER3 */ 758 &uart5 { 759 pinctrl-names = "default"; 760 pinctrl-0 = <&pinctrl_uart5>; 761 }; 762 763 /* USB0 */ 764 &usbotg { 765 /* 766 * no 'imx6-usb-charger-detection' 767 * since USB_OTG_CHD_B pin is not wired 768 */ 769 pinctrl-names = "default"; 770 pinctrl-0 = <&pinctrl_usbotg>; 771 }; 772 773 /* USB1/2 via hub */ 774 &usbh1 { 775 vbus-supply = <®_5p0v_s0>; 776 }; 777 778 /* SDIO */ 779 &usdhc3 { 780 pinctrl-names = "default"; 781 pinctrl-0 = <&pinctrl_usdhc3>; 782 cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; 783 wp-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 784 no-1-8-v; 785 }; 786 787 /* SDMMC */ 788 &usdhc4 { 789 /* Internal eMMC, optional on some boards */ 790 pinctrl-names = "default"; 791 pinctrl-0 = <&pinctrl_usdhc4>; 792 bus-width = <8>; 793 no-sdio; 794 no-sd; 795 non-removable; 796 vmmc-supply = <®_3p3v_s0>; 797 vqmmc-supply = <®_1p8v_s0>; 798 }; 799 800 &wdog1 { 801 /* CPLD is feeded by watchdog (hardwired) */ 802 pinctrl-names = "default"; 803 pinctrl-0 = <&pinctrl_wdog1>; 804 status = "okay"; 805 };
Cache object: ba1862e9bcef59bfe3cefd4308a4b5fa
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