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sys/contrib/device-tree/src/arm/imx6qdl-nitrogen6_max.dtsi
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1 // SPDX-License-Identifier: GPL-2.0 OR X11 2 /* 3 * Copyright 2015 Boundary Devices, Inc. 4 */ 5 #include <dt-bindings/gpio/gpio.h> 6 #include <dt-bindings/input/input.h> 7 8 / { 9 chosen { 10 stdout-path = &uart2; 11 }; 12 13 memory@10000000 { 14 device_type = "memory"; 15 reg = <0x10000000 0xF0000000>; 16 }; 17 18 regulators { 19 compatible = "simple-bus"; 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 reg_1p8v: regulator@0 { 24 compatible = "regulator-fixed"; 25 reg = <0>; 26 regulator-name = "1P8V"; 27 regulator-min-microvolt = <1800000>; 28 regulator-max-microvolt = <1800000>; 29 regulator-always-on; 30 }; 31 32 reg_2p5v: regulator@1 { 33 compatible = "regulator-fixed"; 34 reg = <1>; 35 regulator-name = "2P5V"; 36 regulator-min-microvolt = <2500000>; 37 regulator-max-microvolt = <2500000>; 38 regulator-always-on; 39 }; 40 41 reg_3p3v: regulator@2 { 42 compatible = "regulator-fixed"; 43 reg = <2>; 44 regulator-name = "3P3V"; 45 regulator-min-microvolt = <3300000>; 46 regulator-max-microvolt = <3300000>; 47 regulator-always-on; 48 }; 49 50 reg_usb_otg_vbus: regulator@3 { 51 compatible = "regulator-fixed"; 52 reg = <3>; 53 regulator-name = "usb_otg_vbus"; 54 regulator-min-microvolt = <5000000>; 55 regulator-max-microvolt = <5000000>; 56 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 57 enable-active-high; 58 }; 59 60 reg_usb_h1_vbus: regulator@4 { 61 compatible = "regulator-fixed"; 62 reg = <4>; 63 pinctrl-names = "default"; 64 pinctrl-0 = <&pinctrl_usbh1>; 65 regulator-name = "usb_h1_vbus"; 66 regulator-min-microvolt = <3300000>; 67 regulator-max-microvolt = <3300000>; 68 gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; 69 enable-active-high; 70 }; 71 72 reg_wlan_vmmc: regulator@5 { 73 compatible = "regulator-fixed"; 74 reg = <5>; 75 pinctrl-names = "default"; 76 pinctrl-0 = <&pinctrl_wlan_vmmc>; 77 regulator-name = "reg_wlan_vmmc"; 78 regulator-min-microvolt = <3300000>; 79 regulator-max-microvolt = <3300000>; 80 gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; 81 startup-delay-us = <70000>; 82 enable-active-high; 83 }; 84 85 reg_can_xcvr: regulator@6 { 86 compatible = "regulator-fixed"; 87 reg = <6>; 88 regulator-name = "CAN XCVR"; 89 regulator-min-microvolt = <3300000>; 90 regulator-max-microvolt = <3300000>; 91 pinctrl-names = "default"; 92 pinctrl-0 = <&pinctrl_can_xcvr>; 93 gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; 94 }; 95 }; 96 97 gpio-keys { 98 compatible = "gpio-keys"; 99 pinctrl-names = "default"; 100 pinctrl-0 = <&pinctrl_gpio_keys>; 101 102 power { 103 label = "Power Button"; 104 gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; 105 linux,code = <KEY_POWER>; 106 wakeup-source; 107 }; 108 109 menu { 110 label = "Menu"; 111 gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 112 linux,code = <KEY_MENU>; 113 }; 114 115 home { 116 label = "Home"; 117 gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; 118 linux,code = <KEY_HOME>; 119 }; 120 121 back { 122 label = "Back"; 123 gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; 124 linux,code = <KEY_BACK>; 125 }; 126 127 volume-up { 128 label = "Volume Up"; 129 gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; 130 linux,code = <KEY_VOLUMEUP>; 131 }; 132 133 volume-down { 134 label = "Volume Down"; 135 gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; 136 linux,code = <KEY_VOLUMEDOWN>; 137 }; 138 }; 139 140 i2c2mux { 141 compatible = "i2c-mux-gpio"; 142 pinctrl-names = "default"; 143 pinctrl-0 = <&pinctrl_i2c2mux>; 144 #address-cells = <1>; 145 #size-cells = <0>; 146 mux-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH 147 &gpio4 15 GPIO_ACTIVE_HIGH>; 148 i2c-parent = <&i2c2>; 149 idle-state = <0>; 150 151 i2c2mux@1 { 152 reg = <1>; 153 #address-cells = <1>; 154 #size-cells = <0>; 155 }; 156 157 i2c2mux@2 { 158 reg = <2>; 159 #address-cells = <1>; 160 #size-cells = <0>; 161 }; 162 }; 163 164 i2c3mux { 165 compatible = "i2c-mux-gpio"; 166 pinctrl-names = "default"; 167 pinctrl-0 = <&pinctrl_i2c3mux>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 mux-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; 171 i2c-parent = <&i2c3>; 172 idle-state = <0>; 173 174 i2c3mux@1 { 175 reg = <1>; 176 #address-cells = <1>; 177 #size-cells = <0>; 178 }; 179 }; 180 181 leds { 182 compatible = "gpio-leds"; 183 184 speaker-enable { 185 gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; 186 retain-state-suspended; 187 default-state = "off"; 188 }; 189 190 ttymxc4-rs232 { 191 gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; 192 retain-state-suspended; 193 default-state = "on"; 194 }; 195 }; 196 197 backlight_lcd: backlight-lcd { 198 compatible = "pwm-backlight"; 199 pwms = <&pwm1 0 5000000>; 200 brightness-levels = <0 4 8 16 32 64 128 255>; 201 default-brightness-level = <7>; 202 power-supply = <®_3p3v>; 203 status = "okay"; 204 }; 205 206 backlight_lvds0: backlight-lvds0 { 207 compatible = "pwm-backlight"; 208 pwms = <&pwm4 0 5000000>; 209 brightness-levels = <0 4 8 16 32 64 128 255>; 210 default-brightness-level = <7>; 211 power-supply = <®_3p3v>; 212 status = "okay"; 213 }; 214 215 backlight_lvds1: backlight-lvds1 { 216 compatible = "pwm-backlight"; 217 pwms = <&pwm2 0 5000000>; 218 brightness-levels = <0 4 8 16 32 64 128 255>; 219 default-brightness-level = <7>; 220 power-supply = <®_3p3v>; 221 status = "okay"; 222 }; 223 224 lcd_display: disp0 { 225 compatible = "fsl,imx-parallel-display"; 226 #address-cells = <1>; 227 #size-cells = <0>; 228 interface-pix-fmt = "bgr666"; 229 pinctrl-names = "default"; 230 pinctrl-0 = <&pinctrl_j15>; 231 status = "okay"; 232 233 port@0 { 234 reg = <0>; 235 236 lcd_display_in: endpoint { 237 remote-endpoint = <&ipu1_di0_disp0>; 238 }; 239 }; 240 241 port@1 { 242 reg = <1>; 243 244 lcd_display_out: endpoint { 245 remote-endpoint = <&lcd_panel_in>; 246 }; 247 }; 248 }; 249 250 panel-lcd { 251 compatible = "okaya,rs800480t-7x0gp"; 252 backlight = <&backlight_lcd>; 253 254 port { 255 lcd_panel_in: endpoint { 256 remote-endpoint = <&lcd_display_out>; 257 }; 258 }; 259 }; 260 261 panel-lvds0 { 262 compatible = "hannstar,hsd100pxn1"; 263 backlight = <&backlight_lvds0>; 264 265 port { 266 panel_in_lvds0: endpoint { 267 remote-endpoint = <&lvds0_out>; 268 }; 269 }; 270 }; 271 272 panel-lvds1 { 273 compatible = "hannstar,hsd100pxn1"; 274 backlight = <&backlight_lvds1>; 275 276 port { 277 panel_in_lvds1: endpoint { 278 remote-endpoint = <&lvds1_out>; 279 }; 280 }; 281 }; 282 283 sound { 284 compatible = "fsl,imx6q-nitrogen6_max-sgtl5000", 285 "fsl,imx-audio-sgtl5000"; 286 model = "imx6q-nitrogen6_max-sgtl5000"; 287 ssi-controller = <&ssi1>; 288 audio-codec = <&codec>; 289 audio-routing = 290 "MIC_IN", "Mic Jack", 291 "Mic Jack", "Mic Bias", 292 "Headphone Jack", "HP_OUT"; 293 mux-int-port = <1>; 294 mux-ext-port = <3>; 295 }; 296 }; 297 298 &audmux { 299 pinctrl-names = "default"; 300 pinctrl-0 = <&pinctrl_audmux>; 301 status = "okay"; 302 }; 303 304 &can1 { 305 pinctrl-names = "default"; 306 pinctrl-0 = <&pinctrl_can1>; 307 xceiver-supply = <®_can_xcvr>; 308 status = "okay"; 309 }; 310 311 &clks { 312 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 313 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 314 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 315 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 316 }; 317 318 &ecspi1 { 319 cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; 320 pinctrl-names = "default"; 321 pinctrl-0 = <&pinctrl_ecspi1>; 322 status = "okay"; 323 324 flash: flash@0 { 325 compatible = "microchip,sst25vf016b"; 326 spi-max-frequency = <20000000>; 327 reg = <0>; 328 }; 329 }; 330 331 &fec { 332 pinctrl-names = "default"; 333 pinctrl-0 = <&pinctrl_enet>; 334 phy-mode = "rgmii"; 335 phy-handle = <ðphy>; 336 phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; 337 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, 338 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; 339 fsl,err006687-workaround-present; 340 status = "okay"; 341 342 mdio { 343 #address-cells = <1>; 344 #size-cells = <0>; 345 346 ethphy: ethernet-phy { 347 compatible = "ethernet-phy-ieee802.3-c22"; 348 txen-skew-ps = <0>; 349 txc-skew-ps = <3000>; 350 rxdv-skew-ps = <0>; 351 rxc-skew-ps = <3000>; 352 rxd0-skew-ps = <0>; 353 rxd1-skew-ps = <0>; 354 rxd2-skew-ps = <0>; 355 rxd3-skew-ps = <0>; 356 txd0-skew-ps = <0>; 357 txd1-skew-ps = <0>; 358 txd2-skew-ps = <0>; 359 txd3-skew-ps = <0>; 360 }; 361 }; 362 }; 363 364 &hdmi { 365 ddc-i2c-bus = <&i2c2>; 366 status = "okay"; 367 }; 368 369 &i2c1 { 370 clock-frequency = <100000>; 371 pinctrl-names = "default"; 372 pinctrl-0 = <&pinctrl_i2c1>; 373 status = "okay"; 374 375 codec: sgtl5000@a { 376 compatible = "fsl,sgtl5000"; 377 pinctrl-names = "default"; 378 pinctrl-0 = <&pinctrl_sgtl5000>; 379 reg = <0x0a>; 380 clocks = <&clks IMX6QDL_CLK_CKO>; 381 VDDA-supply = <®_2p5v>; 382 VDDIO-supply = <®_3p3v>; 383 }; 384 385 rtc: rtc@68 { 386 compatible = "microcrystal,rv4162"; 387 pinctrl-names = "default"; 388 pinctrl-0 = <&pinctrl_rv4162>; 389 reg = <0x68>; 390 interrupts-extended = <&gpio4 6 IRQ_TYPE_LEVEL_LOW>; 391 }; 392 }; 393 394 &i2c2 { 395 clock-frequency = <100000>; 396 pinctrl-names = "default"; 397 pinctrl-0 = <&pinctrl_i2c2>; 398 status = "okay"; 399 }; 400 401 &i2c3 { 402 clock-frequency = <100000>; 403 pinctrl-names = "default"; 404 pinctrl-0 = <&pinctrl_i2c3>; 405 status = "okay"; 406 407 touchscreen@4 { 408 compatible = "eeti,egalax_ts"; 409 reg = <0x04>; 410 interrupt-parent = <&gpio1>; 411 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 412 wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; 413 }; 414 415 touchscreen@38 { 416 compatible = "edt,edt-ft5x06"; 417 reg = <0x38>; 418 interrupt-parent = <&gpio1>; 419 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 420 wakeup-source; 421 }; 422 }; 423 424 &iomuxc { 425 imx6q-nitrogen6-max { 426 pinctrl_audmux: audmuxgrp { 427 fsl,pins = < 428 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 429 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 430 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 431 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 432 >; 433 }; 434 435 pinctrl_can1: can1grp { 436 fsl,pins = < 437 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 438 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 439 >; 440 }; 441 442 pinctrl_can_xcvr: can-xcvrgrp { 443 fsl,pins = < 444 /* Flexcan XCVR enable */ 445 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 446 >; 447 }; 448 449 pinctrl_ecspi1: ecspi1grp { 450 fsl,pins = < 451 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 452 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 453 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 454 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 455 >; 456 }; 457 458 pinctrl_enet: enetgrp { 459 fsl,pins = < 460 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 461 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 462 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 463 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 464 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 465 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 466 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 467 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 468 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 469 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 470 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 471 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 472 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 473 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 474 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 475 /* Phy reset */ 476 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 477 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 478 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 479 >; 480 }; 481 482 pinctrl_gpio_keys: gpio-keysgrp { 483 fsl,pins = < 484 /* Power Button */ 485 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 486 /* Menu Button */ 487 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 488 /* Home Button */ 489 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 490 /* Back Button */ 491 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 492 /* Volume Up Button */ 493 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 494 /* Volume Down Button */ 495 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 496 >; 497 }; 498 499 pinctrl_i2c1: i2c1grp { 500 fsl,pins = < 501 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 502 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 503 >; 504 }; 505 506 pinctrl_i2c2: i2c2grp { 507 fsl,pins = < 508 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 509 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 510 >; 511 }; 512 513 pinctrl_i2c2mux: i2c2muxgrp { 514 fsl,pins = < 515 /* ov5642 camera i2c enable */ 516 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x000b0 517 /* ov5640_mipi camera i2c enable */ 518 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0 519 >; 520 }; 521 522 pinctrl_i2c3: i2c3grp { 523 fsl,pins = < 524 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 525 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 526 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 527 >; 528 }; 529 530 pinctrl_i2c3mux: i2c3muxgrp { 531 fsl,pins = < 532 /* PCIe I2C enable */ 533 MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0 534 >; 535 }; 536 537 pinctrl_j15: j15grp { 538 fsl,pins = < 539 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 540 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 541 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 542 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 543 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 544 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 545 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 546 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 547 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 548 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 549 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 550 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 551 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 552 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 553 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 554 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 555 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 556 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 557 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 558 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 559 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 560 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 561 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 562 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 563 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 564 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 565 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 566 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 567 >; 568 }; 569 570 pinctrl_pcie: pciegrp { 571 fsl,pins = < 572 /* PCIe reset */ 573 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x000b0 574 >; 575 }; 576 577 pinctrl_pwm1: pwm1grp { 578 fsl,pins = < 579 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 580 >; 581 }; 582 583 pinctrl_pwm2: pwm2grp { 584 fsl,pins = < 585 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 586 >; 587 }; 588 589 pinctrl_pwm3: pwm3grp { 590 fsl,pins = < 591 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 592 >; 593 }; 594 595 pinctrl_pwm4: pwm4grp { 596 fsl,pins = < 597 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 598 >; 599 }; 600 601 pinctrl_rv4162: rv4162grp { 602 fsl,pins = < 603 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 604 >; 605 }; 606 607 pinctrl_sgtl5000: sgtl5000grp { 608 fsl,pins = < 609 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 610 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 611 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 612 >; 613 }; 614 615 pinctrl_uart1: uart1grp { 616 fsl,pins = < 617 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 618 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 619 >; 620 }; 621 622 pinctrl_uart2: uart2grp { 623 fsl,pins = < 624 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 625 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 626 >; 627 }; 628 629 pinctrl_uart5: uart5grp { 630 fsl,pins = < 631 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x130b1 632 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x030b1 633 /* RS485 RX Enable: pull up */ 634 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b1 635 /* RS485 DEN: pull down */ 636 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b1 637 /* RS485/!RS232 Select: pull down (rs232) */ 638 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x030b1 639 /* ON: pull down */ 640 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x030b1 641 >; 642 }; 643 644 pinctrl_usbh1: usbh1grp { 645 fsl,pins = < 646 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0 647 >; 648 }; 649 650 pinctrl_usbotg: usbotggrp { 651 fsl,pins = < 652 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 653 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 654 /* power enable, high active */ 655 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 656 >; 657 }; 658 659 pinctrl_usdhc2: usdhc2grp { 660 fsl,pins = < 661 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 662 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 663 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 664 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 665 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 666 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 667 >; 668 }; 669 670 pinctrl_usdhc3: usdhc3grp { 671 fsl,pins = < 672 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 673 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 674 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 675 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 676 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 677 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 678 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x100b0 679 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 680 >; 681 }; 682 683 pinctrl_usdhc4: usdhc4grp { 684 fsl,pins = < 685 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 686 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 687 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 688 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 689 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 690 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 691 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 692 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 693 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 694 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 695 >; 696 }; 697 698 pinctrl_wlan_vmmc: wlan-vmmcgrp { 699 fsl,pins = < 700 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 701 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 702 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 703 MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 704 >; 705 }; 706 }; 707 }; 708 709 &ipu1_di0_disp0 { 710 remote-endpoint = <&lcd_display_in>; 711 }; 712 713 &ldb { 714 status = "okay"; 715 716 lvds-channel@0 { 717 status = "okay"; 718 719 port@4 { 720 reg = <4>; 721 722 lvds0_out: endpoint { 723 remote-endpoint = <&panel_in_lvds0>; 724 }; 725 }; 726 }; 727 728 lvds-channel@1 { 729 status = "okay"; 730 731 port@4 { 732 reg = <4>; 733 734 lvds1_out: endpoint { 735 remote-endpoint = <&panel_in_lvds1>; 736 }; 737 }; 738 }; 739 }; 740 741 &pcie { 742 pinctrl-names = "default"; 743 pinctrl-0 = <&pinctrl_pcie>; 744 reset-gpio = <&gpio6 31 GPIO_ACTIVE_LOW>; 745 status = "okay"; 746 }; 747 748 &pwm1 { 749 #pwm-cells = <2>; 750 pinctrl-names = "default"; 751 pinctrl-0 = <&pinctrl_pwm1>; 752 status = "okay"; 753 }; 754 755 &pwm2 { 756 #pwm-cells = <2>; 757 pinctrl-names = "default"; 758 pinctrl-0 = <&pinctrl_pwm2>; 759 status = "okay"; 760 }; 761 762 &pwm3 { 763 pinctrl-names = "default"; 764 pinctrl-0 = <&pinctrl_pwm3>; 765 status = "okay"; 766 }; 767 768 &pwm4 { 769 #pwm-cells = <2>; 770 pinctrl-names = "default"; 771 pinctrl-0 = <&pinctrl_pwm4>; 772 status = "okay"; 773 }; 774 775 &ssi1 { 776 status = "okay"; 777 }; 778 779 &uart1 { 780 pinctrl-names = "default"; 781 pinctrl-0 = <&pinctrl_uart1>; 782 status = "okay"; 783 }; 784 785 &uart2 { 786 pinctrl-names = "default"; 787 pinctrl-0 = <&pinctrl_uart2>; 788 status = "okay"; 789 }; 790 791 &uart5 { 792 pinctrl-names = "default"; 793 pinctrl-0 = <&pinctrl_uart5>; 794 status = "okay"; 795 }; 796 797 &usbh1 { 798 vbus-supply = <®_usb_h1_vbus>; 799 status = "okay"; 800 }; 801 802 &usbotg { 803 vbus-supply = <®_usb_otg_vbus>; 804 pinctrl-names = "default"; 805 pinctrl-0 = <&pinctrl_usbotg>; 806 disable-over-current; 807 status = "okay"; 808 }; 809 810 &usdhc2 { 811 pinctrl-names = "default"; 812 pinctrl-0 = <&pinctrl_usdhc2>; 813 bus-width = <4>; 814 non-removable; 815 vmmc-supply = <®_wlan_vmmc>; 816 cap-power-off-card; 817 keep-power-in-suspend; 818 status = "okay"; 819 820 #address-cells = <1>; 821 #size-cells = <0>; 822 wlcore: wlcore@2 { 823 compatible = "ti,wl1271"; 824 reg = <2>; 825 interrupt-parent = <&gpio6>; 826 interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; 827 ref-clock-frequency = <38400000>; 828 }; 829 }; 830 831 &usdhc3 { 832 pinctrl-names = "default"; 833 pinctrl-0 = <&pinctrl_usdhc3>; 834 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; 835 bus-width = <4>; 836 vmmc-supply = <®_3p3v>; 837 status = "okay"; 838 }; 839 840 &usdhc4 { 841 pinctrl-names = "default"; 842 pinctrl-0 = <&pinctrl_usdhc4>; 843 bus-width = <8>; 844 non-removable; 845 vmmc-supply = <®_1p8v>; 846 keep-power-in-suspend; 847 status = "okay"; 848 };
Cache object: 77fef89e4983460ff05924fc3f812cae
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