Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/contrib/device-tree/src/arm/imx6qdl-pico.dtsi
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1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 // 3 // Copyright 2018 Technexion Ltd. 4 // 5 // Author: Wig Cheng <wig.cheng@technexion.com> 6 // Richard Hu <richard.hu@technexion.com> 7 // Tapani Utriainen <tapani@technexion.com> 8 9 #include <dt-bindings/gpio/gpio.h> 10 11 / { 12 chosen { 13 stdout-path = &uart1; 14 }; 15 16 reg_2p5v: regulator-2p5v { 17 compatible = "regulator-fixed"; 18 regulator-name = "2P5V"; 19 regulator-min-microvolt = <2500000>; 20 regulator-max-microvolt = <2500000>; 21 regulator-always-on; 22 }; 23 24 reg_3p3v: regulator-3p3v { 25 compatible = "regulator-fixed"; 26 regulator-name = "3P3V"; 27 regulator-min-microvolt = <3300000>; 28 regulator-max-microvolt = <3300000>; 29 regulator-always-on; 30 }; 31 32 reg_1p8v: regulator-1p8v { 33 compatible = "regulator-fixed"; 34 regulator-name = "1P8V"; 35 regulator-min-microvolt = <1800000>; 36 regulator-max-microvolt = <1800000>; 37 regulator-always-on; 38 }; 39 40 reg_1p5v: regulator-1p5v { 41 compatible = "regulator-fixed"; 42 regulator-name = "1P5V"; 43 regulator-min-microvolt = <1500000>; 44 regulator-max-microvolt = <1500000>; 45 regulator-always-on; 46 }; 47 48 reg_2p8v: regulator-2p8v { 49 compatible = "regulator-fixed"; 50 regulator-name = "2P8V"; 51 regulator-min-microvolt = <2800000>; 52 regulator-max-microvolt = <2800000>; 53 regulator-always-on; 54 }; 55 56 reg_usb_otg_vbus: regulator-usb-otg-vbus { 57 pinctrl-names = "default"; 58 pinctrl-0 = <&pinctrl_usbotg_vbus>; 59 compatible = "regulator-fixed"; 60 regulator-name = "usb_otg_vbus"; 61 regulator-min-microvolt = <5000000>; 62 regulator-max-microvolt = <5000000>; 63 gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; 64 }; 65 66 codec_osc: clock { 67 compatible = "fixed-clock"; 68 #clock-cells = <0>; 69 clock-frequency = <24576000>; 70 }; 71 72 sound { 73 compatible = "fsl,imx-audio-sgtl5000"; 74 model = "imx6-pico-sgtl5000"; 75 ssi-controller = <&ssi1>; 76 audio-codec = <&sgtl5000>; 77 audio-routing = 78 "MIC_IN", "Mic Jack", 79 "Mic Jack", "Mic Bias", 80 "Headphone Jack", "HP_OUT"; 81 mux-int-port = <1>; 82 mux-ext-port = <3>; 83 }; 84 85 backlight: backlight { 86 compatible = "pwm-backlight"; 87 pwms = <&pwm4 0 50000 0>; 88 brightness-levels = <0 36 72 108 144 180 216 255>; 89 default-brightness-level = <6>; 90 status = "okay"; 91 }; 92 93 reg_lcd_3v3: regulator-lcd-3v3 { 94 compatible = "regulator-fixed"; 95 pinctrl-names = "default"; 96 pinctrl-0 = <&pinctrl_reg_lcd>; 97 regulator-name = "lcd-3v3"; 98 regulator-min-microvolt = <3300000>; 99 regulator-max-microvolt = <3300000>; 100 gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; 101 enable-active-high; 102 }; 103 104 lcd_display: disp0 { 105 compatible = "fsl,imx-parallel-display"; 106 #address-cells = <1>; 107 #size-cells = <0>; 108 pinctrl-names = "default"; 109 pinctrl-0 = <&pinctrl_ipu1>; 110 status = "okay"; 111 112 port@0 { 113 reg = <0>; 114 115 lcd_display_in: endpoint { 116 remote-endpoint = <&ipu1_di0_disp0>; 117 }; 118 }; 119 120 port@1 { 121 reg = <1>; 122 123 lcd_display_out: endpoint { 124 remote-endpoint = <&lcd_panel_in>; 125 }; 126 }; 127 }; 128 129 panel { 130 compatible = "vxt,vl050-8048nt-c01"; 131 backlight = <&backlight>; 132 power-supply = <®_lcd_3v3>; 133 134 port { 135 lcd_panel_in: endpoint { 136 remote-endpoint = <&lcd_display_out>; 137 }; 138 }; 139 }; 140 }; 141 142 &audmux { 143 pinctrl-names = "default"; 144 pinctrl-0 = <&pinctrl_audmux>; 145 status = "okay"; 146 }; 147 148 &can1 { 149 pinctrl-names = "default"; 150 pinctrl-0 = <&pinctrl_flexcan1>; 151 status = "okay"; 152 }; 153 154 &can2 { 155 pinctrl-names = "default"; 156 pinctrl-0 = <&pinctrl_flexcan2>; 157 status = "okay"; 158 }; 159 160 &clks { 161 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 162 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 163 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 164 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 165 }; 166 167 &ecspi2 { 168 pinctrl-names = "default"; 169 pinctrl-0 = <&pinctrl_ecspi2>; 170 cs-gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; 171 status = "okay"; 172 }; 173 174 &fec { 175 pinctrl-names = "default"; 176 pinctrl-0 = <&pinctrl_enet>; 177 phy-mode = "rgmii-id"; 178 phy-reset-gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; 179 phy-handle = <&phy>; 180 status = "okay"; 181 182 mdio { 183 #address-cells = <1>; 184 #size-cells = <0>; 185 186 phy: ethernet-phy@1 { 187 reg = <1>; 188 qca,clk-out-frequency = <125000000>; 189 }; 190 }; 191 }; 192 193 &hdmi { 194 ddc-i2c-bus = <&i2c2>; 195 status = "okay"; 196 }; 197 198 &i2c1 { 199 pinctrl-names = "default"; 200 pinctrl-0 = <&pinctrl_i2c1>; 201 status = "okay"; 202 203 sgtl5000: audio-codec@a { 204 #sound-dai-cells = <0>; 205 reg = <0x0a>; 206 compatible = "fsl,sgtl5000"; 207 clocks = <&codec_osc>; 208 VDDA-supply = <®_2p5v>; 209 VDDIO-supply = <®_1p8v>; 210 }; 211 }; 212 213 &i2c2 { 214 clock-frequency = <100000>; 215 pinctrl-names = "default"; 216 pinctrl-0 = <&pinctrl_i2c2>; 217 status = "okay"; 218 219 touchscreen@38 { 220 compatible = "edt,edt-ft5x06"; 221 reg = <0x38>; 222 interrupt-parent = <&gpio5>; 223 interrupts = <31 IRQ_TYPE_EDGE_FALLING>; 224 reset-gpios = <&gpio5 27 GPIO_ACTIVE_LOW>; 225 touchscreen-size-x = <800>; 226 touchscreen-size-y = <480>; 227 wakeup-source; 228 }; 229 230 camera@3c { 231 compatible = "ovti,ov5645"; 232 pinctrl-names = "default"; 233 pinctrl-0 = <&pinctrl_ov5645>; 234 reg = <0x3c>; 235 clocks = <&clks IMX6QDL_CLK_CKO2>; 236 clock-names = "xclk"; 237 clock-frequency = <24000000>; 238 vdddo-supply = <®_1p8v>; 239 vdda-supply = <®_2p8v>; 240 vddd-supply = <®_1p5v>; 241 enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; 242 reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; 243 244 port { 245 ov5645_to_mipi_csi2: endpoint { 246 remote-endpoint = <&mipi_csi2_in>; 247 clock-lanes = <0>; 248 data-lanes = <1 2>; 249 }; 250 }; 251 }; 252 }; 253 254 &i2c3 { 255 pinctrl-names = "default"; 256 pinctrl-0 = <&pinctrl_i2c3>; 257 status = "okay"; 258 }; 259 260 &ipu1_di0_disp0 { 261 remote-endpoint = <&lcd_display_in>; 262 }; 263 264 &mipi_csi { 265 status = "okay"; 266 267 port@0 { 268 reg = <0>; 269 270 mipi_csi2_in: endpoint { 271 remote-endpoint = <&ov5645_to_mipi_csi2>; 272 clock-lanes = <0>; 273 data-lanes = <1 2>; 274 }; 275 }; 276 }; 277 278 &pcie { 279 pinctrl-names = "default"; 280 pinctrl-0 = <&pinctrl_pcie_reset>; 281 reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>; 282 }; 283 284 &pwm1 { 285 pinctrl-names = "default"; 286 pinctrl-0 = <&pinctrl_pwm1>; 287 status = "okay"; 288 }; 289 290 &pwm2 { 291 pinctrl-names = "default"; 292 pinctrl-0 = <&pinctrl_pwm2>; 293 status = "okay"; 294 }; 295 296 &pwm3 { 297 pinctrl-names = "default"; 298 pinctrl-0 = <&pinctrl_pwm3>; 299 status = "okay"; 300 }; 301 302 &pwm4 { 303 pinctrl-names = "default"; 304 pinctrl-0 = <&pinctrl_pwm4>; 305 status = "okay"; 306 }; 307 308 &ssi1 { 309 status = "okay"; 310 }; 311 312 &uart1 { 313 pinctrl-names = "default"; 314 pinctrl-0 = <&pinctrl_uart1>; 315 status = "okay"; 316 }; 317 318 &uart2 { /* Bluetooth module */ 319 pinctrl-names = "default"; 320 pinctrl-0 = <&pinctrl_uart2>; 321 uart-has-rtscts; 322 status = "okay"; 323 }; 324 325 &uart3 { 326 pinctrl-names = "default"; 327 pinctrl-0 = <&pinctrl_uart3>; 328 uart-has-rtscts; 329 status = "okay"; 330 }; 331 332 &usbh1 { 333 status = "okay"; 334 }; 335 336 &usbotg { 337 vbus-supply = <®_usb_otg_vbus>; 338 pinctrl-names = "default"; 339 pinctrl-0 = <&pinctrl_usbotg>; 340 disable-over-current; 341 dr_mode = "otg"; 342 status = "okay"; 343 }; 344 345 &usdhc1 { 346 pinctrl-names = "default"; 347 pinctrl-0 = <&pinctrl_usdhc1>; 348 bus-width = <8>; 349 cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; 350 status = "okay"; 351 }; 352 353 &usdhc2 { /* Wifi/BT */ 354 pinctrl-names = "default"; 355 pinctrl-0 = <&pinctrl_usdhc2>; 356 bus-width = <4>; 357 no-1-8-v; 358 keep-power-in-suspend; 359 non-removable; 360 status = "okay"; 361 }; 362 363 &usdhc3 { 364 pinctrl-names = "default"; 365 pinctrl-0 = <&pinctrl_usdhc3>; 366 bus-width = <8>; 367 no-1-8-v; 368 non-removable; 369 status = "okay"; 370 }; 371 372 &iomuxc { 373 pinctrl-names = "default"; 374 pinctrl-0 = <&pinctrl_hog>; 375 376 pinctrl_hog: hoggrp { 377 fsl,pins = < 378 MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x4001b0b5 /* PICO_P24 */ 379 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x4001b0b5 /* PICO_P26 */ 380 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b5 /* PICO_P28 */ 381 MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b0b5 /* PICO_P30 */ 382 MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b0b5 /* PICO_P32 */ 383 MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x4001b0b5 /* PICO_P34 */ 384 MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x4001b0b5 /* PICO_P42 */ 385 MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x4001b0b5 /* PICO_P44 */ 386 MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x4001b0b5 /* PICO_P48 */ 387 >; 388 }; 389 390 pinctrl_audmux: audmuxgrp { 391 fsl,pins = < 392 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 393 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 394 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 395 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 396 >; 397 }; 398 399 pinctrl_ecspi1: ecspi1grp { 400 fsl,pins = < 401 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 402 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 403 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 404 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x000f0b0 405 >; 406 }; 407 408 pinctrl_ecspi2: ecspi2grp { 409 fsl,pins = < 410 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x1b0b1 411 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x1b0b1 412 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x1b0b1 413 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000f0b0 414 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x000f0b0 415 >; 416 }; 417 418 pinctrl_enet: enetgrp { 419 fsl,pins = < 420 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 421 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 422 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 423 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 424 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 425 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 426 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 427 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 428 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 429 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 430 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 431 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 432 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 433 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 434 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 435 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 436 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1f0b1 437 >; 438 }; 439 440 pinctrl_flexcan1: flexcan1grp { 441 fsl,pins = < 442 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 443 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 444 >; 445 }; 446 447 pinctrl_flexcan2: flexcan2grp { 448 fsl,pins = < 449 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 450 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 451 >; 452 }; 453 454 pinctrl_i2c1: i2c1grp { 455 fsl,pins = < 456 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 457 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 458 >; 459 }; 460 461 pinctrl_i2c2: i2c2grp { 462 fsl,pins = < 463 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 464 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 465 >; 466 }; 467 468 pinctrl_i2c3: i2c3grp { 469 fsl,pins = < 470 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 471 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 472 >; 473 }; 474 475 pinctrl_ipu1: ipu1grp { 476 fsl,pins = < 477 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 478 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 479 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 480 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 481 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 482 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 483 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 484 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 485 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 486 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 487 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 488 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 489 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 490 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 491 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 492 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 493 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 494 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 495 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 496 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 497 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 498 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 499 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 500 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 501 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 502 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 503 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 504 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 505 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 506 >; 507 }; 508 509 pinctrl_ov5645: ov5645grp { 510 fsl,pins = < 511 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x0b0b0 512 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0b0b0 513 MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 514 >; 515 }; 516 517 pinctrl_pcie_reset: pciegrp { 518 fsl,pins = < 519 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x130b0 520 >; 521 }; 522 523 pinctrl_pwm1: pwm1grp { 524 fsl,pins = < 525 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 526 >; 527 }; 528 529 pinctrl_pwm2: pwm2grp { 530 fsl,pins = < 531 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 532 >; 533 }; 534 535 pinctrl_pwm3: pwm3grp { 536 fsl,pins = < 537 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 538 >; 539 }; 540 541 pinctrl_pwm4: pwm4grp { 542 fsl,pins = < 543 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 544 >; 545 }; 546 547 pinctrl_reg_lcd: reglcdgrp { 548 fsl,pins = < 549 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 550 >; 551 }; 552 553 pinctrl_uart1: uart1grp { 554 fsl,pins = < 555 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 556 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 557 >; 558 }; 559 560 pinctrl_uart2: uart2grp { 561 fsl,pins = < 562 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 563 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 564 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 565 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 566 >; 567 }; 568 569 pinctrl_uart3: uart3grp { 570 fsl,pins = < 571 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 572 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 573 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 574 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 575 >; 576 }; 577 578 pinctrl_usbotg: usbotggrp { 579 fsl,pins = < 580 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 581 >; 582 }; 583 584 pinctrl_usbotg_vbus: usbotgvbusgrp { 585 fsl,pins = < 586 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 587 >; 588 }; 589 590 pinctrl_usdhc1: usdhc1grp { 591 fsl,pins = < 592 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 593 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x17071 594 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 595 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 596 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 597 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 598 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 599 >; 600 }; 601 602 pinctrl_usdhc2: usdhc2grp { 603 fsl,pins = < 604 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 605 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 606 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 607 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 608 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 609 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 610 >; 611 }; 612 613 pinctrl_usdhc3: usdhc3grp { 614 fsl,pins = < 615 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 616 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 617 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 618 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 619 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 620 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 621 MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0xb0b1 622 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 623 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 624 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 625 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 626 >; 627 }; 628 };
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