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sys/contrib/device-tree/src/arm/imx6qdl-sabresd.dtsi
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1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Copyright 2012 Freescale Semiconductor, Inc. 4 // Copyright 2011 Linaro Ltd. 5 6 #include <dt-bindings/clock/imx6qdl-clock.h> 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/input/input.h> 9 10 / { 11 chosen { 12 stdout-path = &uart1; 13 }; 14 15 memory@10000000 { 16 device_type = "memory"; 17 reg = <0x10000000 0x40000000>; 18 }; 19 20 reg_usb_otg_vbus: regulator-usb-otg-vbus { 21 compatible = "regulator-fixed"; 22 regulator-name = "usb_otg_vbus"; 23 regulator-min-microvolt = <5000000>; 24 regulator-max-microvolt = <5000000>; 25 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 26 enable-active-high; 27 vin-supply = <&swbst_reg>; 28 }; 29 30 reg_usb_h1_vbus: regulator-usb-h1-vbus { 31 compatible = "regulator-fixed"; 32 regulator-name = "usb_h1_vbus"; 33 regulator-min-microvolt = <5000000>; 34 regulator-max-microvolt = <5000000>; 35 gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; 36 enable-active-high; 37 vin-supply = <&swbst_reg>; 38 }; 39 40 reg_audio: regulator-audio { 41 compatible = "regulator-fixed"; 42 regulator-name = "wm8962-supply"; 43 gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>; 44 enable-active-high; 45 }; 46 47 reg_pcie: regulator-pcie { 48 compatible = "regulator-fixed"; 49 pinctrl-names = "default"; 50 pinctrl-0 = <&pinctrl_pcie_reg>; 51 regulator-name = "MPCIE_3V3"; 52 regulator-min-microvolt = <3300000>; 53 regulator-max-microvolt = <3300000>; 54 gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; 55 enable-active-high; 56 }; 57 58 reg_sensors: regulator-sensors { 59 compatible = "regulator-fixed"; 60 pinctrl-names = "default"; 61 pinctrl-0 = <&pinctrl_sensors_reg>; 62 regulator-name = "sensors-supply"; 63 regulator-min-microvolt = <3300000>; 64 regulator-max-microvolt = <3300000>; 65 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; 66 enable-active-high; 67 }; 68 69 gpio-keys { 70 compatible = "gpio-keys"; 71 pinctrl-names = "default"; 72 pinctrl-0 = <&pinctrl_gpio_keys>; 73 74 power { 75 label = "Power Button"; 76 gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; 77 wakeup-source; 78 linux,code = <KEY_POWER>; 79 }; 80 81 volume-up { 82 label = "Volume Up"; 83 gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; 84 wakeup-source; 85 linux,code = <KEY_VOLUMEUP>; 86 }; 87 88 volume-down { 89 label = "Volume Down"; 90 gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; 91 wakeup-source; 92 linux,code = <KEY_VOLUMEDOWN>; 93 }; 94 }; 95 96 sound { 97 compatible = "fsl,imx6q-sabresd-wm8962", 98 "fsl,imx-audio-wm8962"; 99 model = "wm8962-audio"; 100 pinctrl-names = "default"; 101 pinctrl-0 = <&pinctrl_hp>; 102 ssi-controller = <&ssi2>; 103 audio-codec = <&codec>; 104 audio-asrc = <&asrc>; 105 audio-routing = 106 "Headphone Jack", "HPOUTL", 107 "Headphone Jack", "HPOUTR", 108 "Ext Spk", "SPKOUTL", 109 "Ext Spk", "SPKOUTR", 110 "AMIC", "MICBIAS", 111 "IN3R", "AMIC", 112 "DMIC", "MICBIAS", 113 "DMICDAT", "DMIC"; 114 mux-int-port = <2>; 115 mux-ext-port = <3>; 116 hp-det-gpio = <&gpio7 8 GPIO_ACTIVE_LOW>; 117 mic-det-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; 118 }; 119 120 backlight_lvds: backlight-lvds { 121 compatible = "pwm-backlight"; 122 pwms = <&pwm1 0 5000000>; 123 brightness-levels = <0 4 8 16 32 64 128 255>; 124 default-brightness-level = <7>; 125 status = "okay"; 126 }; 127 128 leds { 129 compatible = "gpio-leds"; 130 pinctrl-names = "default"; 131 pinctrl-0 = <&pinctrl_gpio_leds>; 132 133 red { 134 gpios = <&gpio1 2 0>; 135 default-state = "on"; 136 }; 137 }; 138 139 panel { 140 compatible = "hannstar,hsd100pxn1"; 141 backlight = <&backlight_lvds>; 142 143 port { 144 panel_in: endpoint { 145 remote-endpoint = <&lvds0_out>; 146 }; 147 }; 148 }; 149 }; 150 151 &ipu1_csi0_from_ipu1_csi0_mux { 152 bus-width = <8>; 153 data-shift = <12>; /* Lines 19:12 used */ 154 hsync-active = <1>; 155 vsync-active = <1>; 156 }; 157 158 &ipu1_csi0_mux_from_parallel_sensor { 159 remote-endpoint = <&ov5642_to_ipu1_csi0_mux>; 160 }; 161 162 &ipu1_csi0 { 163 pinctrl-names = "default"; 164 pinctrl-0 = <&pinctrl_ipu1_csi0>; 165 }; 166 167 &mipi_csi { 168 status = "okay"; 169 170 port@0 { 171 reg = <0>; 172 173 mipi_csi2_in: endpoint { 174 remote-endpoint = <&ov5640_to_mipi_csi2>; 175 clock-lanes = <0>; 176 data-lanes = <1 2>; 177 }; 178 }; 179 }; 180 181 &audmux { 182 pinctrl-names = "default"; 183 pinctrl-0 = <&pinctrl_audmux>; 184 status = "okay"; 185 }; 186 187 &clks { 188 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 189 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 190 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 191 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 192 }; 193 194 &ecspi1 { 195 cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; 196 pinctrl-names = "default"; 197 pinctrl-0 = <&pinctrl_ecspi1>; 198 status = "okay"; 199 200 flash: flash@0 { 201 #address-cells = <1>; 202 #size-cells = <1>; 203 compatible = "st,m25p32", "jedec,spi-nor"; 204 spi-max-frequency = <20000000>; 205 reg = <0>; 206 }; 207 }; 208 209 &fec { 210 pinctrl-names = "default"; 211 pinctrl-0 = <&pinctrl_enet>; 212 phy-mode = "rgmii-id"; 213 phy-handle = <&phy>; 214 fsl,magic-packet; 215 status = "okay"; 216 217 mdio { 218 #address-cells = <1>; 219 #size-cells = <0>; 220 221 phy: ethernet-phy@1 { 222 reg = <1>; 223 qca,clk-out-frequency = <125000000>; 224 reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; 225 reset-assert-us = <10000>; 226 }; 227 }; 228 }; 229 230 &hdmi { 231 pinctrl-names = "default"; 232 pinctrl-0 = <&pinctrl_hdmi_cec>; 233 ddc-i2c-bus = <&i2c2>; 234 status = "okay"; 235 }; 236 237 &i2c1 { 238 clock-frequency = <100000>; 239 pinctrl-names = "default"; 240 pinctrl-0 = <&pinctrl_i2c1>; 241 status = "okay"; 242 243 codec: wm8962@1a { 244 compatible = "wlf,wm8962"; 245 reg = <0x1a>; 246 clocks = <&clks IMX6QDL_CLK_CKO>; 247 DCVDD-supply = <®_audio>; 248 DBVDD-supply = <®_audio>; 249 AVDD-supply = <®_audio>; 250 CPVDD-supply = <®_audio>; 251 MICVDD-supply = <®_audio>; 252 PLLVDD-supply = <®_audio>; 253 SPKVDD1-supply = <®_audio>; 254 SPKVDD2-supply = <®_audio>; 255 gpio-cfg = < 256 0x0000 /* 0:Default */ 257 0x0000 /* 1:Default */ 258 0x0013 /* 2:FN_DMICCLK */ 259 0x0000 /* 3:Default */ 260 0x8014 /* 4:FN_DMICCDAT */ 261 0x0000 /* 5:Default */ 262 >; 263 }; 264 265 accelerometer@1c { 266 compatible = "fsl,mma8451"; 267 reg = <0x1c>; 268 pinctrl-names = "default"; 269 pinctrl-0 = <&pinctrl_i2c1_mma8451_int>; 270 interrupt-parent = <&gpio1>; 271 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 272 vdd-supply = <®_sensors>; 273 vddio-supply = <®_sensors>; 274 }; 275 276 ov5642: camera@3c { 277 compatible = "ovti,ov5642"; 278 pinctrl-names = "default"; 279 pinctrl-0 = <&pinctrl_ov5642>; 280 clocks = <&clks IMX6QDL_CLK_CKO>; 281 clock-names = "xclk"; 282 reg = <0x3c>; 283 DOVDD-supply = <&vgen4_reg>; /* 1.8v */ 284 AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3 285 rev B board is VGEN5 */ 286 DVDD-supply = <&vgen2_reg>; /* 1.5v*/ 287 powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; 288 reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; 289 status = "disabled"; 290 291 port { 292 ov5642_to_ipu1_csi0_mux: endpoint { 293 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; 294 bus-width = <8>; 295 hsync-active = <1>; 296 vsync-active = <1>; 297 }; 298 }; 299 }; 300 }; 301 302 &i2c2 { 303 clock-frequency = <100000>; 304 pinctrl-names = "default"; 305 pinctrl-0 = <&pinctrl_i2c2>; 306 status = "okay"; 307 308 touchscreen@4 { 309 compatible = "eeti,egalax_ts"; 310 reg = <0x04>; 311 pinctrl-names = "default"; 312 pinctrl-0 = <&pinctrl_i2c2_egalax_int>; 313 interrupt-parent = <&gpio6>; 314 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 315 wakeup-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; 316 }; 317 318 ov5640: camera@3c { 319 compatible = "ovti,ov5640"; 320 pinctrl-names = "default"; 321 pinctrl-0 = <&pinctrl_ov5640>; 322 reg = <0x3c>; 323 clocks = <&clks IMX6QDL_CLK_CKO>; 324 clock-names = "xclk"; 325 DOVDD-supply = <&vgen4_reg>; /* 1.8v */ 326 AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3 327 rev B board is VGEN5 */ 328 DVDD-supply = <&vgen2_reg>; /* 1.5v*/ 329 powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; 330 reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; 331 332 port { 333 ov5640_to_mipi_csi2: endpoint { 334 remote-endpoint = <&mipi_csi2_in>; 335 clock-lanes = <0>; 336 data-lanes = <1 2>; 337 }; 338 }; 339 }; 340 341 pmic: pfuze100@8 { 342 compatible = "fsl,pfuze100"; 343 reg = <0x08>; 344 345 regulators { 346 sw1a_reg: sw1ab { 347 regulator-min-microvolt = <300000>; 348 regulator-max-microvolt = <1875000>; 349 regulator-boot-on; 350 regulator-always-on; 351 regulator-ramp-delay = <6250>; 352 }; 353 354 sw1c_reg: sw1c { 355 regulator-min-microvolt = <300000>; 356 regulator-max-microvolt = <1875000>; 357 regulator-boot-on; 358 regulator-always-on; 359 regulator-ramp-delay = <6250>; 360 }; 361 362 sw2_reg: sw2 { 363 regulator-min-microvolt = <800000>; 364 regulator-max-microvolt = <3300000>; 365 regulator-boot-on; 366 regulator-always-on; 367 regulator-ramp-delay = <6250>; 368 }; 369 370 sw3a_reg: sw3a { 371 regulator-min-microvolt = <400000>; 372 regulator-max-microvolt = <1975000>; 373 regulator-boot-on; 374 regulator-always-on; 375 }; 376 377 sw3b_reg: sw3b { 378 regulator-min-microvolt = <400000>; 379 regulator-max-microvolt = <1975000>; 380 regulator-boot-on; 381 regulator-always-on; 382 }; 383 384 sw4_reg: sw4 { 385 regulator-min-microvolt = <800000>; 386 regulator-max-microvolt = <3300000>; 387 regulator-always-on; 388 }; 389 390 swbst_reg: swbst { 391 regulator-min-microvolt = <5000000>; 392 regulator-max-microvolt = <5150000>; 393 }; 394 395 snvs_reg: vsnvs { 396 regulator-min-microvolt = <1000000>; 397 regulator-max-microvolt = <3000000>; 398 regulator-boot-on; 399 regulator-always-on; 400 }; 401 402 vref_reg: vrefddr { 403 regulator-boot-on; 404 regulator-always-on; 405 }; 406 407 vgen1_reg: vgen1 { 408 regulator-min-microvolt = <800000>; 409 regulator-max-microvolt = <1550000>; 410 }; 411 412 vgen2_reg: vgen2 { 413 regulator-min-microvolt = <800000>; 414 regulator-max-microvolt = <1550000>; 415 }; 416 417 vgen3_reg: vgen3 { 418 regulator-min-microvolt = <1800000>; 419 regulator-max-microvolt = <3300000>; 420 }; 421 422 vgen4_reg: vgen4 { 423 regulator-min-microvolt = <1800000>; 424 regulator-max-microvolt = <3300000>; 425 regulator-always-on; 426 }; 427 428 vgen5_reg: vgen5 { 429 regulator-min-microvolt = <1800000>; 430 regulator-max-microvolt = <3300000>; 431 regulator-always-on; 432 }; 433 434 vgen6_reg: vgen6 { 435 regulator-min-microvolt = <1800000>; 436 regulator-max-microvolt = <3300000>; 437 regulator-always-on; 438 }; 439 }; 440 }; 441 }; 442 443 &i2c3 { 444 clock-frequency = <100000>; 445 pinctrl-names = "default"; 446 pinctrl-0 = <&pinctrl_i2c3>; 447 status = "okay"; 448 449 egalax_ts@4 { 450 compatible = "eeti,egalax_ts"; 451 reg = <0x04>; 452 interrupt-parent = <&gpio6>; 453 interrupts = <7 2>; 454 wakeup-gpios = <&gpio6 7 0>; 455 }; 456 457 magnetometer@e { 458 compatible = "fsl,mag3110"; 459 reg = <0x0e>; 460 pinctrl-names = "default"; 461 pinctrl-0 = <&pinctrl_i2c3_mag3110_int>; 462 interrupt-parent = <&gpio3>; 463 interrupts = <16 IRQ_TYPE_EDGE_RISING>; 464 vdd-supply = <®_sensors>; 465 vddio-supply = <®_sensors>; 466 }; 467 468 light-sensor@44 { 469 compatible = "isil,isl29023"; 470 reg = <0x44>; 471 pinctrl-names = "default"; 472 pinctrl-0 = <&pinctrl_i2c3_isl29023_int>; 473 interrupt-parent = <&gpio3>; 474 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 475 vcc-supply = <®_sensors>; 476 }; 477 }; 478 479 &iomuxc { 480 pinctrl-names = "default"; 481 pinctrl-0 = <&pinctrl_hog>; 482 483 imx6qdl-sabresd { 484 pinctrl_hog: hoggrp { 485 fsl,pins = < 486 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 487 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 488 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 489 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 490 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 491 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 492 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 493 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 494 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 495 >; 496 }; 497 498 pinctrl_audmux: audmuxgrp { 499 fsl,pins = < 500 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 501 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 502 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 503 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 504 >; 505 }; 506 507 pinctrl_ecspi1: ecspi1grp { 508 fsl,pins = < 509 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 510 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 511 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 512 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 513 >; 514 }; 515 516 pinctrl_enet: enetgrp { 517 fsl,pins = < 518 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 519 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 520 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 521 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 522 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 523 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 524 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 525 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 526 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 527 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 528 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 529 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 530 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 531 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 532 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 533 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 534 >; 535 }; 536 537 pinctrl_gpio_keys: gpio_keysgrp { 538 fsl,pins = < 539 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 540 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 541 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 542 >; 543 }; 544 545 pinctrl_hdmi_cec: hdmicecgrp { 546 fsl,pins = < 547 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 548 >; 549 }; 550 551 pinctrl_hp: hpgrp { 552 fsl,pins = < 553 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 554 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 555 >; 556 }; 557 558 pinctrl_i2c1: i2c1grp { 559 fsl,pins = < 560 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 561 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 562 >; 563 }; 564 565 pinctrl_i2c1_mma8451_int: i2c1mma8451intgrp { 566 fsl,pins = < 567 MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0xb0b1 568 >; 569 }; 570 571 pinctrl_i2c2: i2c2grp { 572 fsl,pins = < 573 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 574 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 575 >; 576 }; 577 578 pinctrl_i2c2_egalax_int: i2c2egalaxintgrp { 579 fsl,pins = < 580 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 581 >; 582 }; 583 584 pinctrl_i2c3: i2c3grp { 585 fsl,pins = < 586 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 587 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 588 >; 589 }; 590 591 pinctrl_i2c3_isl29023_int: i2c3isl29023intgrp { 592 fsl,pins = < 593 MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0xb0b1 594 >; 595 }; 596 597 pinctrl_i2c3_mag3110_int: i2c3mag3110intgrp { 598 fsl,pins = < 599 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0xb0b1 600 >; 601 }; 602 603 pinctrl_ipu1_csi0: ipu1csi0grp { 604 fsl,pins = < 605 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 606 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 607 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 608 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 609 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 610 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 611 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 612 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 613 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 614 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 615 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 616 >; 617 }; 618 619 pinctrl_ov5640: ov5640grp { 620 fsl,pins = < 621 MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 622 MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0 623 >; 624 }; 625 626 pinctrl_ov5642: ov5642grp { 627 fsl,pins = < 628 MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 629 MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 630 >; 631 }; 632 633 pinctrl_pcie: pciegrp { 634 fsl,pins = < 635 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 636 >; 637 }; 638 639 pinctrl_pcie_reg: pciereggrp { 640 fsl,pins = < 641 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 642 >; 643 }; 644 645 pinctrl_pwm1: pwm1grp { 646 fsl,pins = < 647 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 648 >; 649 }; 650 651 pinctrl_sensors_reg: sensorsreggrp { 652 fsl,pins = < 653 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 654 >; 655 }; 656 657 pinctrl_uart1: uart1grp { 658 fsl,pins = < 659 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 660 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 661 >; 662 }; 663 664 pinctrl_usbotg: usbotggrp { 665 fsl,pins = < 666 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 667 >; 668 }; 669 670 pinctrl_usdhc2: usdhc2grp { 671 fsl,pins = < 672 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 673 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 674 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 675 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 676 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 677 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 678 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 679 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 680 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 681 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 682 >; 683 }; 684 685 pinctrl_usdhc3: usdhc3grp { 686 fsl,pins = < 687 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 688 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 689 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 690 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 691 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 692 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 693 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 694 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 695 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 696 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 697 >; 698 }; 699 700 pinctrl_usdhc4: usdhc4grp { 701 fsl,pins = < 702 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 703 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 704 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 705 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 706 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 707 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 708 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 709 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 710 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 711 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 712 >; 713 }; 714 715 pinctrl_wdog: wdoggrp { 716 fsl,pins = < 717 MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0 718 >; 719 }; 720 }; 721 722 gpio_leds { 723 pinctrl_gpio_leds: gpioledsgrp { 724 fsl,pins = < 725 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 726 >; 727 }; 728 }; 729 }; 730 731 &ldb { 732 status = "okay"; 733 734 lvds-channel@1 { 735 fsl,data-mapping = "spwg"; 736 fsl,data-width = <18>; 737 status = "okay"; 738 739 port@4 { 740 reg = <4>; 741 742 lvds0_out: endpoint { 743 remote-endpoint = <&panel_in>; 744 }; 745 }; 746 }; 747 }; 748 749 &pcie { 750 pinctrl-names = "default"; 751 pinctrl-0 = <&pinctrl_pcie>; 752 reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; 753 vpcie-supply = <®_pcie>; 754 status = "okay"; 755 }; 756 757 &pwm1 { 758 #pwm-cells = <2>; 759 pinctrl-names = "default"; 760 pinctrl-0 = <&pinctrl_pwm1>; 761 status = "okay"; 762 }; 763 764 ®_arm { 765 vin-supply = <&sw1a_reg>; 766 }; 767 768 ®_pu { 769 vin-supply = <&sw1c_reg>; 770 }; 771 772 ®_soc { 773 vin-supply = <&sw1c_reg>; 774 }; 775 776 ®_vdd1p1 { 777 vin-supply = <&vgen5_reg>; 778 }; 779 780 ®_vdd2p5 { 781 vin-supply = <&vgen5_reg>; 782 }; 783 784 &snvs_poweroff { 785 status = "okay"; 786 }; 787 788 &snvs_pwrkey { 789 status = "okay"; 790 }; 791 792 &ssi2 { 793 status = "okay"; 794 }; 795 796 &uart1 { 797 pinctrl-names = "default"; 798 pinctrl-0 = <&pinctrl_uart1>; 799 status = "okay"; 800 }; 801 802 &usbh1 { 803 vbus-supply = <®_usb_h1_vbus>; 804 status = "okay"; 805 }; 806 807 &usbotg { 808 vbus-supply = <®_usb_otg_vbus>; 809 pinctrl-names = "default"; 810 pinctrl-0 = <&pinctrl_usbotg>; 811 disable-over-current; 812 status = "okay"; 813 }; 814 815 &usdhc2 { 816 pinctrl-names = "default"; 817 pinctrl-0 = <&pinctrl_usdhc2>; 818 bus-width = <8>; 819 cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; 820 wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; 821 status = "okay"; 822 }; 823 824 &usdhc3 { 825 pinctrl-names = "default"; 826 pinctrl-0 = <&pinctrl_usdhc3>; 827 bus-width = <8>; 828 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 829 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; 830 status = "okay"; 831 }; 832 833 &usdhc4 { 834 pinctrl-names = "default"; 835 pinctrl-0 = <&pinctrl_usdhc4>; 836 bus-width = <8>; 837 non-removable; 838 no-1-8-v; 839 status = "okay"; 840 }; 841 842 &wdog1 { 843 status = "disabled"; 844 }; 845 846 &wdog2 { 847 pinctrl-names = "default"; 848 pinctrl-0 = <&pinctrl_wdog>; 849 fsl,ext-reset-output; 850 status = "okay"; 851 };
Cache object: 07b7b0996c82552a2269b193e2105067
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