The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/imx6qdl-savageboard.dtsi

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    1 /*
    2  * Copyright (C) 2017 Milo Kim <woogyom.kim@gmail.com>
    3  *
    4  * This file is dual-licensed: you can use it either under the terms
    5  * of the GPL or the X11 license, at your option. Note that this dual
    6  * licensing only applies to this file, and not this project as a
    7  * whole.
    8  *
    9  *  a) This file is free software; you can redistribute it and/or
   10  *     modify it under the terms of the GNU General Public License as
   11  *     published by the Free Software Foundation; either version 2 of the
   12  *     License, or (at your option) any later version.
   13  *
   14  *     This file is distributed in the hope that it will be useful,
   15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
   16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   17  *     GNU General Public License for more details.
   18  *
   19  * Or, alternatively,
   20  *
   21  *  b) Permission is hereby granted, free of charge, to any person
   22  *     obtaining a copy of this software and associated documentation
   23  *     files (the "Software"), to deal in the Software without
   24  *     restriction, including without limitation the rights to use,
   25  *     copy, modify, merge, publish, distribute, sublicense, and/or
   26  *     sell copies of the Software, and to permit persons to whom the
   27  *     Software is furnished to do so, subject to the following
   28  *     conditions:
   29  *
   30  *     The above copyright notice and this permission notice shall be
   31  *     included in all copies or substantial portions of the Software.
   32  *
   33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
   34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
   35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
   36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
   37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
   38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
   39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
   40  *     OTHER DEALINGS IN THE SOFTWARE.
   41  */
   42 
   43 #include <dt-bindings/gpio/gpio.h>
   44 #include <dt-bindings/input/input.h>
   45 
   46 / {
   47         chosen {
   48                 stdout-path = &uart1;
   49         };
   50 
   51         memory@10000000 {
   52                 device_type = "memory";
   53                 reg = <0x10000000 0x40000000>;
   54         };
   55 
   56         gpio-keys {
   57                 compatible = "gpio-keys";
   58                 pinctrl-names = "default";
   59                 pinctrl-0 = <&pinctrl_gpio_keys>;
   60 
   61                 power {
   62                         gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
   63                         label = "Power Button";
   64                         linux,code = <KEY_POWER>;
   65                         wakeup-source;
   66                 };
   67         };
   68 
   69         panel {
   70                 compatible = "avic,tm097tdh02", "hannstar,hsd100pxn1";
   71                 backlight = <&panel_bl>;
   72                 power-supply = <&reg_3p3v>;
   73 
   74                 port {
   75                         panel_in: endpoint {
   76                                 remote-endpoint = <&lvds0_out>;
   77                         };
   78                 };
   79         };
   80 
   81         panel_bl: backlight {
   82                 compatible = "pwm-backlight";
   83                 brightness-levels = <0 4 8 16 32 64 128 255>;
   84                 default-brightness-level = <4>;
   85                 power-supply = <&reg_3p3v>;
   86                 pwms = <&pwm1 0 10000>;
   87         };
   88 
   89         reg_3p3v: regulator-3p3v {
   90                 compatible = "regulator-fixed";
   91                 regulator-name = "3P3V";
   92                 regulator-min-microvolt = <3300000>;
   93                 regulator-max-microvolt = <3300000>;
   94                 regulator-always-on;
   95         };
   96 };
   97 
   98 &clks {
   99         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
  100                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
  101         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
  102                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
  103 };
  104 
  105 &fec {
  106         phy-mode = "rgmii";
  107         phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
  108         pinctrl-names = "default";
  109         pinctrl-0 = <&pinctrl_enet>;
  110         status = "okay";
  111 };
  112 
  113 &hdmi {
  114         ddc-i2c-bus = <&i2c2>;
  115         status = "okay";
  116 };
  117 
  118 &i2c2 {
  119         clock-frequency = <100000>;
  120         pinctrl-names = "default";
  121         pinctrl-0 = <&pinctrl_i2c2>;
  122         status = "okay";
  123 };
  124 
  125 &ldb {
  126         status = "okay";
  127 
  128         lvds-channel@0 {
  129                 reg = <0>;
  130                 status = "okay";
  131 
  132                 port@4 {
  133                         reg = <4>;
  134 
  135                         lvds0_out: endpoint {
  136                                 remote-endpoint = <&panel_in>;
  137                         };
  138                 };
  139         };
  140 };
  141 
  142 &pwm1 {
  143         #pwm-cells = <2>;
  144         pinctrl-names = "default";
  145         pinctrl-0 = <&pinctrl_pwm1>;
  146         status = "okay";
  147 };
  148 
  149 &uart1 {
  150         pinctrl-names = "default";
  151         pinctrl-0 = <&pinctrl_uart1>;
  152         status = "okay";
  153 };
  154 
  155 &usbh1 {
  156         status = "okay";
  157 };
  158 
  159 /* SD card */
  160 &usdhc3 {
  161         bus-width = <4>;
  162         cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
  163         no-1-8-v;
  164         pinctrl-names = "default";
  165         pinctrl-0 = <&pinctrl_sd>;
  166         status = "okay";
  167 };
  168 
  169 /* eMMC */
  170 &usdhc4 {
  171         bus-width = <8>;
  172         keep-power-in-suspend;
  173         no-1-8-v;
  174         non-removable;
  175         pinctrl-names = "default";
  176         pinctrl-0 = <&pinctrl_emmc>;
  177         status = "okay";
  178 };
  179 
  180 &iomuxc {
  181         pinctrl_emmc: emmcgrp {
  182                 fsl,pins = <
  183                         MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
  184                         MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
  185                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
  186                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
  187                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
  188                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
  189                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
  190                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
  191                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
  192                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
  193                 >;
  194         };
  195 
  196         pinctrl_enet: enetgrp {
  197                 fsl,pins = <
  198                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
  199                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
  200                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
  201                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
  202                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
  203                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
  204                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
  205                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
  206                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
  207                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
  208                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
  209                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
  210                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
  211                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
  212                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
  213                         /* PHY reset */
  214                         MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25      0x1b0b0
  215                 >;
  216         };
  217 
  218         pinctrl_gpio_keys: gpiokeysgrp {
  219                 fsl,pins = <
  220                         MX6QDL_PAD_EIM_DA7__GPIO3_IO07          0x1b0b1
  221                 >;
  222         };
  223 
  224         pinctrl_i2c2: i2c2grp {
  225                 fsl,pins = <
  226                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
  227                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
  228                 >;
  229         };
  230 
  231         pinctrl_pwm1: pwm1grp {
  232                 fsl,pins = <
  233                         MX6QDL_PAD_SD1_DAT3__PWM1_OUT           0x1b0b1
  234                 >;
  235         };
  236 
  237         pinctrl_sd: sdgrp {
  238                 fsl,pins = <
  239                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
  240                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
  241                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
  242                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
  243                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
  244                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
  245                         /* CD pin */
  246                         MX6QDL_PAD_NANDF_D0__GPIO2_IO00         0x1b0b1
  247                 >;
  248         };
  249 
  250         pinctrl_uart1: uart1grp {
  251                 fsl,pins = <
  252                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
  253                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
  254                 >;
  255         };
  256 };

Cache object: 4d7f3216bff3f75775b9d417dfec7d98


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