Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/imx6qdl-sr-som.dtsi
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1 /* 2 * Copyright (C) 2013,2014 Russell King 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * version 2 as published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * Or, alternatively, 19 * 20 * b) Permission is hereby granted, free of charge, to any person 21 * obtaining a copy of this software and associated documentation 22 * files (the "Software"), to deal in the Software without 23 * restriction, including without limitation the rights to use, 24 * copy, modify, merge, publish, distribute, sublicense, and/or 25 * sell copies of the Software, and to permit persons to whom the 26 * Software is furnished to do so, subject to the following 27 * conditions: 28 * 29 * The above copyright notice and this permission notice shall be 30 * included in all copies or substantial portions of the Software. 31 * 32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 39 * OTHER DEALINGS IN THE SOFTWARE. 40 */ 41 #include <dt-bindings/gpio/gpio.h> 42 43 / { 44 vcc_3v3: regulator-vcc-3v3 { 45 compatible = "regulator-fixed"; 46 regulator-always-on; 47 regulator-name = "vcc_3v3"; 48 regulator-min-microvolt = <3300000>; 49 regulator-max-microvolt = <3300000>; 50 }; 51 }; 52 53 &fec { 54 pinctrl-names = "default"; 55 pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; 56 phy-mode = "rgmii-id"; 57 58 /* 59 * The PHY seems to require a long-enough reset duration to avoid 60 * some rare issues where the PHY gets stuck in an inconsistent and 61 * non-functional state at boot-up. 10ms proved to be fine . 62 */ 63 phy-reset-duration = <10>; 64 phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; 65 status = "okay"; 66 67 mdio { 68 #address-cells = <1>; 69 #size-cells = <0>; 70 71 /* 72 * The PHY can appear at either address 0 or 4 due to the 73 * configuration (LED) pin not being pulled sufficiently. 74 */ 75 ethernet-phy@0 { 76 reg = <0>; 77 qca,clk-out-frequency = <125000000>; 78 qca,smarteee-tw-us-1g = <24>; 79 }; 80 81 ethernet-phy@4 { 82 reg = <4>; 83 qca,clk-out-frequency = <125000000>; 84 qca,smarteee-tw-us-1g = <24>; 85 }; 86 87 /* 88 * ADIN1300 (som rev 1.9 or later) is always at address 1. It 89 * will be enabled automatically by U-Boot if detected. 90 */ 91 ethernet-phy@1 { 92 reg = <1>; 93 adi,phy-output-clock = "125mhz-free-running"; 94 status = "disabled"; 95 }; 96 }; 97 }; 98 99 &iomuxc { 100 microsom { 101 pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 { 102 fsl,pins = < 103 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 104 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 105 /* AR8035 reset */ 106 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0 107 /* AR8035 interrupt */ 108 MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 109 /* GPIO16 -> AR8035 25MHz */ 110 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0 111 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x13030 112 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 113 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 114 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 115 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 116 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 117 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ 118 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 119 /* AR8035 pin strapping: IO voltage: pull up */ 120 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 121 /* AR8035 pin strapping: PHYADDR#0: pull down */ 122 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 123 /* AR8035 pin strapping: PHYADDR#1: pull down */ 124 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 125 /* AR8035 pin strapping: MODE#1: pull up */ 126 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 127 /* AR8035 pin strapping: MODE#3: pull up */ 128 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 129 /* AR8035 pin strapping: MODE#0: pull down */ 130 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 131 132 /* 133 * As the RMII pins are also connected to RGMII 134 * so that an AR8030 can be placed, set these 135 * to high-z with the same pulls as above. 136 * Use the GPIO settings to avoid changing the 137 * input select registers. 138 */ 139 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x03000 140 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x03000 141 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x03000 142 >; 143 }; 144 145 pinctrl_microsom_uart1: microsom-uart1 { 146 fsl,pins = < 147 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 148 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 149 >; 150 }; 151 }; 152 }; 153 154 &uart1 { 155 pinctrl-names = "default"; 156 pinctrl-0 = <&pinctrl_microsom_uart1>; 157 status = "okay"; 158 };
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