Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/contrib/device-tree/src/arm/imx6qdl-vicut1.dtsi
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1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 /* 3 * Copyright (c) 2014 Protonic Holland 4 * Copyright (c) 2020 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix 5 */ 6 7 #include <dt-bindings/display/sdtv-standards.h> 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/input/input.h> 10 #include <dt-bindings/leds/common.h> 11 #include <dt-bindings/media/tvp5150.h> 12 #include <dt-bindings/sound/fsl-imx-audmux.h> 13 14 / { 15 chosen { 16 stdout-path = &uart4; 17 }; 18 19 backlight_lcd: backlight { 20 compatible = "pwm-backlight"; 21 pinctrl-names = "default"; 22 pinctrl-0 = <&pinctrl_backlight>; 23 pwms = <&pwm1 0 5000000 0>; 24 brightness-levels = <0 16 64 255>; 25 num-interpolated-steps = <16>; 26 default-brightness-level = <48>; 27 power-supply = <®_3v3>; 28 enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; 29 }; 30 31 backlight_led: backlight-led { 32 compatible = "pwm-backlight"; 33 pwms = <&pwm3 0 5000000 0>; 34 brightness-levels = <0 16 64 255>; 35 num-interpolated-steps = <16>; 36 default-brightness-level = <48>; 37 power-supply = <®_3v3>; 38 }; 39 40 connector { 41 compatible = "composite-video-connector"; 42 label = "Composite0"; 43 sdtv-standards = <SDTV_STD_PAL_B>; 44 45 port { 46 comp0_out: endpoint { 47 remote-endpoint = <&tvp5150_comp0_in>; 48 }; 49 }; 50 }; 51 52 counter-0 { 53 compatible = "interrupt-counter"; 54 pinctrl-names = "default"; 55 pinctrl-0 = <&pinctrl_counter0>; 56 gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 57 }; 58 59 counter-1 { 60 compatible = "interrupt-counter"; 61 pinctrl-names = "default"; 62 pinctrl-0 = <&pinctrl_counter1>; 63 gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 64 }; 65 66 counter-2 { 67 compatible = "interrupt-counter"; 68 pinctrl-names = "default"; 69 pinctrl-0 = <&pinctrl_counter2>; 70 gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; 71 }; 72 73 leds { 74 compatible = "gpio-leds"; 75 pinctrl-names = "default"; 76 pinctrl-0 = <&pinctrl_leds>; 77 78 led-0 { 79 label = "debug0"; 80 function = LED_FUNCTION_HEARTBEAT; 81 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; 82 linux,default-trigger = "heartbeat"; 83 }; 84 85 led-1 { 86 label = "debug1"; 87 function = LED_FUNCTION_DISK; 88 gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; 89 linux,default-trigger = "disk-activity"; 90 }; 91 92 led-2 { 93 label = "power_led"; 94 function = LED_FUNCTION_POWER; 95 gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; 96 default-state = "on"; 97 }; 98 99 led-3 { 100 label = "isb_led"; 101 function = LED_FUNCTION_POWER; 102 gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; 103 default-state = "on"; 104 }; 105 }; 106 107 reg_1v8: regulator-1v8 { 108 compatible = "regulator-fixed"; 109 regulator-name = "1v8"; 110 regulator-min-microvolt = <1800000>; 111 regulator-max-microvolt = <1800000>; 112 }; 113 114 reg_3v3: regulator-3v3 { 115 compatible = "regulator-fixed"; 116 regulator-name = "3v3"; 117 regulator-min-microvolt = <3300000>; 118 regulator-max-microvolt = <3300000>; 119 }; 120 121 reg_otg_vbus: regulator-otg-vbus { 122 compatible = "regulator-fixed"; 123 regulator-name = "otg-vbus"; 124 regulator-min-microvolt = <5000000>; 125 regulator-max-microvolt = <5000000>; 126 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 127 enable-active-high; 128 }; 129 130 sound { 131 compatible = "simple-audio-card"; 132 simple-audio-card,name = "prti6q-sgtl5000"; 133 simple-audio-card,format = "i2s"; 134 simple-audio-card,widgets = 135 "Microphone", "Microphone Jack", 136 "Line", "Line In Jack", 137 "Headphone", "Headphone Jack", 138 "Speaker", "External Speaker"; 139 simple-audio-card,routing = 140 "MIC_IN", "Microphone Jack", 141 "LINE_IN", "Line In Jack", 142 "Headphone Jack", "HP_OUT", 143 "External Speaker", "LINE_OUT"; 144 145 simple-audio-card,cpu { 146 sound-dai = <&ssi1>; 147 system-clock-frequency = <0>; /* Do NOT call fsl_ssi_set_dai_sysclk! */ 148 }; 149 150 simple-audio-card,codec { 151 sound-dai = <&codec>; 152 bitclock-master; 153 frame-master; 154 }; 155 }; 156 157 thermal-zones { 158 chassis-thermal { 159 polling-delay = <20000>; 160 polling-delay-passive = <0>; 161 thermal-sensors = <&tsens0>; 162 }; 163 }; 164 }; 165 166 &audmux { 167 pinctrl-names = "default"; 168 pinctrl-0 = <&pinctrl_audmux>; 169 status = "okay"; 170 171 mux-ssi1 { 172 fsl,audmux-port = <0>; 173 fsl,port-config = < 174 IMX_AUDMUX_V2_PTCR_SYN 0 175 IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 176 IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 177 IMX_AUDMUX_V2_PTCR_TFSDIR 0 178 IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) 179 >; 180 }; 181 182 mux-pins3 { 183 fsl,audmux-port = <2>; 184 fsl,port-config = < 185 IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) 186 0 IMX_AUDMUX_V2_PDCR_TXRXEN 187 >; 188 }; 189 }; 190 191 &can1 { 192 pinctrl-names = "default"; 193 pinctrl-0 = <&pinctrl_can1>; 194 termination-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; 195 termination-ohms = <150>; 196 status = "okay"; 197 }; 198 199 &can2 { 200 pinctrl-names = "default"; 201 pinctrl-0 = <&pinctrl_can2>; 202 status = "okay"; 203 }; 204 205 &clks { 206 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>; 207 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; 208 }; 209 210 &ecspi1 { 211 cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; 212 pinctrl-names = "default"; 213 pinctrl-0 = <&pinctrl_ecspi1>; 214 status = "okay"; 215 216 flash@0 { 217 compatible = "jedec,spi-nor"; 218 reg = <0>; 219 spi-max-frequency = <20000000>; 220 }; 221 }; 222 223 &gpio2 { 224 gpio-line-names = 225 "YACO_WHEEL", "YACO_RADAR", "YACO_PTO", "", "", "", "", "", 226 "", "LED_PWM", "", "", "", 227 "", "", "", 228 "", "", "", "", "", "ISB_IN2", "ISB_nIN1", "ON_SWITCH", 229 "POWER_LED", "", "", "", "", "", "", ""; 230 }; 231 232 &gpio3 { 233 gpio-line-names = 234 "", "", "", "", "", "", "", "", 235 "", "", "", "", "", "", "", "", 236 "ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1", 237 "CPU_ON1_FB", "USB_OTG_OC", "USB_OTG_PWR", "YACO_IRQ", 238 "TSS_TXD", "TSS_RXD", "", "", "", "", "YACO_BOOT0", 239 "YACO_RESET"; 240 }; 241 242 &gpio7 { 243 gpio-line-names = 244 "EMMC_DAT5", "EMMC_DAT4", "EMMC_CMD", "EMMC_CLK", "EMMC_DAT0", 245 "EMMC_DAT1", "EMMC_DAT2", "EMMC_DAT3", 246 "EMMC_RST", "", "", "", "CAM_DETECT", "", "", "", 247 "", "EMMC_DAT7", "EMMC_DAT6", "", "", "", "", "", 248 "", "", "", "", "", "", "", ""; 249 }; 250 251 &i2c1 { 252 clock-frequency = <100000>; 253 pinctrl-names = "default"; 254 pinctrl-0 = <&pinctrl_i2c1>; 255 status = "okay"; 256 257 codec: audio-codec@a { 258 compatible = "fsl,sgtl5000"; 259 reg = <0xa>; 260 #sound-dai-cells = <0>; 261 clocks = <&clks 201>; 262 VDDA-supply = <®_3v3>; 263 VDDIO-supply = <®_3v3>; 264 VDDD-supply = <®_1v8>; 265 }; 266 267 video-decoder@5c { 268 compatible = "ti,tvp5150"; 269 reg = <0x5c>; 270 #address-cells = <1>; 271 #size-cells = <0>; 272 273 port@0 { 274 reg = <0>; 275 276 tvp5150_comp0_in: endpoint { 277 remote-endpoint = <&comp0_out>; 278 }; 279 }; 280 281 /* Output port 2 is video output pad */ 282 port@2 { 283 reg = <2>; 284 285 tvp5151_to_ipu1_csi0_mux: endpoint { 286 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; 287 }; 288 }; 289 }; 290 }; 291 292 &i2c3 { 293 clock-frequency = <100000>; 294 pinctrl-names = "default"; 295 pinctrl-0 = <&pinctrl_i2c3>; 296 status = "okay"; 297 298 adc@49 { 299 compatible = "ti,ads1015"; 300 reg = <0x49>; 301 #address-cells = <1>; 302 #size-cells = <0>; 303 304 channel@4 { 305 reg = <4>; 306 ti,gain = <3>; 307 ti,datarate = <3>; 308 }; 309 310 channel@5 { 311 reg = <5>; 312 ti,gain = <3>; 313 ti,datarate = <3>; 314 }; 315 316 channel@6 { 317 reg = <6>; 318 ti,gain = <3>; 319 ti,datarate = <3>; 320 }; 321 322 channel@7 { 323 reg = <7>; 324 ti,gain = <3>; 325 ti,datarate = <3>; 326 }; 327 }; 328 329 rtc@51 { 330 compatible = "nxp,pcf8563"; 331 reg = <0x51>; 332 }; 333 334 tsens0: temperature-sensor@70 { 335 compatible = "ti,tmp103"; 336 reg = <0x70>; 337 #thermal-sensor-cells = <0>; 338 }; 339 }; 340 341 &ipu1_csi0 { 342 pinctrl-names = "default"; 343 pinctrl-0 = <&pinctrl_ipu1_csi0>; 344 status = "okay"; 345 }; 346 347 &ipu1_csi0_mux_from_parallel_sensor { 348 remote-endpoint = <&tvp5151_to_ipu1_csi0_mux>; 349 }; 350 351 &ldb { 352 status = "okay"; 353 354 lvds-channel@0 { 355 status = "okay"; 356 357 port@4 { 358 reg = <4>; 359 360 lvds0_out: endpoint { 361 remote-endpoint = <&panel_in>; 362 }; 363 }; 364 }; 365 }; 366 367 &pwm1 { 368 pinctrl-names = "default"; 369 pinctrl-0 = <&pinctrl_pwm1>; 370 status = "okay"; 371 }; 372 373 &pwm3 { 374 pinctrl-names = "default"; 375 pinctrl-0 = <&pinctrl_pwm3>; 376 status = "okay"; 377 }; 378 379 &ssi1 { 380 #sound-dai-cells = <0>; 381 fsl,mode = "ac97-slave"; 382 status = "okay"; 383 }; 384 385 &uart1 { 386 pinctrl-names = "default"; 387 pinctrl-0 = <&pinctrl_uart1>; 388 status = "okay"; 389 }; 390 391 &uart3 { 392 pinctrl-names = "default"; 393 pinctrl-0 = <&pinctrl_uart3>; 394 status = "okay"; 395 }; 396 397 &uart4 { 398 pinctrl-names = "default"; 399 pinctrl-0 = <&pinctrl_uart4>; 400 status = "okay"; 401 }; 402 403 &uart5 { 404 pinctrl-names = "default"; 405 pinctrl-0 = <&pinctrl_uart5>; 406 status = "okay"; 407 }; 408 409 &usbh1 { 410 pinctrl-names = "default"; 411 phy_type = "utmi"; 412 dr_mode = "host"; 413 status = "okay"; 414 }; 415 416 &usbotg { 417 vbus-supply = <®_otg_vbus>; 418 pinctrl-names = "default"; 419 pinctrl-0 = <&pinctrl_usbotg>; 420 phy_type = "utmi"; 421 dr_mode = "host"; 422 disable-over-current; 423 status = "okay"; 424 }; 425 426 &usdhc1 { 427 pinctrl-names = "default"; 428 pinctrl-0 = <&pinctrl_usdhc1>; 429 cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 430 no-1-8-v; 431 disable-wp; 432 cap-sd-highspeed; 433 no-mmc; 434 no-sdio; 435 status = "okay"; 436 }; 437 438 &usdhc3 { 439 pinctrl-names = "default"; 440 pinctrl-0 = <&pinctrl_usdhc3>; 441 bus-width = <8>; 442 no-1-8-v; 443 non-removable; 444 no-sd; 445 no-sdio; 446 status = "okay"; 447 }; 448 449 &iomuxc { 450 pinctrl-names = "default"; 451 pinctrl-0 = <&pinctrl_hog>; 452 453 pinctrl_audmux: audmuxgrp { 454 fsl,pins = < 455 /* SGTL5000 sys_mclk */ 456 MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 457 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 458 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 459 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 460 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 461 >; 462 }; 463 464 pinctrl_backlight: backlightgrp { 465 fsl,pins = < 466 MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 467 >; 468 }; 469 470 pinctrl_can1: can1grp { 471 fsl,pins = < 472 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 473 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 474 /* CAN1_SR */ 475 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008 476 /* CAN1_TERM */ 477 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b088 478 >; 479 }; 480 481 pinctrl_can2: can2grp { 482 fsl,pins = < 483 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 484 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 485 /* CAN2_SR */ 486 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13008 487 >; 488 }; 489 490 pinctrl_counter0: counter0grp { 491 fsl,pins = < 492 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b000 493 >; 494 }; 495 496 pinctrl_counter1: counter1grp { 497 fsl,pins = < 498 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b000 499 >; 500 }; 501 502 pinctrl_counter2: counter2grp { 503 fsl,pins = < 504 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b000 505 >; 506 }; 507 508 pinctrl_ecspi1: ecspi1grp { 509 fsl,pins = < 510 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 511 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 512 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 513 /* CS */ 514 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 515 >; 516 }; 517 518 pinctrl_hog: hoggrp { 519 fsl,pins = < 520 /* ITU656_nRESET */ 521 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 522 /* CAM1_MIRROR */ 523 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x130b0 524 /* CAM2_MIRROR */ 525 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 526 /* CAM_nDETECT */ 527 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 528 /* ISB_IN1 */ 529 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 530 /* ISB_nIN2 */ 531 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 532 /* WARN_LIGHT */ 533 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x100b0 534 /* ON2_FB */ 535 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 536 /* YACO_nIRQ */ 537 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 538 /* YACO_BOOT0 */ 539 MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x130b0 540 /* YACO_nRESET */ 541 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 542 /* FORCE_ON1 */ 543 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 544 /* AUDIO_nRESET */ 545 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0 546 /* ITU656_nPDN */ 547 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 548 549 /* New in HW revision 1 */ 550 /* ON1_FB */ 551 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0 552 /* DIP1_FB */ 553 MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 554 >; 555 }; 556 557 pinctrl_i2c1: i2c1grp { 558 fsl,pins = < 559 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 560 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 561 >; 562 }; 563 564 pinctrl_i2c3: i2c3grp { 565 fsl,pins = < 566 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 567 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 568 >; 569 }; 570 571 pinctrl_ipu1_csi0: ipu1csi0grp { 572 fsl,pins = < 573 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 574 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 575 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 576 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 577 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 578 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 579 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 580 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 581 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 582 >; 583 }; 584 585 pinctrl_leds: ledsgrp { 586 fsl,pins = < 587 /* DEBUG0 */ 588 MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b0 589 /* DEBUG1 */ 590 MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0 591 /* POWER_LED */ 592 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0 593 /* ISB_LED */ 594 MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 595 >; 596 }; 597 598 pinctrl_pwm1: pwm1grp { 599 fsl,pins = < 600 MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 601 >; 602 }; 603 604 pinctrl_pwm3: pwm3grp { 605 fsl,pins = < 606 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0 607 >; 608 }; 609 610 /* YaCO AUX Uart */ 611 pinctrl_uart1: uart1grp { 612 fsl,pins = < 613 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 614 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 615 >; 616 }; 617 618 /* YaCO Touchscreen UART */ 619 pinctrl_uart3: uart3grp { 620 fsl,pins = < 621 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 622 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 623 >; 624 }; 625 626 pinctrl_uart4: uart4grp { 627 fsl,pins = < 628 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 629 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 630 >; 631 }; 632 633 pinctrl_uart5: uart5grp { 634 fsl,pins = < 635 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 636 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 637 >; 638 }; 639 640 pinctrl_usbotg: usbotggrp { 641 fsl,pins = < 642 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 643 /* power enable, high active */ 644 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 645 >; 646 }; 647 648 pinctrl_usdhc1: usdhc1grp { 649 fsl,pins = < 650 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 651 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 652 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 653 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 654 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 655 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 656 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 657 >; 658 }; 659 660 pinctrl_usdhc3: usdhc3grp { 661 fsl,pins = < 662 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 663 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 664 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 665 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 666 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 667 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 668 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 669 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 670 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 671 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 672 MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 673 >; 674 }; 675 };
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