imx6qdl-zii-rdu2.dtsi

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    1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
    2 /*
    3  * Copyright (C) 2016-2017 Zodiac Inflight Innovations
    4  */
    5 
    6 #include <dt-bindings/gpio/gpio.h>
    7 #include <dt-bindings/sound/fsl-imx-audmux.h>
    8 
    9 / {
   10         chosen {
   11                 stdout-path = &uart1;
   12         };
   13 
   14         aliases {
   15                 mdio-gpio0 = &mdio1;
   16                 rtc0 = &ds1341;
   17         };
   18 
   19         mdio1: mdio {
   20                 compatible = "virtual,mdio-gpio";
   21                 #address-cells = <1>;
   22                 #size-cells = <0>;
   23                 pinctrl-names = "default";
   24                 pinctrl-0 = <&pinctrl_mdio1>;
   25                 gpios = <&gpio6 5 GPIO_ACTIVE_HIGH
   26                          &gpio6 4 GPIO_ACTIVE_HIGH>;
   27 
   28                 phy: ethernet-phy@0 {
   29                         pinctrl-0 = <&pinctrl_rmii_phy_irq>;
   30                         pinctrl-names = "default";
   31                         reg = <0>;
   32                         interrupt-parent = <&gpio3>;
   33                         interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
   34                 };
   35         };
   36 
   37         reg_28p0v: regulator-28p0v {
   38                 compatible = "regulator-fixed";
   39                 regulator-name = "28V_IN";
   40                 regulator-min-microvolt = <28000000>;
   41                 regulator-max-microvolt = <28000000>;
   42                 regulator-always-on;
   43         };
   44 
   45         reg_12p0v: regulator-12p0v {
   46                 compatible = "regulator-fixed";
   47                 vin-supply = <&reg_28p0v>;
   48                 regulator-name = "12V_MAIN";
   49                 regulator-min-microvolt = <12000000>;
   50                 regulator-max-microvolt = <12000000>;
   51                 regulator-always-on;
   52         };
   53 
   54         reg_5p0v_main: regulator-5p0v-main {
   55                 compatible = "regulator-fixed";
   56                 vin-supply = <&reg_12p0v>;
   57                 regulator-name = "5V_MAIN";
   58                 regulator-min-microvolt = <5000000>;
   59                 regulator-max-microvolt = <5000000>;
   60                 regulator-always-on;
   61         };
   62 
   63         reg_3p3v_pmic: regulator-3p3v-pmic {
   64                 compatible = "regulator-fixed";
   65                 vin-supply = <&reg_12p0v>;
   66                 regulator-name = "PMIC_3V3";
   67                 regulator-min-microvolt = <3300000>;
   68                 regulator-max-microvolt = <3300000>;
   69                 regulator-always-on;
   70         };
   71 
   72         reg_3p3v: regulator-3p3v {
   73                 compatible = "regulator-fixed";
   74                 vin-supply = <&reg_3p3v_pmic>;
   75                 regulator-name = "GEN_3V3";
   76                 regulator-min-microvolt = <3300000>;
   77                 regulator-max-microvolt = <3300000>;
   78                 regulator-always-on;
   79         };
   80 
   81         reg_3p3v_sd: regulator-3p3v-sd {
   82                 compatible = "regulator-fixed";
   83                 pinctrl-names = "default";
   84                 pinctrl-0 = <&pinctrl_reg_3p3v_sd>;
   85                 vin-supply = <&reg_3p3v>;
   86                 regulator-name = "3V3_SD";
   87                 regulator-min-microvolt = <3300000>;
   88                 regulator-max-microvolt = <3300000>;
   89                 gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
   90                 startup-delay-us = <1000>;
   91                 enable-active-high;
   92                 regulator-always-on;
   93         };
   94 
   95         reg_3p3v_display: regulator-3p3v-display {
   96                 compatible = "regulator-fixed";
   97                 vin-supply = <&reg_12p0v>;
   98                 regulator-name = "3V3_DISPLAY";
   99                 regulator-min-microvolt = <3300000>;
  100                 regulator-max-microvolt = <3300000>;
  101                 regulator-always-on;
  102         };
  103 
  104         reg_3p3v_ssd: regulator-3p3v-ssd {
  105                 compatible = "regulator-fixed";
  106                 vin-supply = <&reg_12p0v>;
  107                 regulator-name = "3V3_SSD";
  108                 regulator-min-microvolt = <3300000>;
  109                 regulator-max-microvolt = <3300000>;
  110                 regulator-always-on;
  111         };
  112 
  113         sound1 {
  114                 compatible = "simple-audio-card";
  115                 simple-audio-card,name = "front";
  116                 simple-audio-card,format = "i2s";
  117                 simple-audio-card,bitclock-master = <&sound1_codec>;
  118                 simple-audio-card,frame-master = <&sound1_codec>;
  119                 simple-audio-card,widgets =
  120                         "Headphone", "Headphone Jack";
  121                 simple-audio-card,routing =
  122                         "Headphone Jack", "HPA1 HPLEFT",
  123                         "Headphone Jack", "HPA1 HPRIGHT",
  124                         "HPA1 LEFTIN", "HPL",
  125                         "HPA1 RIGHTIN", "HPR";
  126                 simple-audio-card,aux-devs = <&hpa1>;
  127 
  128                 sound1_cpu: simple-audio-card,cpu {
  129                         sound-dai = <&ssi2>;
  130                 };
  131 
  132                 sound1_codec: simple-audio-card,codec {
  133                         sound-dai = <&codec1>;
  134                         clocks = <&cs2000>;
  135                 };
  136         };
  137 
  138         sound2 {
  139                 compatible = "simple-audio-card";
  140                 simple-audio-card,name = "periph";
  141                 simple-audio-card,format = "i2s";
  142                 simple-audio-card,bitclock-master = <&sound2_codec>;
  143                 simple-audio-card,frame-master = <&sound2_codec>;
  144                 simple-audio-card,widgets =
  145                         "Headphone", "Headphone Jack";
  146                 simple-audio-card,routing =
  147                         "Headphone Jack", "HPA1 HPLEFT",
  148                         "Headphone Jack", "HPA1 HPRIGHT",
  149                         "HPA1 LEFTIN", "HPL",
  150                         "HPA1 RIGHTIN", "HPR";
  151                 simple-audio-card,aux-devs = <&hpa2>;
  152 
  153                 sound2_cpu: simple-audio-card,cpu {
  154                         sound-dai = <&ssi1>;
  155                 };
  156 
  157                 sound2_codec: simple-audio-card,codec {
  158                         sound-dai = <&codec2>;
  159                         clocks = <&cs2000>;
  160                 };
  161         };
  162 
  163         panel {
  164                 power-supply = <&reg_3p3v_display>;
  165                 backlight = <&sp_backlight>;
  166                 status = "disabled";
  167 
  168                 port {
  169                         panel_in: endpoint {
  170                                 remote-endpoint = <&lvds0_out>;
  171                         };
  172                 };
  173         };
  174 
  175         disp0: disp0 {
  176                 #address-cells = <1>;
  177                 #size-cells = <0>;
  178                 compatible = "fsl,imx-parallel-display";
  179                 pinctrl-names = "default";
  180                 pinctrl-0 = <&pinctrl_disp0>;
  181                 status = "disabled";
  182 
  183                 port@0 {
  184                         reg = <0>;
  185 
  186                         disp0_in_0: endpoint {
  187                                 remote-endpoint = <&ipu1_di0_disp0>;
  188                         };
  189                 };
  190 
  191                 port@1 {
  192                         reg = <1>;
  193 
  194                         disp0_out: endpoint {
  195                                 remote-endpoint = <&tc358767_in>;
  196                         };
  197                 };
  198         };
  199 
  200         cs2000_ref: cs2000-ref {
  201                 compatible = "fixed-clock";
  202                 #clock-cells = <0>;
  203                 clock-frequency = <24576000>;
  204         };
  205 
  206         cs2000_in_dummy: cs2000-in-dummy {
  207                 compatible = "fixed-clock";
  208                 #clock-cells = <0>;
  209                 clock-frequency = <0>;
  210         };
  211 
  212         edp_refclk: edp-refclk {
  213                 compatible = "fixed-clock";
  214                 #clock-cells = <0>;
  215                 clock-frequency = <19200000>;
  216         };
  217 };
  218 
  219 &clks {
  220         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
  221                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
  222         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
  223                                  <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
  224 };
  225 
  226 &cpu0 {
  227         fsl,soc-operating-points = <
  228                 /* ARM kHz  SOC-PU uV */
  229                 1200000 1300000
  230                 996000  1275000
  231                 852000  1275000
  232                 792000  1200000
  233                 396000  1200000
  234         >;
  235 };
  236 
  237 &reg_arm {
  238         vin-supply = <&sw1a_reg>;
  239 };
  240 
  241 &reg_pu {
  242         vin-supply = <&sw1c_reg>;
  243 };
  244 
  245 &reg_soc {
  246         vin-supply = <&sw1c_reg>;
  247 };
  248 
  249 &ldb {
  250         lvds-channel@0 {
  251                 port@4 {
  252                         reg = <4>;
  253 
  254                         lvds0_out: endpoint {
  255                                 remote-endpoint = <&panel_in>;
  256                         };
  257                 };
  258         };
  259 };
  260 
  261 &uart1 {
  262         pinctrl-names = "default";
  263         pinctrl-0 = <&pinctrl_uart1>;
  264         status = "okay";
  265 };
  266 
  267 &uart3 {
  268         pinctrl-names = "default";
  269         pinctrl-0 = <&pinctrl_uart3>;
  270         uart-has-rtscts;
  271         linux,rs485-enabled-at-boot-time;
  272         status = "okay";
  273 };
  274 
  275 &uart4 {
  276         pinctrl-names = "default";
  277         pinctrl-0 = <&pinctrl_uart4>;
  278         status = "okay";
  279 
  280         rave-sp {
  281                 compatible = "zii,rave-sp-rdu2";
  282                 current-speed = <1000000>;
  283                 #address-cells = <1>;
  284                 #size-cells = <1>;
  285 
  286                 watchdog {
  287                         compatible = "zii,rave-sp-watchdog";
  288                 };
  289 
  290                 sp_backlight: backlight {
  291                         compatible = "zii,rave-sp-backlight";
  292                 };
  293 
  294                 pwrbutton {
  295                         compatible = "zii,rave-sp-pwrbutton";
  296                 };
  297 
  298                 eeprom@a3 {
  299                         compatible = "zii,rave-sp-eeprom";
  300                         reg = <0xa3 0x4000>;
  301                         #address-cells = <1>;
  302                         #size-cells = <1>;
  303                         zii,eeprom-name = "dds-eeprom";
  304                 };
  305 
  306                 eeprom@a4 {
  307                         compatible = "zii,rave-sp-eeprom";
  308                         reg = <0xa4 0x4000>;
  309                         #address-cells = <1>;
  310                         #size-cells = <1>;
  311                         zii,eeprom-name = "main-eeprom";
  312                 };
  313         };
  314 };
  315 
  316 &ecspi1 {
  317         pinctrl-names = "default";
  318         pinctrl-0 = <&pinctrl_ecspi1>;
  319         cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
  320         status = "okay";
  321 
  322         flash@0 {
  323                 compatible = "st,m25p128", "jedec,spi-nor";
  324                 spi-max-frequency = <20000000>;
  325                 reg = <0>;
  326         };
  327 };
  328 
  329 &gpio3 {
  330         pinctrl-names = "default";
  331         pinctrl-0 = <&pinctrl_gpio3_hog>;
  332 
  333         usb-emulation-hog {
  334                 gpio-hog;
  335                 gpios = <19 GPIO_ACTIVE_HIGH>;
  336                 output-low;
  337                 line-name = "usb-emulation";
  338         };
  339 
  340         usb-mode1-hog {
  341                 gpio-hog;
  342                 gpios = <20 GPIO_ACTIVE_HIGH>;
  343                 output-high;
  344                 line-name = "usb-mode1";
  345         };
  346 
  347         usb-pwr-hog {
  348                 gpio-hog;
  349                 gpios = <22 GPIO_ACTIVE_LOW>;
  350                 output-high;
  351                 line-name = "usb-pwr-ctrl-en-n";
  352         };
  353 
  354         usb-mode2-hog {
  355                 gpio-hog;
  356                 gpios = <23 GPIO_ACTIVE_HIGH>;
  357                 output-high;
  358                 line-name = "usb-mode2";
  359         };
  360 };
  361 
  362 &i2c1 {
  363         pinctrl-names = "default";
  364         pinctrl-0 = <&pinctrl_i2c1>;
  365         clock-frequency = <100000>;
  366         status = "okay";
  367 
  368         codec2: codec@18 {
  369                 compatible = "ti,tlv320dac3100";
  370                 pinctrl-names = "default";
  371                 pinctrl-0 = <&pinctrl_codec2>;
  372                 reg = <0x18>;
  373                 #sound-dai-cells = <0>;
  374                 HPVDD-supply = <&reg_3p3v>;
  375                 SPRVDD-supply = <&reg_3p3v>;
  376                 SPLVDD-supply = <&reg_3p3v>;
  377                 AVDD-supply = <&reg_3p3v>;
  378                 IOVDD-supply = <&reg_3p3v>;
  379                 DVDD-supply = <&vgen4_reg>;
  380                 reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
  381         };
  382 
  383         accel@1c {
  384                 pinctrl-names = "default";
  385                 pinctrl-0 = <&pinctrl_accel>;
  386                 compatible = "fsl,mma8451";
  387                 reg = <0x1c>;
  388                 interrupt-parent = <&gpio1>;
  389                 interrupt-names = "INT2";
  390                 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
  391                 vdd-supply = <&reg_3p3v>;
  392                 vddio-supply = <&reg_3p3v>;
  393         };
  394 
  395         hpa2: amp@60 {
  396                 compatible = "ti,tpa6130a2";
  397                 pinctrl-names = "default";
  398                 pinctrl-0 = <&pinctrl_tpa2>;
  399                 reg = <0x60>;
  400                 power-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  401                 Vdd-supply = <&reg_5p0v_main>;
  402                 sound-name-prefix = "HPA1";
  403         };
  404 
  405         edp-bridge@68 {
  406                 compatible = "toshiba,tc358767";
  407                 pinctrl-names = "default";
  408                 pinctrl-0 = <&pinctrl_tc358767>;
  409                 reg = <0x68>;
  410                 shutdown-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  411                 clock-names = "ref";
  412                 clocks = <&edp_refclk>;
  413                 status = "disabled";
  414 
  415                 ports {
  416                         #address-cells = <1>;
  417                         #size-cells = <0>;
  418 
  419                         port@1 {
  420                                 reg = <1>;
  421 
  422                                 tc358767_in: endpoint {
  423                                         remote-endpoint = <&disp0_out>;
  424                                 };
  425                         };
  426                 };
  427         };
  428 };
  429 
  430 &i2c2 {
  431         pinctrl-names = "default";
  432         pinctrl-0 = <&pinctrl_i2c2>;
  433         clock-frequency = <100000>;
  434         status = "okay";
  435 
  436         pmic@8 {
  437                 compatible = "fsl,pfuze100";
  438                 pinctrl-names = "default";
  439                 pinctrl-0 = <&pinctrl_pfuze100_irq>;
  440                 reg = <0x08>;
  441                 interrupt-parent = <&gpio7>;
  442                 interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
  443 
  444                 regulators {
  445                         sw1a_reg: sw1ab {
  446                                 regulator-min-microvolt = <300000>;
  447                                 regulator-max-microvolt = <1875000>;
  448                                 regulator-boot-on;
  449                                 regulator-always-on;
  450                                 regulator-ramp-delay = <6250>;
  451                         };
  452 
  453                         sw1c_reg: sw1c {
  454                                 regulator-min-microvolt = <300000>;
  455                                 regulator-max-microvolt = <1875000>;
  456                                 regulator-boot-on;
  457                                 regulator-always-on;
  458                                 regulator-ramp-delay = <6250>;
  459                         };
  460 
  461                         sw2_reg: sw2 {
  462                                 regulator-min-microvolt = <800000>;
  463                                 regulator-max-microvolt = <3000000>;
  464                                 regulator-boot-on;
  465                                 regulator-always-on;
  466                         };
  467 
  468                         sw3a_reg: sw3a {
  469                                 regulator-min-microvolt = <400000>;
  470                                 regulator-max-microvolt = <1500000>;
  471                                 regulator-boot-on;
  472                                 regulator-always-on;
  473                         };
  474 
  475                         sw3b_reg: sw3b {
  476                                 regulator-min-microvolt = <400000>;
  477                                 regulator-max-microvolt = <1500000>;
  478                                 regulator-boot-on;
  479                                 regulator-always-on;
  480                         };
  481 
  482                         sw4_reg: sw4 {
  483                                 regulator-min-microvolt = <800000>;
  484                                 regulator-max-microvolt = <1800000>;
  485                                 regulator-boot-on;
  486                                 regulator-always-on;
  487                         };
  488 
  489                         snvs_reg: vsnvs {
  490                                 regulator-min-microvolt = <1000000>;
  491                                 regulator-max-microvolt = <3000000>;
  492                                 regulator-boot-on;
  493                                 regulator-always-on;
  494                         };
  495 
  496                         vref_reg: vrefddr {
  497                                 regulator-boot-on;
  498                                 regulator-always-on;
  499                         };
  500 
  501                         vgen2_reg: vgen2 {
  502                                 regulator-min-microvolt = <1000000>;
  503                                 regulator-max-microvolt = <1500000>;
  504                                 regulator-always-on;
  505                         };
  506 
  507                         vgen4_reg: vgen4 {
  508                                 regulator-min-microvolt = <1200000>;
  509                                 regulator-max-microvolt = <1800000>;
  510                                 regulator-always-on;
  511                         };
  512 
  513                         vgen5_reg: vgen5 {
  514                                 regulator-min-microvolt = <1800000>;
  515                                 regulator-max-microvolt = <2500000>;
  516                                 regulator-always-on;
  517                         };
  518 
  519                         vgen6_reg: vgen6 {
  520                                 regulator-min-microvolt = <1800000>;
  521                                 regulator-max-microvolt = <2800000>;
  522                                 regulator-always-on;
  523                         };
  524                 };
  525         };
  526 
  527         watchdog@38 {
  528                 compatible = "zii,rave-wdt";
  529                 reg = <0x38>;
  530         };
  531 
  532         temp-sense@48 {
  533                 compatible = "national,lm75";
  534                 reg = <0x48>;
  535         };
  536 
  537         cs2000: clkgen@4e {
  538                 compatible = "cirrus,cs2000-cp";
  539                 reg = <0x4e>;
  540                 #clock-cells = <0>;
  541                 clock-names = "clk_in", "ref_clk";
  542                 clocks = <&cs2000_in_dummy>, <&cs2000_ref>;
  543                 assigned-clocks = <&cs2000>;
  544                 assigned-clock-rates = <24000000>;
  545         };
  546 
  547         eeprom@54 {
  548                 compatible = "atmel,24c128";
  549                 reg = <0x54>;
  550         };
  551 
  552         ds1341: rtc@68 {
  553                 compatible = "dallas,ds1341";
  554                 reg = <0x68>;
  555         };
  556 };
  557 
  558 &i2c3 {
  559         pinctrl-names = "default";
  560         pinctrl-0 = <&pinctrl_i2c3>;
  561         clock-frequency = <400000>;
  562         status = "okay";
  563 
  564         codec1: codec@18 {
  565                 compatible = "ti,tlv320dac3100";
  566                 pinctrl-names = "default";
  567                 pinctrl-0 = <&pinctrl_codec1>;
  568                 reg = <0x18>;
  569                 #sound-dai-cells = <0>;
  570                 HPVDD-supply = <&reg_3p3v>;
  571                 SPRVDD-supply = <&reg_3p3v>;
  572                 SPLVDD-supply = <&reg_3p3v>;
  573                 AVDD-supply = <&reg_3p3v>;
  574                 IOVDD-supply = <&reg_3p3v>;
  575                 DVDD-supply = <&vgen4_reg>;
  576                 reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
  577         };
  578 
  579         touchscreen@20 {
  580                 compatible = "syna,rmi4-i2c";
  581                 pinctrl-names = "default";
  582                 pinctrl-0 = <&pinctrl_ts>;
  583                 reg = <0x20>;
  584                 interrupt-parent = <&gpio1>;
  585                 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
  586                 vdd-supply = <&reg_5p0v_main>;
  587                 vio-supply = <&reg_3p3v>;
  588 
  589                 #address-cells = <1>;
  590                 #size-cells = <0>;
  591 
  592                 rmi4-f01@1 {
  593                         reg = <0x1>;
  594                         syna,nosleep-mode = <2>;
  595                 };
  596 
  597                 rmi4-f11@11 {
  598                         reg = <0x11>;
  599                         touchscreen-inverted-x;
  600                         touchscreen-swapped-x-y;
  601                         syna,sensor-type = <1>;
  602                         syna,delta-x-threshold = <5>;
  603                         syna,delta-y-threshold = <10>;
  604                 };
  605 
  606                 rmi4-f12@12 {
  607                         reg = <0x12>;
  608                         touchscreen-inverted-x;
  609                         touchscreen-swapped-x-y;
  610                         syna,sensor-type = <1>;
  611                 };
  612         };
  613 
  614         touchscreen@2a {
  615                 compatible = "eeti,exc3000";
  616                 pinctrl-names = "default";
  617                 pinctrl-0 = <&pinctrl_ts>;
  618                 reg = <0x2a>;
  619                 interrupt-parent = <&gpio1>;
  620                 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
  621                 touchscreen-inverted-x;
  622                 touchscreen-swapped-x-y;
  623                 status = "disabled";
  624         };
  625 
  626         reg_5p0v_user_usb: charger@32 {
  627                 compatible = "microchip,ucs1002";
  628                 pinctrl-names = "default";
  629                 pinctrl-0 = <&pinctrl_ucs1002_pins>;
  630                 reg = <0x32>;
  631                 interrupts-extended = <&gpio5 2 IRQ_TYPE_EDGE_BOTH>,
  632                                       <&gpio3 21 IRQ_TYPE_EDGE_FALLING>;
  633                 interrupt-names = "a_det", "alert";
  634         };
  635 
  636         hpa1: amp@60 {
  637                 compatible = "ti,tpa6130a2";
  638                 pinctrl-names = "default";
  639                 pinctrl-0 = <&pinctrl_tpa1>;
  640                 reg = <0x60>;
  641                 power-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
  642                 Vdd-supply = <&reg_5p0v_main>;
  643                 sound-name-prefix = "HPA1";
  644         };
  645 };
  646 
  647 &ipu1_di0_disp0 {
  648         remote-endpoint = <&disp0_in_0>;
  649 };
  650 
  651 &pcie {
  652         pinctrl-names = "default";
  653         pinctrl-0 = <&pinctrl_pcie>;
  654         reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
  655         status = "okay";
  656 
  657         host@0 {
  658                 reg = <0 0 0 0 0>;
  659 
  660                 #address-cells = <3>;
  661                 #size-cells = <2>;
  662 
  663                 i210: i210@0 {
  664                         reg = <0 0 0 0 0>;
  665                 };
  666         };
  667 };
  668 
  669 &usdhc2 {
  670         pinctrl-names = "default";
  671         pinctrl-0 = <&pinctrl_usdhc2>;
  672         bus-width = <4>;
  673         cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
  674         disable-wp;
  675         vmmc-supply = <&reg_3p3v_sd>;
  676         vqmmc-supply = <&reg_3p3v>;
  677         no-1-8-v;
  678         no-sdio;
  679         status = "okay";
  680 };
  681 
  682 &usdhc3 {
  683         pinctrl-names = "default";
  684         pinctrl-0 = <&pinctrl_usdhc3>;
  685         bus-width = <4>;
  686         cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
  687         disable-wp;
  688         vmmc-supply = <&reg_3p3v_sd>;
  689         vqmmc-supply = <&reg_3p3v>;
  690         no-1-8-v;
  691         no-sdio;
  692         status = "okay";
  693 };
  694 
  695 &usdhc4 {
  696         pinctrl-names = "default";
  697         pinctrl-0 = <&pinctrl_usdhc4>;
  698         bus-width = <8>;
  699         vmmc-supply = <&reg_3p3v>;
  700         vqmmc-supply = <&reg_3p3v>;
  701         no-1-8-v;
  702         non-removable;
  703         no-sdio;
  704         no-sd;
  705         status = "okay";
  706 };
  707 
  708 &sata {
  709         target-supply = <&reg_3p3v_ssd>;
  710         status = "okay";
  711 };
  712 
  713 &fec {
  714         pinctrl-names = "default";
  715         pinctrl-0 = <&pinctrl_enet>;
  716         phy-mode = "rmii";
  717         phy-handle = <&phy>;
  718         phy-reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
  719         phy-reset-duration = <100>;
  720         phy-supply = <&reg_3p3v>;
  721         status = "okay";
  722 
  723         mdio {
  724                 #address-cells = <1>;
  725                 #size-cells = <0>;
  726                 clock-frequency = <12500000>;
  727                 suppress-preamble;
  728                 status = "okay";
  729 
  730                 switch: switch@0 {
  731                         compatible = "marvell,mv88e6085";
  732                         pinctrl-0 = <&pinctrl_switch_irq>;
  733                         pinctrl-names = "default";
  734                         reg = <0>;
  735                         dsa,member = <0 0>;
  736                         eeprom-length = <512>;
  737                         interrupt-parent = <&gpio6>;
  738                         interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
  739                         interrupt-controller;
  740                         #interrupt-cells = <2>;
  741 
  742                         ports {
  743                                 #address-cells = <1>;
  744                                 #size-cells = <0>;
  745 
  746                                 port@0 {
  747                                         reg = <0>;
  748                                         label = "gigabit_proc";
  749                                         phy-handle = <&switchphy0>;
  750                                 };
  751 
  752                                 port@1 {
  753                                         reg = <1>;
  754                                         label = "netaux";
  755                                         phy-handle = <&switchphy1>;
  756                                 };
  757 
  758                                 port@2 {
  759                                         reg = <2>;
  760                                         label = "cpu";
  761                                         ethernet = <&fec>;
  762 
  763                                         fixed-link {
  764                                                 speed = <100>;
  765                                                 full-duplex;
  766                                         };
  767                                 };
  768 
  769                                 port@3 {
  770                                         reg = <3>;
  771                                         label = "netright";
  772                                         phy-handle = <&switchphy3>;
  773                                 };
  774 
  775                                 port@4 {
  776                                         reg = <4>;
  777                                         label = "netleft";
  778                                         phy-handle = <&switchphy4>;
  779                                 };
  780                         };
  781 
  782                         mdio {
  783                                 #address-cells = <1>;
  784                                 #size-cells = <0>;
  785 
  786                                 switchphy0: switchphy@0 {
  787                                         reg = <0>;
  788                                         interrupt-parent = <&switch>;
  789                                         interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
  790                                 };
  791 
  792                                 switchphy1: switchphy@1 {
  793                                         reg = <1>;
  794                                         interrupt-parent = <&switch>;
  795                                         interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
  796                                 };
  797 
  798                                 switchphy2: switchphy@2 {
  799                                         reg = <2>;
  800                                         interrupt-parent = <&switch>;
  801                                         interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
  802                                 };
  803 
  804                                 switchphy3: switchphy@3 {
  805                                         reg = <3>;
  806                                         interrupt-parent = <&switch>;
  807                                         interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
  808                                 };
  809 
  810                                 switchphy4: switchphy@4 {
  811                                         reg = <4>;
  812                                         interrupt-parent = <&switch>;
  813                                         interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
  814                                 };
  815                         };
  816                 };
  817         };
  818 };
  819 
  820 &usbh1 {
  821         vbus-supply = <&reg_5p0v_main>;
  822         disable-over-current;
  823         maximum-speed = "full-speed";
  824         status = "okay";
  825 };
  826 
  827 &usbotg {
  828         vbus-supply = <&reg_5p0v_user_usb>;
  829         disable-over-current;
  830         dr_mode = "host";
  831         status = "okay";
  832 };
  833 
  834 &snvs_rtc {
  835         status = "disabled";
  836 };
  837 
  838 &ssi1 {
  839         status = "okay";
  840 };
  841 
  842 &ssi2 {
  843         status = "okay";
  844 };
  845 
  846 &audmux {
  847         pinctrl-names = "default";
  848         pinctrl-0 = <&pinctrl_audmux>;
  849         status = "okay";
  850 
  851         ssi1 {
  852                 fsl,audmux-port = <0>;
  853                 fsl,port-config = <
  854                         (IMX_AUDMUX_V2_PTCR_SYN |
  855                          IMX_AUDMUX_V2_PTCR_TFSEL(2) |
  856                          IMX_AUDMUX_V2_PTCR_TCSEL(2) |
  857                          IMX_AUDMUX_V2_PTCR_TFSDIR |
  858                          IMX_AUDMUX_V2_PTCR_TCLKDIR)
  859                         IMX_AUDMUX_V2_PDCR_RXDSEL(2)
  860                 >;
  861         };
  862 
  863         aud3 {
  864                 fsl,audmux-port = <2>;
  865                 fsl,port-config = <
  866                         IMX_AUDMUX_V2_PTCR_SYN
  867                         IMX_AUDMUX_V2_PDCR_RXDSEL(0)
  868                 >;
  869         };
  870 
  871         ssi2 {
  872                 fsl,audmux-port = <1>;
  873                 fsl,port-config = <
  874                         (IMX_AUDMUX_V2_PTCR_SYN |
  875                          IMX_AUDMUX_V2_PTCR_TFSEL(4) |
  876                          IMX_AUDMUX_V2_PTCR_TCSEL(4) |
  877                          IMX_AUDMUX_V2_PTCR_TFSDIR |
  878                          IMX_AUDMUX_V2_PTCR_TCLKDIR)
  879                         IMX_AUDMUX_V2_PDCR_RXDSEL(4)
  880                 >;
  881         };
  882 
  883         aud5 {
  884                 fsl,audmux-port = <4>;
  885                 fsl,port-config = <
  886                         IMX_AUDMUX_V2_PTCR_SYN
  887                         IMX_AUDMUX_V2_PDCR_RXDSEL(1)
  888                 >;
  889         };
  890 };
  891 
  892 &iomuxc {
  893         pinctrl_accel: accelgrp {
  894                 fsl,pins = <
  895                         MX6QDL_PAD_SD1_CLK__GPIO1_IO20          0x4001b000
  896                 >;
  897         };
  898 
  899         pinctrl_audmux: audmuxgrp {
  900                 fsl,pins = <
  901                         MX6QDL_PAD_KEY_COL0__AUD5_TXC           0x130b0
  902                         MX6QDL_PAD_KEY_ROW0__AUD5_TXD           0x130b0
  903                         MX6QDL_PAD_KEY_COL1__AUD5_TXFS          0x130b0
  904                         MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
  905                         MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x130b0
  906                         MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
  907                 >;
  908         };
  909 
  910         pinctrl_codec1: dac1grp {
  911                 fsl,pins = <
  912                         MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x40000038
  913                 >;
  914         };
  915 
  916         pinctrl_codec2: dac2grp {
  917                 fsl,pins = <
  918                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x40000038
  919                 >;
  920         };
  921 
  922         pinctrl_disp0: disp0grp {
  923                 fsl,pins = <
  924                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f9
  925                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x100f9
  926                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x100f9
  927                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x100f9
  928                         MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x100f9
  929                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x100f9
  930                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x100f9
  931                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x100f9
  932                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x100f9
  933                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x100f9
  934                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x100f9
  935                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x100f9
  936                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x100f9
  937                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x100f9
  938                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x100f9
  939                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x100f9
  940                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x100f9
  941                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x100f9
  942                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x100f9
  943                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x100f9
  944                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x100f9
  945                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x100f9
  946                         MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x100f9
  947                         MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x100f9
  948                         MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x100f9
  949                         MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x100f9
  950                         MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x100f9
  951                         MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x100f9
  952                 >;
  953         };
  954 
  955         pinctrl_ecspi1: ecspi1grp {
  956                 fsl,pins = <
  957                         MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
  958                         MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
  959                         MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
  960                         MX6QDL_PAD_EIM_EB2__GPIO2_IO30          0x1b0b1
  961                 >;
  962         };
  963 
  964         pinctrl_enet: enetgrp {
  965                 fsl,pins = <
  966                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x000b1
  967                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x100b1
  968                         MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x100f5
  969                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x100f5
  970                         MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x100c0
  971                         MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x100c0
  972                         MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x100f5
  973                         MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x100f5
  974                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x40010040
  975                         MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x100b0
  976                         MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23     0x1b0b0
  977                 >;
  978         };
  979 
  980         pinctrl_gpio3_hog: gpio3hoggrp {
  981                 fsl,pins = <
  982                         MX6QDL_PAD_EIM_D19__GPIO3_IO19          0x1b0b0
  983                         MX6QDL_PAD_EIM_D20__GPIO3_IO20          0x1b0b0
  984                         MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0
  985                         MX6QDL_PAD_EIM_D23__GPIO3_IO23          0x1b0b0
  986                 >;
  987         };
  988 
  989         pinctrl_i2c1: i2c1grp {
  990                 fsl,pins = <
  991                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b811
  992                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b811
  993                 >;
  994         };
  995 
  996         pinctrl_i2c2: i2c2grp {
  997                 fsl,pins = <
  998                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b811
  999                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b811
 1000                 >;
 1001         };
 1002 
 1003         pinctrl_i2c3: i2c3grp {
 1004                 fsl,pins = <
 1005                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b811
 1006                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b811
 1007                 >;
 1008         };
 1009 
 1010         pinctrl_mdio1: bitbangmdiogrp {
 1011                 fsl,pins = <
 1012                         /* Bitbang MDIO for DEB Switch */
 1013                         MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05       0x4001b030
 1014                         MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04       0x40018830
 1015                 >;
 1016         };
 1017 
 1018         pinctrl_pcie: pciegrp {
 1019                 fsl,pins = <
 1020                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x10038
 1021                 >;
 1022         };
 1023 
 1024         pinctrl_pfuze100_irq: pfuze100grp {
 1025                 fsl,pins = <
 1026                         MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x40010000
 1027                 >;
 1028         };
 1029 
 1030         pinctrl_reg_3p3v_sd: mmcsupply1grp {
 1031                 fsl,pins = <
 1032                         MX6QDL_PAD_SD3_RST__GPIO7_IO08          0x858
 1033                 >;
 1034         };
 1035 
 1036         pinctrl_rmii_phy_irq: phygrp {
 1037                 fsl,pins = <
 1038                         MX6QDL_PAD_EIM_D30__GPIO3_IO30          0x40010000
 1039                 >;
 1040         };
 1041 
 1042         pinctrl_switch_irq: switchgrp {
 1043                 fsl,pins = <
 1044                         MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03       0x4001b000
 1045                 >;
 1046         };
 1047 
 1048         pinctrl_tc358767: tc358767grp {
 1049                 fsl,pins = <
 1050                         MX6QDL_PAD_GPIO_9__GPIO1_IO09           0x10
 1051                 >;
 1052         };
 1053 
 1054         pinctrl_tpa1: tpa6130-1grp {
 1055                 fsl,pins = <
 1056                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x40000038
 1057                 >;
 1058         };
 1059 
 1060         pinctrl_tpa2: tpa6130-2grp {
 1061                 fsl,pins = <
 1062                         MX6QDL_PAD_GPIO_5__GPIO1_IO05           0x40000038
 1063                 >;
 1064         };
 1065 
 1066         pinctrl_ts: tsgrp {
 1067                 fsl,pins = <
 1068                         MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x1b0b0
 1069                         MX6QDL_PAD_GPIO_7__GPIO1_IO07           0x1b0b0
 1070                 >;
 1071         };
 1072 
 1073         pinctrl_uart1: uart1grp {
 1074                 fsl,pins = <
 1075                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 1076                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 1077                 >;
 1078         };
 1079 
 1080         pinctrl_uart3: uart3grp {
 1081                 fsl,pins = <
 1082                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 1083                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 1084                         MX6QDL_PAD_EIM_D31__UART3_RTS_B         0x1b0b1
 1085                 >;
 1086         };
 1087 
 1088         pinctrl_uart4: uart4grp {
 1089                 fsl,pins = <
 1090                         MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
 1091                         MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
 1092                 >;
 1093         };
 1094 
 1095         pinctrl_ucs1002_pins: ucs1002grp {
 1096                 fsl,pins = <
 1097                         MX6QDL_PAD_EIM_A25__GPIO5_IO02          0x1b0b0
 1098                         MX6QDL_PAD_EIM_D21__GPIO3_IO21          0x1b0b0
 1099                 >;
 1100         };
 1101 
 1102         pinctrl_usdhc2: usdhc2grp {
 1103                 fsl,pins = <
 1104                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x10059
 1105                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10069
 1106                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 1107                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 1108                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 1109                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 1110                         MX6QDL_PAD_NANDF_D2__GPIO2_IO02         0x40010040
 1111                 >;
 1112         };
 1113 
 1114         pinctrl_usdhc3: usdhc3grp {
 1115                 fsl,pins = <
 1116                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x10059
 1117                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10069
 1118                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 1119                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 1120                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 1121                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 1122                         MX6QDL_PAD_NANDF_D0__GPIO2_IO00         0x40010040
 1123 
 1124                 >;
 1125         };
 1126 
 1127         pinctrl_usdhc4: usdhc4grp {
 1128                 fsl,pins = <
 1129                         MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
 1130                         MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
 1131                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
 1132                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
 1133                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
 1134                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
 1135                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
 1136                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
 1137                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
 1138                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
 1139                         MX6QDL_PAD_NANDF_ALE__SD4_RESET         0x1b0b1
 1140                 >;
 1141         };
 1142 };
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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm/imx6qdl-zii-rdu2.dtsi

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/imx6qdl-zii-rdu2.dtsi
