Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/imx6sl-tolino-shine3.dts
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1 // SPDX-License-Identifier: (GPL-2.0) 2 /* 3 * Device tree for the Tolino Shine 3 ebook reader 4 * 5 * Name on mainboard is: 37NB-E60K00+4A4 6 * Serials start with: E60K02 (a number also seen in 7 * vendor kernel sources) 8 * 9 * This mainboard seems to be equipped with different SoCs. 10 * In the Toline Shine 3 ebook reader it is a i.MX6SL 11 * 12 * Copyright 2019 Andreas Kemnade 13 * based on works 14 * Copyright 2016 Freescale Semiconductor, Inc. 15 */ 16 17 /dts-v1/; 18 19 #include <dt-bindings/input/input.h> 20 #include <dt-bindings/gpio/gpio.h> 21 #include "imx6sl.dtsi" 22 #include "e60k02.dtsi" 23 24 / { 25 model = "Tolino Shine 3"; 26 compatible = "kobo,tolino-shine3", "fsl,imx6sl"; 27 }; 28 29 &gpio_keys { 30 pinctrl-names = "default"; 31 pinctrl-0 = <&pinctrl_gpio_keys>; 32 }; 33 34 &i2c1 { 35 pinctrl-names = "default","sleep"; 36 pinctrl-0 = <&pinctrl_i2c1>; 37 pinctrl-1 = <&pinctrl_i2c1_sleep>; 38 }; 39 40 &i2c2 { 41 pinctrl-names = "default","sleep"; 42 pinctrl-0 = <&pinctrl_i2c2>; 43 pinctrl-1 = <&pinctrl_i2c2_sleep>; 44 }; 45 46 &i2c3 { 47 pinctrl-names = "default"; 48 pinctrl-0 = <&pinctrl_i2c3>; 49 }; 50 51 &iomuxc { 52 pinctrl-names = "default"; 53 pinctrl-0 = <&pinctrl_hog>; 54 55 pinctrl_gpio_keys: gpio-keysgrp { 56 fsl,pins = < 57 MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059 /* PWR_SW */ 58 MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x17059 /* HALL_EN */ 59 >; 60 }; 61 62 pinctrl_hog: hoggrp { 63 fsl,pins = < 64 MX6SL_PAD_LCD_DAT0__GPIO2_IO20 0x79 65 MX6SL_PAD_LCD_DAT1__GPIO2_IO21 0x79 66 MX6SL_PAD_LCD_DAT2__GPIO2_IO22 0x79 67 MX6SL_PAD_LCD_DAT3__GPIO2_IO23 0x79 68 MX6SL_PAD_LCD_DAT4__GPIO2_IO24 0x79 69 MX6SL_PAD_LCD_DAT5__GPIO2_IO25 0x79 70 MX6SL_PAD_LCD_DAT6__GPIO2_IO26 0x79 71 MX6SL_PAD_LCD_DAT7__GPIO2_IO27 0x79 72 MX6SL_PAD_LCD_DAT8__GPIO2_IO28 0x79 73 MX6SL_PAD_LCD_DAT9__GPIO2_IO29 0x79 74 MX6SL_PAD_LCD_DAT10__GPIO2_IO30 0x79 75 MX6SL_PAD_LCD_DAT11__GPIO2_IO31 0x79 76 MX6SL_PAD_LCD_DAT12__GPIO3_IO00 0x79 77 MX6SL_PAD_LCD_DAT13__GPIO3_IO01 0x79 78 MX6SL_PAD_LCD_DAT14__GPIO3_IO02 0x79 79 MX6SL_PAD_LCD_DAT15__GPIO3_IO03 0x79 80 MX6SL_PAD_LCD_DAT16__GPIO3_IO04 0x79 81 MX6SL_PAD_LCD_DAT17__GPIO3_IO05 0x79 82 MX6SL_PAD_LCD_DAT18__GPIO3_IO06 0x79 83 MX6SL_PAD_LCD_DAT19__GPIO3_IO07 0x79 84 MX6SL_PAD_LCD_DAT20__GPIO3_IO08 0x79 85 MX6SL_PAD_LCD_DAT21__GPIO3_IO09 0x79 86 MX6SL_PAD_LCD_DAT22__GPIO3_IO10 0x79 87 MX6SL_PAD_LCD_DAT23__GPIO3_IO11 0x79 88 MX6SL_PAD_LCD_CLK__GPIO2_IO15 0x79 89 MX6SL_PAD_LCD_ENABLE__GPIO2_IO16 0x79 90 MX6SL_PAD_LCD_HSYNC__GPIO2_IO17 0x79 91 MX6SL_PAD_LCD_VSYNC__GPIO2_IO18 0x79 92 MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x79 93 MX6SL_PAD_KEY_COL3__GPIO3_IO30 0x79 94 MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x79 95 MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79 96 MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x79 97 >; 98 }; 99 100 pinctrl_i2c1: i2c1grp { 101 fsl,pins = < 102 MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1 103 MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1 104 >; 105 }; 106 107 pinctrl_i2c1_sleep: i2c1grp-sleep { 108 fsl,pins = < 109 MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 110 MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 111 >; 112 }; 113 114 pinctrl_i2c2: i2c2grp { 115 fsl,pins = < 116 MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1 117 MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1 118 >; 119 }; 120 121 pinctrl_i2c2_sleep: i2c2grp-sleep { 122 fsl,pins = < 123 MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 124 MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 125 >; 126 }; 127 128 pinctrl_i2c3: i2c3grp { 129 fsl,pins = < 130 MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1 131 MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1 132 >; 133 }; 134 135 pinctrl_led: ledgrp { 136 fsl,pins = < 137 MX6SL_PAD_SD1_DAT6__GPIO5_IO07 0x17059 138 >; 139 }; 140 141 pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp { 142 fsl,pins = < 143 MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x10059 /* HWEN */ 144 >; 145 }; 146 147 pinctrl_ricoh_gpio: ricoh_gpiogrp { 148 fsl,pins = < 149 MX6SL_PAD_SD1_CLK__GPIO5_IO15 0x1b8b1 /* ricoh619 chg */ 150 MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */ 151 MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */ 152 >; 153 }; 154 155 pinctrl_uart1: uart1grp { 156 fsl,pins = < 157 MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 158 MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 159 >; 160 }; 161 162 pinctrl_uart4: uart4grp { 163 fsl,pins = < 164 MX6SL_PAD_KEY_ROW6__UART4_TX_DATA 0x1b0b1 165 MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x1b0b1 166 >; 167 }; 168 169 pinctrl_usbotg1: usbotg1grp { 170 fsl,pins = < 171 MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 172 >; 173 }; 174 175 pinctrl_usdhc2: usdhc2grp { 176 fsl,pins = < 177 MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 178 MX6SL_PAD_SD2_CLK__SD2_CLK 0x13059 179 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 180 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 181 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 182 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 183 >; 184 }; 185 186 pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { 187 fsl,pins = < 188 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 189 MX6SL_PAD_SD2_CLK__SD2_CLK 0x130b9 190 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 191 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 192 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 193 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 194 >; 195 }; 196 197 pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { 198 fsl,pins = < 199 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 200 MX6SL_PAD_SD2_CLK__SD2_CLK 0x130f9 201 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 202 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 203 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 204 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 205 >; 206 }; 207 208 pinctrl_usdhc2_sleep: usdhc2grp-sleep { 209 fsl,pins = < 210 MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x100f9 211 MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x100f9 212 MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x100f9 213 MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x100f9 214 MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x100f9 215 MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x100f9 216 >; 217 }; 218 219 pinctrl_usdhc3: usdhc3grp { 220 fsl,pins = < 221 MX6SL_PAD_SD3_CMD__SD3_CMD 0x11059 222 MX6SL_PAD_SD3_CLK__SD3_CLK 0x11059 223 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x11059 224 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x11059 225 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x11059 226 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x11059 227 >; 228 }; 229 230 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { 231 fsl,pins = < 232 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 233 MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9 234 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 235 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 236 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 237 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 238 >; 239 }; 240 241 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { 242 fsl,pins = < 243 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 244 MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9 245 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 246 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 247 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 248 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 249 >; 250 }; 251 252 pinctrl_usdhc3_sleep: usdhc3grp-sleep { 253 fsl,pins = < 254 MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 255 MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1 256 MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x100c1 257 MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x100c1 258 MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x100c1 259 MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x100c1 260 >; 261 }; 262 263 pinctrl_wifi_power: wifi-powergrp { 264 fsl,pins = < 265 MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */ 266 >; 267 }; 268 269 pinctrl_wifi_reset: wifi-resetgrp { 270 fsl,pins = < 271 MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x10059 /* WIFI_RST */ 272 >; 273 }; 274 }; 275 276 &leds { 277 pinctrl-names = "default"; 278 pinctrl-0 = <&pinctrl_led>; 279 }; 280 281 &lm3630a { 282 pinctrl-names = "default"; 283 pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>; 284 }; 285 286 ®_wifi { 287 pinctrl-names = "default"; 288 pinctrl-0 = <&pinctrl_wifi_power>; 289 }; 290 291 ®_vdd1p1 { 292 vin-supply = <&dcdc2_reg>; 293 }; 294 295 ®_vdd2p5 { 296 vin-supply = <&dcdc2_reg>; 297 }; 298 299 &ricoh619 { 300 pinctrl-names = "default"; 301 pinctrl-0 = <&pinctrl_ricoh_gpio>; 302 }; 303 304 &uart1 { 305 pinctrl-names = "default"; 306 pinctrl-0 = <&pinctrl_uart1>; 307 }; 308 309 &uart4 { 310 pinctrl-names = "default"; 311 pinctrl-0 = <&pinctrl_uart4>; 312 }; 313 314 &usdhc2 { 315 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 316 pinctrl-0 = <&pinctrl_usdhc2>; 317 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 318 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 319 pinctrl-3 = <&pinctrl_usdhc2_sleep>; 320 }; 321 322 &usdhc3 { 323 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 324 pinctrl-0 = <&pinctrl_usdhc3>; 325 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 326 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 327 pinctrl-3 = <&pinctrl_usdhc3_sleep>; 328 }; 329 330 &wifi_pwrseq { 331 pinctrl-names = "default"; 332 pinctrl-0 = <&pinctrl_wifi_reset>; 333 };
Cache object: 99bc4a214f1c0cd65405f486dca0c265
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