Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/imx6sll-kobo-clarahd.dts
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 // SPDX-License-Identifier: (GPL-2.0) 2 /* 3 * Device tree for the Kobo Clara HD ebook reader 4 * 5 * Name on mainboard is: 37NB-E60K00+4A4 6 * Serials start with: E60K02 (a number also seen in 7 * vendor kernel sources) 8 * 9 * This mainboard seems to be equipped with different SoCs. 10 * In the Kobo Clara HD ebook reader it is an i.MX6SLL 11 * 12 * Copyright 2019 Andreas Kemnade 13 * based on works 14 * Copyright 2016 Freescale Semiconductor, Inc. 15 */ 16 17 /dts-v1/; 18 19 #include <dt-bindings/input/input.h> 20 #include <dt-bindings/gpio/gpio.h> 21 #include "imx6sll.dtsi" 22 #include "e60k02.dtsi" 23 24 / { 25 model = "Kobo Clara HD"; 26 compatible = "kobo,clarahd", "fsl,imx6sll"; 27 }; 28 29 &clks { 30 assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>; 31 assigned-clock-rates = <393216000>; 32 }; 33 34 &cpu0 { 35 arm-supply = <&dcdc3_reg>; 36 soc-supply = <&dcdc1_reg>; 37 }; 38 39 &gpio_keys { 40 pinctrl-names = "default"; 41 pinctrl-0 = <&pinctrl_gpio_keys>; 42 }; 43 44 &i2c1 { 45 pinctrl-names = "default","sleep"; 46 pinctrl-0 = <&pinctrl_i2c1>; 47 pinctrl-1 = <&pinctrl_i2c1_sleep>; 48 }; 49 50 &i2c2 { 51 pinctrl-names = "default","sleep"; 52 pinctrl-0 = <&pinctrl_i2c2>; 53 pinctrl-1 = <&pinctrl_i2c2_sleep>; 54 }; 55 56 &i2c3 { 57 pinctrl-names = "default"; 58 pinctrl-0 = <&pinctrl_i2c3>; 59 }; 60 61 &iomuxc { 62 pinctrl-names = "default"; 63 pinctrl-0 = <&pinctrl_hog>; 64 65 pinctrl_gpio_keys: gpio-keysgrp { 66 fsl,pins = < 67 MX6SLL_PAD_SD1_DATA1__GPIO5_IO08 0x17059 /* PWR_SW */ 68 MX6SLL_PAD_SD1_DATA4__GPIO5_IO12 0x17059 /* HALL_EN */ 69 >; 70 }; 71 72 pinctrl_hog: hoggrp { 73 fsl,pins = < 74 MX6SLL_PAD_LCD_DATA00__GPIO2_IO20 0x79 75 MX6SLL_PAD_LCD_DATA01__GPIO2_IO21 0x79 76 MX6SLL_PAD_LCD_DATA02__GPIO2_IO22 0x79 77 MX6SLL_PAD_LCD_DATA03__GPIO2_IO23 0x79 78 MX6SLL_PAD_LCD_DATA04__GPIO2_IO24 0x79 79 MX6SLL_PAD_LCD_DATA05__GPIO2_IO25 0x79 80 MX6SLL_PAD_LCD_DATA06__GPIO2_IO26 0x79 81 MX6SLL_PAD_LCD_DATA07__GPIO2_IO27 0x79 82 MX6SLL_PAD_LCD_DATA08__GPIO2_IO28 0x79 83 MX6SLL_PAD_LCD_DATA09__GPIO2_IO29 0x79 84 MX6SLL_PAD_LCD_DATA10__GPIO2_IO30 0x79 85 MX6SLL_PAD_LCD_DATA11__GPIO2_IO31 0x79 86 MX6SLL_PAD_LCD_DATA12__GPIO3_IO00 0x79 87 MX6SLL_PAD_LCD_DATA13__GPIO3_IO01 0x79 88 MX6SLL_PAD_LCD_DATA14__GPIO3_IO02 0x79 89 MX6SLL_PAD_LCD_DATA15__GPIO3_IO03 0x79 90 MX6SLL_PAD_LCD_DATA16__GPIO3_IO04 0x79 91 MX6SLL_PAD_LCD_DATA17__GPIO3_IO05 0x79 92 MX6SLL_PAD_LCD_DATA18__GPIO3_IO06 0x79 93 MX6SLL_PAD_LCD_DATA19__GPIO3_IO07 0x79 94 MX6SLL_PAD_LCD_DATA20__GPIO3_IO08 0x79 95 MX6SLL_PAD_LCD_DATA21__GPIO3_IO09 0x79 96 MX6SLL_PAD_LCD_DATA22__GPIO3_IO10 0x79 97 MX6SLL_PAD_LCD_DATA23__GPIO3_IO11 0x79 98 MX6SLL_PAD_LCD_CLK__GPIO2_IO15 0x79 99 MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16 0x79 100 MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17 0x79 101 MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18 0x79 102 MX6SLL_PAD_LCD_RESET__GPIO2_IO19 0x79 103 MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x79 104 MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x79 105 MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79 106 MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x79 107 >; 108 }; 109 110 pinctrl_i2c1: i2c1grp { 111 fsl,pins = < 112 MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1 113 MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1 114 >; 115 }; 116 117 pinctrl_i2c1_sleep: i2c1grp-sleep { 118 fsl,pins = < 119 MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 120 MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 121 >; 122 }; 123 124 pinctrl_i2c2: i2c2grp { 125 fsl,pins = < 126 MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1 127 MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1 128 >; 129 }; 130 131 pinctrl_i2c2_sleep: i2c2grp-sleep { 132 fsl,pins = < 133 MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 134 MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 135 >; 136 }; 137 138 pinctrl_i2c3: i2c3grp { 139 fsl,pins = < 140 MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1 141 MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1 142 >; 143 }; 144 145 pinctrl_led: ledgrp { 146 fsl,pins = < 147 MX6SLL_PAD_SD1_DATA6__GPIO5_IO07 0x17059 148 >; 149 }; 150 151 pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp { 152 fsl,pins = < 153 MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 0x10059 /* HWEN */ 154 >; 155 }; 156 157 pinctrl_ricoh_gpio: ricoh-gpiogrp { 158 fsl,pins = < 159 MX6SLL_PAD_SD1_CLK__GPIO5_IO15 0x1b8b1 /* ricoh619 chg */ 160 MX6SLL_PAD_SD1_DATA0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */ 161 MX6SLL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */ 162 >; 163 }; 164 165 pinctrl_uart1: uart1grp { 166 fsl,pins = < 167 MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1 168 MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1 169 >; 170 }; 171 172 pinctrl_uart4: uart4grp { 173 fsl,pins = < 174 MX6SLL_PAD_KEY_ROW6__UART4_DCE_TX 0x1b0b1 175 MX6SLL_PAD_KEY_COL6__UART4_DCE_RX 0x1b0b1 176 >; 177 }; 178 179 pinctrl_usbotg1: usbotg1grp { 180 fsl,pins = < 181 MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059 182 >; 183 }; 184 185 pinctrl_usdhc2: usdhc2grp { 186 fsl,pins = < 187 MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059 188 MX6SLL_PAD_SD2_CLK__SD2_CLK 0x13059 189 MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059 190 MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x17059 191 MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x17059 192 MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x17059 193 >; 194 }; 195 196 pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { 197 fsl,pins = < 198 MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9 199 MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9 200 MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170b9 201 MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170b9 202 MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170b9 203 MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170b9 204 >; 205 }; 206 207 pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { 208 fsl,pins = < 209 MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9 210 MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9 211 MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170f9 212 MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170f9 213 MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170f9 214 MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170f9 215 >; 216 }; 217 218 pinctrl_usdhc2_sleep: usdhc2grp-sleep { 219 fsl,pins = < 220 MX6SLL_PAD_SD2_CMD__GPIO5_IO04 0x100f9 221 MX6SLL_PAD_SD2_CLK__GPIO5_IO05 0x100f9 222 MX6SLL_PAD_SD2_DATA0__GPIO5_IO01 0x100f9 223 MX6SLL_PAD_SD2_DATA1__GPIO4_IO30 0x100f9 224 MX6SLL_PAD_SD2_DATA2__GPIO5_IO03 0x100f9 225 MX6SLL_PAD_SD2_DATA3__GPIO4_IO28 0x100f9 226 >; 227 }; 228 229 pinctrl_usdhc3: usdhc3grp { 230 fsl,pins = < 231 MX6SLL_PAD_SD3_CMD__SD3_CMD 0x11059 232 MX6SLL_PAD_SD3_CLK__SD3_CLK 0x11059 233 MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x11059 234 MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x11059 235 MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x11059 236 MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x11059 237 >; 238 }; 239 240 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { 241 fsl,pins = < 242 MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9 243 MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170b9 244 MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9 245 MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9 246 MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9 247 MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9 248 >; 249 }; 250 251 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { 252 fsl,pins = < 253 MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170f9 254 MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170f9 255 MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170f9 256 MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170f9 257 MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170f9 258 MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170f9 259 >; 260 }; 261 262 pinctrl_usdhc3_sleep: usdhc3grp-sleep { 263 fsl,pins = < 264 MX6SLL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 265 MX6SLL_PAD_SD3_CLK__GPIO5_IO18 0x100c1 266 MX6SLL_PAD_SD3_DATA0__GPIO5_IO19 0x100c1 267 MX6SLL_PAD_SD3_DATA1__GPIO5_IO20 0x100c1 268 MX6SLL_PAD_SD3_DATA2__GPIO5_IO16 0x100c1 269 MX6SLL_PAD_SD3_DATA3__GPIO5_IO17 0x100c1 270 >; 271 }; 272 273 pinctrl_wifi_power: wifi-powergrp { 274 fsl,pins = < 275 MX6SLL_PAD_SD2_DATA6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */ 276 >; 277 }; 278 279 pinctrl_wifi_reset: wifi-resetgrp { 280 fsl,pins = < 281 MX6SLL_PAD_SD2_DATA7__GPIO5_IO00 0x10059 /* WIFI_RST */ 282 >; 283 }; 284 }; 285 286 &leds { 287 pinctrl-names = "default"; 288 pinctrl-0 = <&pinctrl_led>; 289 }; 290 291 &lm3630a { 292 pinctrl-names = "default"; 293 pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>; 294 }; 295 296 ®_wifi { 297 pinctrl-names = "default"; 298 pinctrl-0 = <&pinctrl_wifi_power>; 299 }; 300 301 &ricoh619 { 302 pinctrl-names = "default"; 303 pinctrl-0 = <&pinctrl_ricoh_gpio>; 304 }; 305 306 &uart1 { 307 pinctrl-names = "default"; 308 pinctrl-0 = <&pinctrl_uart1>; 309 }; 310 311 &uart4 { 312 pinctrl-names = "default"; 313 pinctrl-0 = <&pinctrl_uart4>; 314 }; 315 316 &usdhc2 { 317 pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep"; 318 pinctrl-0 = <&pinctrl_usdhc2>; 319 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 320 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 321 pinctrl-3 = <&pinctrl_usdhc2_sleep>; 322 }; 323 324 &usdhc3 { 325 pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep"; 326 pinctrl-0 = <&pinctrl_usdhc3>; 327 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 328 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 329 pinctrl-3 = <&pinctrl_usdhc3_sleep>; 330 }; 331 332 &wifi_pwrseq { 333 pinctrl-names = "default"; 334 pinctrl-0 = <&pinctrl_wifi_reset>; 335 };
Cache object: 1dff827597b33d1a7a0ef58765fdc2c8
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]