Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/imx6sx-sabreauto.dts
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright (C) 2014 Freescale Semiconductor, Inc. 4 5 /dts-v1/; 6 7 #include "imx6sx.dtsi" 8 9 / { 10 model = "Freescale i.MX6 SoloX Sabre Auto Board"; 11 compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx"; 12 13 memory@80000000 { 14 device_type = "memory"; 15 reg = <0x80000000 0x80000000>; 16 }; 17 18 leds { 19 compatible = "gpio-leds"; 20 pinctrl-names = "default"; 21 pinctrl-0 = <&pinctrl_led>; 22 23 user { 24 label = "debug"; 25 gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; 26 linux,default-trigger = "heartbeat"; 27 }; 28 }; 29 30 vcc_sd3: regulator-vcc-sd3 { 31 compatible = "regulator-fixed"; 32 pinctrl-names = "default"; 33 pinctrl-0 = <&pinctrl_vcc_sd3>; 34 regulator-name = "VCC_SD3"; 35 regulator-min-microvolt = <3000000>; 36 regulator-max-microvolt = <3000000>; 37 gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; 38 enable-active-high; 39 }; 40 41 reg_can_wake: regulator-can-wake { 42 compatible = "regulator-fixed"; 43 regulator-name = "can-wake"; 44 regulator-min-microvolt = <3300000>; 45 regulator-max-microvolt = <3300000>; 46 gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>; 47 enable-active-high; 48 }; 49 50 reg_can_en: regulator-can-en { 51 compatible = "regulator-fixed"; 52 regulator-name = "can-en"; 53 regulator-min-microvolt = <3300000>; 54 regulator-max-microvolt = <3300000>; 55 gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>; 56 enable-active-high; 57 vin-supply = <®_can_wake>; 58 }; 59 60 reg_can_stby: regulator-can-stby { 61 compatible = "regulator-fixed"; 62 regulator-name = "can-stby"; 63 regulator-min-microvolt = <3300000>; 64 regulator-max-microvolt = <3300000>; 65 gpio = <&max7310_b 4 GPIO_ACTIVE_HIGH>; 66 enable-active-high; 67 vin-supply = <®_can_en>; 68 }; 69 70 reg_cs42888: cs42888_supply { 71 compatible = "regulator-fixed"; 72 regulator-name = "cs42888_supply"; 73 regulator-min-microvolt = <3300000>; 74 regulator-max-microvolt = <3300000>; 75 regulator-always-on; 76 }; 77 78 sound-cs42888 { 79 compatible = "fsl,imx6-sabreauto-cs42888", 80 "fsl,imx-audio-cs42888"; 81 model = "imx-cs42888"; 82 audio-cpu = <&esai>; 83 audio-asrc = <&asrc>; 84 audio-codec = <&cs42888>; 85 audio-routing = 86 "Line Out Jack", "AOUT1L", 87 "Line Out Jack", "AOUT1R", 88 "Line Out Jack", "AOUT2L", 89 "Line Out Jack", "AOUT2R", 90 "Line Out Jack", "AOUT3L", 91 "Line Out Jack", "AOUT3R", 92 "Line Out Jack", "AOUT4L", 93 "Line Out Jack", "AOUT4R", 94 "AIN1L", "Line In Jack", 95 "AIN1R", "Line In Jack", 96 "AIN2L", "Line In Jack", 97 "AIN2R", "Line In Jack"; 98 }; 99 100 sound-spdif { 101 compatible = "fsl,imx-audio-spdif"; 102 model = "imx-spdif"; 103 spdif-controller = <&spdif>; 104 spdif-in; 105 }; 106 }; 107 108 &anaclk2 { 109 clock-frequency = <24576000>; 110 }; 111 112 &clks { 113 assigned-clocks = <&clks IMX6SX_PLL4_BYPASS_SRC>, 114 <&clks IMX6SX_PLL4_BYPASS>, 115 <&clks IMX6SX_CLK_PLL4_POST_DIV>; 116 assigned-clock-parents = <&clks IMX6SX_CLK_LVDS2_IN>, 117 <&clks IMX6SX_PLL4_BYPASS_SRC>; 118 assigned-clock-rates = <0>, <0>, <24576000>; 119 }; 120 121 &esai { 122 pinctrl-names = "default"; 123 pinctrl-0 = <&pinctrl_esai>; 124 assigned-clocks = <&clks IMX6SX_CLK_ESAI_SEL>, 125 <&clks IMX6SX_CLK_ESAI_EXTAL>; 126 assigned-clock-parents = <&clks IMX6SX_CLK_PLL4_AUDIO_DIV>; 127 assigned-clock-rates = <0>, <24576000>; 128 status = "okay"; 129 }; 130 131 &fec1 { 132 pinctrl-names = "default"; 133 pinctrl-0 = <&pinctrl_enet1>; 134 phy-mode = "rgmii-id"; 135 phy-handle = <ðphy1>; 136 fsl,magic-packet; 137 status = "okay"; 138 139 mdio { 140 #address-cells = <1>; 141 #size-cells = <0>; 142 143 ethphy0: ethernet-phy@0 { 144 compatible = "ethernet-phy-ieee802.3-c22"; 145 reg = <0>; 146 }; 147 148 ethphy1: ethernet-phy@1 { 149 compatible = "ethernet-phy-ieee802.3-c22"; 150 reg = <1>; 151 }; 152 }; 153 }; 154 155 &fec2 { 156 pinctrl-names = "default"; 157 pinctrl-0 = <&pinctrl_enet2>; 158 phy-mode = "rgmii-id"; 159 phy-handle = <ðphy0>; 160 fsl,magic-packet; 161 status = "okay"; 162 }; 163 164 &flexcan1 { 165 pinctrl-names = "default"; 166 pinctrl-0 = <&pinctrl_flexcan1>; 167 xceiver-supply = <®_can_stby>; 168 status = "okay"; 169 }; 170 171 &flexcan2 { 172 pinctrl-names = "default"; 173 pinctrl-0 = <&pinctrl_flexcan2>; 174 xceiver-supply = <®_can_stby>; 175 status = "okay"; 176 }; 177 178 &uart1 { 179 pinctrl-names = "default"; 180 pinctrl-0 = <&pinctrl_uart1>; 181 status = "okay"; 182 }; 183 184 &usdhc3 { 185 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 186 pinctrl-0 = <&pinctrl_usdhc3>; 187 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 188 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 189 bus-width = <8>; 190 cd-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; 191 wp-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; 192 keep-power-in-suspend; 193 wakeup-source; 194 vmmc-supply = <&vcc_sd3>; 195 status = "okay"; 196 }; 197 198 &usdhc4 { 199 pinctrl-names = "default"; 200 pinctrl-0 = <&pinctrl_usdhc4>; 201 bus-width = <8>; 202 cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>; 203 no-1-8-v; 204 keep-power-in-suspend; 205 wakeup-source; 206 status = "okay"; 207 }; 208 209 &iomuxc { 210 pinctrl_egalax_int: egalax-intgrp { 211 fsl,pins = < 212 MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x10b0 213 >; 214 }; 215 216 pinctrl_enet1: enet1grp { 217 fsl,pins = < 218 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 219 MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 220 MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9 221 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 222 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 223 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 224 MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 225 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 226 MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 227 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 228 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 229 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 230 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 231 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 232 >; 233 }; 234 235 pinctrl_enet2: enet2grp { 236 fsl,pins = < 237 MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 238 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 239 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 240 MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 241 MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 242 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 243 MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 244 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 245 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 246 MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 247 MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 248 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 249 >; 250 }; 251 252 pinctrl_esai: esaigrp { 253 fsl,pins = < 254 MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030 255 MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030 256 MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030 257 MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030 258 MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030 259 MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030 260 MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030 261 MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030 262 MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030 263 MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030 264 >; 265 }; 266 267 pinctrl_flexcan1: flexcan1grp { 268 fsl,pins = < 269 MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 270 MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 271 >; 272 }; 273 274 pinctrl_flexcan2: flexcan2grp { 275 fsl,pins = < 276 MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 277 MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 278 >; 279 }; 280 281 pinctrl_i2c2: i2c2grp { 282 fsl,pins = < 283 MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 284 MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 285 >; 286 }; 287 288 pinctrl_i2c3: i2c3grp { 289 fsl,pins = < 290 MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 291 MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 292 >; 293 }; 294 295 pinctrl_led: ledgrp { 296 fsl,pins = < 297 MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x17059 298 >; 299 }; 300 301 pinctrl_spdif: spdifgrp { 302 fsl,pins = < 303 MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0 304 >; 305 }; 306 307 pinctrl_uart1: uart1grp { 308 fsl,pins = < 309 MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 310 MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 311 >; 312 }; 313 314 pinctrl_usdhc3: usdhc3grp { 315 fsl,pins = < 316 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 317 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 318 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 319 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 320 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 321 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 322 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 323 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 324 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 325 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 326 MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */ 327 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */ 328 >; 329 }; 330 331 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { 332 fsl,pins = < 333 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 334 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 335 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 336 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 337 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 338 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 339 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 340 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 341 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 342 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 343 >; 344 }; 345 346 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { 347 fsl,pins = < 348 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 349 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 350 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 351 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 352 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 353 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 354 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 355 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 356 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 357 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 358 >; 359 }; 360 361 pinctrl_usdhc4: usdhc4grp { 362 fsl,pins = < 363 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 364 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 365 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 366 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 367 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 368 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 369 MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */ 370 MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */ 371 >; 372 }; 373 374 pinctrl_vcc_sd3: vccsd3grp { 375 fsl,pins = < 376 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 377 >; 378 }; 379 380 pinctrl_wdog: wdoggrp { 381 fsl,pins = < 382 MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0 383 >; 384 }; 385 }; 386 387 &i2c2 { 388 clock-frequency = <100000>; 389 pinctrl-names = "default"; 390 pinctrl-0 = <&pinctrl_i2c2>; 391 status = "okay"; 392 393 cs42888: cs42888@48 { 394 compatible = "cirrus,cs42888"; 395 reg = <0x48>; 396 clocks = <&anaclk2 0>; 397 clock-names = "mclk"; 398 VA-supply = <®_cs42888>; 399 VD-supply = <®_cs42888>; 400 VLS-supply = <®_cs42888>; 401 VLC-supply = <®_cs42888>; 402 }; 403 404 touchscreen@4 { 405 compatible = "eeti,egalax_ts"; 406 reg = <0x04>; 407 pinctrl-names = "default"; 408 pinctrl-0 = <&pinctrl_egalax_int>; 409 interrupt-parent = <&gpio6>; 410 interrupts = <22 IRQ_TYPE_EDGE_FALLING>; 411 wakeup-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; 412 }; 413 414 pfuze100: pmic@8 { 415 compatible = "fsl,pfuze100"; 416 reg = <0x08>; 417 418 regulators { 419 sw1a_reg: sw1ab { 420 regulator-min-microvolt = <300000>; 421 regulator-max-microvolt = <1875000>; 422 regulator-boot-on; 423 regulator-always-on; 424 regulator-ramp-delay = <6250>; 425 }; 426 427 sw1c_reg: sw1c { 428 regulator-min-microvolt = <300000>; 429 regulator-max-microvolt = <1875000>; 430 regulator-boot-on; 431 regulator-always-on; 432 regulator-ramp-delay = <6250>; 433 }; 434 435 sw2_reg: sw2 { 436 regulator-min-microvolt = <800000>; 437 regulator-max-microvolt = <3300000>; 438 regulator-boot-on; 439 regulator-always-on; 440 }; 441 442 sw3a_reg: sw3a { 443 regulator-min-microvolt = <400000>; 444 regulator-max-microvolt = <1975000>; 445 regulator-boot-on; 446 regulator-always-on; 447 }; 448 449 sw3b_reg: sw3b { 450 regulator-min-microvolt = <400000>; 451 regulator-max-microvolt = <1975000>; 452 regulator-boot-on; 453 regulator-always-on; 454 }; 455 456 sw4_reg: sw4 { 457 regulator-min-microvolt = <800000>; 458 regulator-max-microvolt = <3300000>; 459 regulator-always-on; 460 }; 461 462 swbst_reg: swbst { 463 regulator-min-microvolt = <5000000>; 464 regulator-max-microvolt = <5150000>; 465 }; 466 467 snvs_reg: vsnvs { 468 regulator-min-microvolt = <1000000>; 469 regulator-max-microvolt = <3000000>; 470 regulator-boot-on; 471 regulator-always-on; 472 }; 473 474 vref_reg: vrefddr { 475 regulator-boot-on; 476 regulator-always-on; 477 }; 478 479 vgen1_reg: vgen1 { 480 regulator-min-microvolt = <800000>; 481 regulator-max-microvolt = <1550000>; 482 regulator-always-on; 483 }; 484 485 vgen2_reg: vgen2 { 486 regulator-min-microvolt = <800000>; 487 regulator-max-microvolt = <1550000>; 488 }; 489 490 vgen3_reg: vgen3 { 491 regulator-min-microvolt = <1800000>; 492 regulator-max-microvolt = <3300000>; 493 regulator-always-on; 494 }; 495 496 vgen4_reg: vgen4 { 497 regulator-min-microvolt = <1800000>; 498 regulator-max-microvolt = <3300000>; 499 regulator-always-on; 500 }; 501 502 vgen5_reg: vgen5 { 503 regulator-min-microvolt = <1800000>; 504 regulator-max-microvolt = <3300000>; 505 regulator-always-on; 506 }; 507 508 vgen6_reg: vgen6 { 509 regulator-min-microvolt = <1800000>; 510 regulator-max-microvolt = <3300000>; 511 regulator-always-on; 512 }; 513 }; 514 }; 515 516 max7322: gpio@68 { 517 compatible = "maxim,max7322"; 518 reg = <0x68>; 519 gpio-controller; 520 #gpio-cells = <2>; 521 }; 522 }; 523 524 &i2c3 { 525 clock-frequency = <100000>; 526 pinctrl-names = "default"; 527 pinctrl-0 = <&pinctrl_i2c3>; 528 status = "okay"; 529 530 max7310_a: gpio@30 { 531 compatible = "maxim,max7310"; 532 reg = <0x30>; 533 gpio-controller; 534 #gpio-cells = <2>; 535 }; 536 537 max7310_b: gpio@32 { 538 compatible = "maxim,max7310"; 539 reg = <0x32>; 540 gpio-controller; 541 #gpio-cells = <2>; 542 }; 543 }; 544 545 &spdif { 546 pinctrl-names = "default"; 547 pinctrl-0 = <&pinctrl_spdif>; 548 assigned-clocks = <&clks IMX6SX_CLK_SPDIF_PODF>; 549 assigned-clock-rates = <24576000>; 550 status = "okay"; 551 }; 552 553 &wdog1 { 554 pinctrl-names = "default"; 555 pinctrl-0 = <&pinctrl_wdog>; 556 fsl,ext-reset-output; 557 };
Cache object: 690c80b32c5324b1afc22c06a40e4072
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]