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sys/contrib/device-tree/src/arm/imx6sx.dtsi
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1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright 2014 Freescale Semiconductor, Inc. 4 5 #include <dt-bindings/clock/imx6sx-clock.h> 6 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/input/input.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include "imx6sx-pinfunc.h" 10 11 / { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 /* 15 * The decompressor and also some bootloaders rely on a 16 * pre-existing /chosen node to be available to insert the 17 * command line and merge other ATAGS info. 18 */ 19 chosen {}; 20 21 aliases { 22 can0 = &flexcan1; 23 can1 = &flexcan2; 24 ethernet0 = &fec1; 25 ethernet1 = &fec2; 26 gpio0 = &gpio1; 27 gpio1 = &gpio2; 28 gpio2 = &gpio3; 29 gpio3 = &gpio4; 30 gpio4 = &gpio5; 31 gpio5 = &gpio6; 32 gpio6 = &gpio7; 33 i2c0 = &i2c1; 34 i2c1 = &i2c2; 35 i2c2 = &i2c3; 36 i2c3 = &i2c4; 37 mmc0 = &usdhc1; 38 mmc1 = &usdhc2; 39 mmc2 = &usdhc3; 40 mmc3 = &usdhc4; 41 serial0 = &uart1; 42 serial1 = &uart2; 43 serial2 = &uart3; 44 serial3 = &uart4; 45 serial4 = &uart5; 46 serial5 = &uart6; 47 spi0 = &ecspi1; 48 spi1 = &ecspi2; 49 spi2 = &ecspi3; 50 spi3 = &ecspi4; 51 spi4 = &ecspi5; 52 usb0 = &usbotg1; 53 usb1 = &usbotg2; 54 usb2 = &usbh; 55 usbphy0 = &usbphy1; 56 usbphy1 = &usbphy2; 57 }; 58 59 cpus { 60 #address-cells = <1>; 61 #size-cells = <0>; 62 63 cpu0: cpu@0 { 64 compatible = "arm,cortex-a9"; 65 device_type = "cpu"; 66 reg = <0>; 67 next-level-cache = <&L2>; 68 operating-points = < 69 /* kHz uV */ 70 996000 1250000 71 792000 1175000 72 396000 1075000 73 198000 975000 74 >; 75 fsl,soc-operating-points = < 76 /* ARM kHz SOC uV */ 77 996000 1175000 78 792000 1175000 79 396000 1175000 80 198000 1175000 81 >; 82 clock-latency = <61036>; /* two CLK32 periods */ 83 #cooling-cells = <2>; 84 clocks = <&clks IMX6SX_CLK_ARM>, 85 <&clks IMX6SX_CLK_PLL2_PFD2>, 86 <&clks IMX6SX_CLK_STEP>, 87 <&clks IMX6SX_CLK_PLL1_SW>, 88 <&clks IMX6SX_CLK_PLL1_SYS>; 89 clock-names = "arm", "pll2_pfd2_396m", "step", 90 "pll1_sw", "pll1_sys"; 91 arm-supply = <®_arm>; 92 soc-supply = <®_soc>; 93 nvmem-cells = <&cpu_speed_grade>; 94 nvmem-cell-names = "speed_grade"; 95 }; 96 }; 97 98 ckil: clock-ckil { 99 compatible = "fixed-clock"; 100 #clock-cells = <0>; 101 clock-frequency = <32768>; 102 clock-output-names = "ckil"; 103 }; 104 105 osc: clock-osc { 106 compatible = "fixed-clock"; 107 #clock-cells = <0>; 108 clock-frequency = <24000000>; 109 clock-output-names = "osc"; 110 }; 111 112 ipp_di0: clock-ipp-di0 { 113 compatible = "fixed-clock"; 114 #clock-cells = <0>; 115 clock-frequency = <0>; 116 clock-output-names = "ipp_di0"; 117 }; 118 119 ipp_di1: clock-ipp-di1 { 120 compatible = "fixed-clock"; 121 #clock-cells = <0>; 122 clock-frequency = <0>; 123 clock-output-names = "ipp_di1"; 124 }; 125 126 anaclk1: clock-anaclk1 { 127 compatible = "fixed-clock"; 128 #clock-cells = <0>; 129 clock-frequency = <0>; 130 clock-output-names = "anaclk1"; 131 }; 132 133 anaclk2: clock-anaclk2 { 134 compatible = "fixed-clock"; 135 #clock-cells = <0>; 136 clock-frequency = <0>; 137 clock-output-names = "anaclk2"; 138 }; 139 140 mqs: mqs { 141 compatible = "fsl,imx6sx-mqs"; 142 gpr = <&gpr>; 143 status = "disabled"; 144 }; 145 146 pmu { 147 compatible = "arm,cortex-a9-pmu"; 148 interrupt-parent = <&gpc>; 149 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 150 }; 151 152 usbphynop1: usbphynop1 { 153 compatible = "usb-nop-xceiv"; 154 #phy-cells = <0>; 155 }; 156 157 soc: soc { 158 #address-cells = <1>; 159 #size-cells = <1>; 160 compatible = "simple-bus"; 161 interrupt-parent = <&gpc>; 162 ranges; 163 164 ocram_s: sram@8f8000 { 165 compatible = "mmio-sram"; 166 reg = <0x008f8000 0x4000>; 167 clocks = <&clks IMX6SX_CLK_OCRAM_S>; 168 }; 169 170 ocram: sram@900000 { 171 compatible = "mmio-sram"; 172 reg = <0x00900000 0x20000>; 173 clocks = <&clks IMX6SX_CLK_OCRAM>; 174 }; 175 176 intc: interrupt-controller@a01000 { 177 compatible = "arm,cortex-a9-gic"; 178 #interrupt-cells = <3>; 179 interrupt-controller; 180 reg = <0x00a01000 0x1000>, 181 <0x00a00100 0x100>; 182 interrupt-parent = <&intc>; 183 }; 184 185 L2: cache-controller@a02000 { 186 compatible = "arm,pl310-cache"; 187 reg = <0x00a02000 0x1000>; 188 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 189 cache-unified; 190 cache-level = <2>; 191 arm,tag-latency = <4 2 3>; 192 arm,data-latency = <4 2 3>; 193 }; 194 195 gpu: gpu@1800000 { 196 compatible = "vivante,gc"; 197 reg = <0x01800000 0x4000>; 198 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 199 clocks = <&clks IMX6SX_CLK_GPU>, 200 <&clks IMX6SX_CLK_GPU>, 201 <&clks IMX6SX_CLK_GPU>; 202 clock-names = "bus", "core", "shader"; 203 power-domains = <&pd_pu>; 204 }; 205 206 dma_apbh: dma-apbh@1804000 { 207 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh"; 208 reg = <0x01804000 0x2000>; 209 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 213 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 214 #dma-cells = <1>; 215 dma-channels = <4>; 216 clocks = <&clks IMX6SX_CLK_APBH_DMA>; 217 }; 218 219 gpmi: nand-controller@1806000{ 220 compatible = "fsl,imx6sx-gpmi-nand"; 221 #address-cells = <1>; 222 #size-cells = <1>; 223 reg = <0x01806000 0x2000>, <0x01808000 0x4000>; 224 reg-names = "gpmi-nand", "bch"; 225 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 226 interrupt-names = "bch"; 227 clocks = <&clks IMX6SX_CLK_GPMI_IO>, 228 <&clks IMX6SX_CLK_GPMI_APB>, 229 <&clks IMX6SX_CLK_GPMI_BCH>, 230 <&clks IMX6SX_CLK_GPMI_BCH_APB>, 231 <&clks IMX6SX_CLK_PER1_BCH>; 232 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", 233 "gpmi_bch_apb", "per1_bch"; 234 dmas = <&dma_apbh 0>; 235 dma-names = "rx-tx"; 236 status = "disabled"; 237 }; 238 239 aips1: bus@2000000 { 240 compatible = "fsl,aips-bus", "simple-bus"; 241 #address-cells = <1>; 242 #size-cells = <1>; 243 reg = <0x02000000 0x100000>; 244 ranges; 245 246 spba-bus@2000000 { 247 compatible = "fsl,spba-bus", "simple-bus"; 248 #address-cells = <1>; 249 #size-cells = <1>; 250 reg = <0x02000000 0x40000>; 251 ranges; 252 253 spdif: spdif@2004000 { 254 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif"; 255 reg = <0x02004000 0x4000>; 256 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 257 dmas = <&sdma 14 18 0>, 258 <&sdma 15 18 0>; 259 dma-names = "rx", "tx"; 260 clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>, 261 <&clks IMX6SX_CLK_OSC>, 262 <&clks IMX6SX_CLK_SPDIF>, 263 <&clks 0>, <&clks 0>, <&clks 0>, 264 <&clks IMX6SX_CLK_IPG>, 265 <&clks 0>, <&clks 0>, 266 <&clks IMX6SX_CLK_SPBA>; 267 clock-names = "core", "rxtx0", 268 "rxtx1", "rxtx2", 269 "rxtx3", "rxtx4", 270 "rxtx5", "rxtx6", 271 "rxtx7", "spba"; 272 status = "disabled"; 273 }; 274 275 ecspi1: spi@2008000 { 276 #address-cells = <1>; 277 #size-cells = <0>; 278 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 279 reg = <0x02008000 0x4000>; 280 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&clks IMX6SX_CLK_ECSPI1>, 282 <&clks IMX6SX_CLK_ECSPI1>; 283 clock-names = "ipg", "per"; 284 status = "disabled"; 285 }; 286 287 ecspi2: spi@200c000 { 288 #address-cells = <1>; 289 #size-cells = <0>; 290 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 291 reg = <0x0200c000 0x4000>; 292 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&clks IMX6SX_CLK_ECSPI2>, 294 <&clks IMX6SX_CLK_ECSPI2>; 295 clock-names = "ipg", "per"; 296 status = "disabled"; 297 }; 298 299 ecspi3: spi@2010000 { 300 #address-cells = <1>; 301 #size-cells = <0>; 302 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 303 reg = <0x02010000 0x4000>; 304 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&clks IMX6SX_CLK_ECSPI3>, 306 <&clks IMX6SX_CLK_ECSPI3>; 307 clock-names = "ipg", "per"; 308 status = "disabled"; 309 }; 310 311 ecspi4: spi@2014000 { 312 #address-cells = <1>; 313 #size-cells = <0>; 314 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 315 reg = <0x02014000 0x4000>; 316 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&clks IMX6SX_CLK_ECSPI4>, 318 <&clks IMX6SX_CLK_ECSPI4>; 319 clock-names = "ipg", "per"; 320 status = "disabled"; 321 }; 322 323 uart1: serial@2020000 { 324 compatible = "fsl,imx6sx-uart", 325 "fsl,imx6q-uart", "fsl,imx21-uart"; 326 reg = <0x02020000 0x4000>; 327 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 328 clocks = <&clks IMX6SX_CLK_UART_IPG>, 329 <&clks IMX6SX_CLK_UART_SERIAL>; 330 clock-names = "ipg", "per"; 331 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; 332 dma-names = "rx", "tx"; 333 status = "disabled"; 334 }; 335 336 esai: esai@2024000 { 337 compatible = "fsl,imx6sx-esai", "fsl,imx35-esai"; 338 reg = <0x02024000 0x4000>; 339 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&clks IMX6SX_CLK_ESAI_IPG>, 341 <&clks IMX6SX_CLK_ESAI_MEM>, 342 <&clks IMX6SX_CLK_ESAI_EXTAL>, 343 <&clks IMX6SX_CLK_ESAI_IPG>, 344 <&clks IMX6SX_CLK_SPBA>; 345 clock-names = "core", "mem", "extal", 346 "fsys", "spba"; 347 dmas = <&sdma 23 21 0>, 348 <&sdma 24 21 0>; 349 dma-names = "rx", "tx"; 350 status = "disabled"; 351 }; 352 353 ssi1: ssi@2028000 { 354 #sound-dai-cells = <0>; 355 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; 356 reg = <0x02028000 0x4000>; 357 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&clks IMX6SX_CLK_SSI1_IPG>, 359 <&clks IMX6SX_CLK_SSI1>; 360 clock-names = "ipg", "baud"; 361 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>; 362 dma-names = "rx", "tx"; 363 fsl,fifo-depth = <15>; 364 status = "disabled"; 365 }; 366 367 ssi2: ssi@202c000 { 368 #sound-dai-cells = <0>; 369 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; 370 reg = <0x0202c000 0x4000>; 371 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 372 clocks = <&clks IMX6SX_CLK_SSI2_IPG>, 373 <&clks IMX6SX_CLK_SSI2>; 374 clock-names = "ipg", "baud"; 375 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>; 376 dma-names = "rx", "tx"; 377 fsl,fifo-depth = <15>; 378 status = "disabled"; 379 }; 380 381 ssi3: ssi@2030000 { 382 #sound-dai-cells = <0>; 383 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; 384 reg = <0x02030000 0x4000>; 385 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&clks IMX6SX_CLK_SSI3_IPG>, 387 <&clks IMX6SX_CLK_SSI3>; 388 clock-names = "ipg", "baud"; 389 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>; 390 dma-names = "rx", "tx"; 391 fsl,fifo-depth = <15>; 392 status = "disabled"; 393 }; 394 395 asrc: asrc@2034000 { 396 compatible = "fsl,imx6sx-asrc", "fsl,imx53-asrc"; 397 reg = <0x02034000 0x4000>; 398 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&clks IMX6SX_CLK_ASRC_IPG>, 400 <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>, 401 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 402 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 403 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 404 <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>, 405 <&clks IMX6SX_CLK_SPBA>; 406 clock-names = "mem", "ipg", "asrck_0", 407 "asrck_1", "asrck_2", "asrck_3", "asrck_4", 408 "asrck_5", "asrck_6", "asrck_7", "asrck_8", 409 "asrck_9", "asrck_a", "asrck_b", "asrck_c", 410 "asrck_d", "asrck_e", "asrck_f", "spba"; 411 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, 412 <&sdma 19 23 1>, <&sdma 20 23 1>, 413 <&sdma 21 23 1>, <&sdma 22 23 1>; 414 dma-names = "rxa", "rxb", "rxc", 415 "txa", "txb", "txc"; 416 fsl,asrc-rate = <48000>; 417 fsl,asrc-width = <16>; 418 status = "okay"; 419 }; 420 }; 421 422 pwm1: pwm@2080000 { 423 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 424 reg = <0x02080000 0x4000>; 425 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 426 clocks = <&clks IMX6SX_CLK_PWM1>, 427 <&clks IMX6SX_CLK_PWM1>; 428 clock-names = "ipg", "per"; 429 #pwm-cells = <3>; 430 }; 431 432 pwm2: pwm@2084000 { 433 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 434 reg = <0x02084000 0x4000>; 435 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 436 clocks = <&clks IMX6SX_CLK_PWM2>, 437 <&clks IMX6SX_CLK_PWM2>; 438 clock-names = "ipg", "per"; 439 #pwm-cells = <3>; 440 }; 441 442 pwm3: pwm@2088000 { 443 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 444 reg = <0x02088000 0x4000>; 445 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&clks IMX6SX_CLK_PWM3>, 447 <&clks IMX6SX_CLK_PWM3>; 448 clock-names = "ipg", "per"; 449 #pwm-cells = <3>; 450 }; 451 452 pwm4: pwm@208c000 { 453 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 454 reg = <0x0208c000 0x4000>; 455 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&clks IMX6SX_CLK_PWM4>, 457 <&clks IMX6SX_CLK_PWM4>; 458 clock-names = "ipg", "per"; 459 #pwm-cells = <3>; 460 }; 461 462 flexcan1: can@2090000 { 463 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; 464 reg = <0x02090000 0x4000>; 465 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 466 clocks = <&clks IMX6SX_CLK_CAN1_IPG>, 467 <&clks IMX6SX_CLK_CAN1_SERIAL>; 468 clock-names = "ipg", "per"; 469 fsl,stop-mode = <&gpr 0x10 1>; 470 status = "disabled"; 471 }; 472 473 flexcan2: can@2094000 { 474 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; 475 reg = <0x02094000 0x4000>; 476 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&clks IMX6SX_CLK_CAN2_IPG>, 478 <&clks IMX6SX_CLK_CAN2_SERIAL>; 479 clock-names = "ipg", "per"; 480 fsl,stop-mode = <&gpr 0x10 2>; 481 status = "disabled"; 482 }; 483 484 gpt: timer@2098000 { 485 compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt"; 486 reg = <0x02098000 0x4000>; 487 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 488 clocks = <&clks IMX6SX_CLK_GPT_BUS>, 489 <&clks IMX6SX_CLK_GPT_3M>; 490 clock-names = "ipg", "per"; 491 }; 492 493 gpio1: gpio@209c000 { 494 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 495 reg = <0x0209c000 0x4000>; 496 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 498 gpio-controller; 499 #gpio-cells = <2>; 500 interrupt-controller; 501 #interrupt-cells = <2>; 502 gpio-ranges = <&iomuxc 0 5 26>; 503 }; 504 505 gpio2: gpio@20a0000 { 506 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 507 reg = <0x020a0000 0x4000>; 508 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 510 gpio-controller; 511 #gpio-cells = <2>; 512 interrupt-controller; 513 #interrupt-cells = <2>; 514 gpio-ranges = <&iomuxc 0 31 20>; 515 }; 516 517 gpio3: gpio@20a4000 { 518 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 519 reg = <0x020a4000 0x4000>; 520 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 522 gpio-controller; 523 #gpio-cells = <2>; 524 interrupt-controller; 525 #interrupt-cells = <2>; 526 gpio-ranges = <&iomuxc 0 51 29>; 527 }; 528 529 gpio4: gpio@20a8000 { 530 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 531 reg = <0x020a8000 0x4000>; 532 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 534 gpio-controller; 535 #gpio-cells = <2>; 536 interrupt-controller; 537 #interrupt-cells = <2>; 538 gpio-ranges = <&iomuxc 0 80 32>; 539 }; 540 541 gpio5: gpio@20ac000 { 542 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 543 reg = <0x020ac000 0x4000>; 544 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 546 gpio-controller; 547 #gpio-cells = <2>; 548 interrupt-controller; 549 #interrupt-cells = <2>; 550 gpio-ranges = <&iomuxc 0 112 24>; 551 }; 552 553 gpio6: gpio@20b0000 { 554 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 555 reg = <0x020b0000 0x4000>; 556 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 558 gpio-controller; 559 #gpio-cells = <2>; 560 interrupt-controller; 561 #interrupt-cells = <2>; 562 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>; 563 }; 564 565 gpio7: gpio@20b4000 { 566 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 567 reg = <0x020b4000 0x4000>; 568 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 570 gpio-controller; 571 #gpio-cells = <2>; 572 interrupt-controller; 573 #interrupt-cells = <2>; 574 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>; 575 }; 576 577 kpp: keypad@20b8000 { 578 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp"; 579 reg = <0x020b8000 0x4000>; 580 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&clks IMX6SX_CLK_IPG>; 582 status = "disabled"; 583 }; 584 585 wdog1: watchdog@20bc000 { 586 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; 587 reg = <0x020bc000 0x4000>; 588 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 589 clocks = <&clks IMX6SX_CLK_IPG>; 590 }; 591 592 wdog2: watchdog@20c0000 { 593 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; 594 reg = <0x020c0000 0x4000>; 595 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&clks IMX6SX_CLK_IPG>; 597 status = "disabled"; 598 }; 599 600 clks: clock-controller@20c4000 { 601 compatible = "fsl,imx6sx-ccm"; 602 reg = <0x020c4000 0x4000>; 603 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 605 #clock-cells = <1>; 606 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>; 607 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2"; 608 }; 609 610 anatop: anatop@20c8000 { 611 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop", 612 "syscon", "simple-mfd"; 613 reg = <0x020c8000 0x1000>; 614 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 617 618 reg_vdd1p1: regulator-1p1 { 619 compatible = "fsl,anatop-regulator"; 620 regulator-name = "vdd1p1"; 621 regulator-min-microvolt = <1000000>; 622 regulator-max-microvolt = <1200000>; 623 regulator-always-on; 624 anatop-reg-offset = <0x110>; 625 anatop-vol-bit-shift = <8>; 626 anatop-vol-bit-width = <5>; 627 anatop-min-bit-val = <4>; 628 anatop-min-voltage = <800000>; 629 anatop-max-voltage = <1375000>; 630 anatop-enable-bit = <0>; 631 }; 632 633 reg_vdd3p0: regulator-3p0 { 634 compatible = "fsl,anatop-regulator"; 635 regulator-name = "vdd3p0"; 636 regulator-min-microvolt = <2800000>; 637 regulator-max-microvolt = <3150000>; 638 regulator-always-on; 639 anatop-reg-offset = <0x120>; 640 anatop-vol-bit-shift = <8>; 641 anatop-vol-bit-width = <5>; 642 anatop-min-bit-val = <0>; 643 anatop-min-voltage = <2625000>; 644 anatop-max-voltage = <3400000>; 645 anatop-enable-bit = <0>; 646 }; 647 648 reg_vdd2p5: regulator-2p5 { 649 compatible = "fsl,anatop-regulator"; 650 regulator-name = "vdd2p5"; 651 regulator-min-microvolt = <2250000>; 652 regulator-max-microvolt = <2750000>; 653 regulator-always-on; 654 anatop-reg-offset = <0x130>; 655 anatop-vol-bit-shift = <8>; 656 anatop-vol-bit-width = <5>; 657 anatop-min-bit-val = <0>; 658 anatop-min-voltage = <2100000>; 659 anatop-max-voltage = <2875000>; 660 anatop-enable-bit = <0>; 661 }; 662 663 reg_arm: regulator-vddcore { 664 compatible = "fsl,anatop-regulator"; 665 regulator-name = "vddarm"; 666 regulator-min-microvolt = <725000>; 667 regulator-max-microvolt = <1450000>; 668 regulator-always-on; 669 anatop-reg-offset = <0x140>; 670 anatop-vol-bit-shift = <0>; 671 anatop-vol-bit-width = <5>; 672 anatop-delay-reg-offset = <0x170>; 673 anatop-delay-bit-shift = <24>; 674 anatop-delay-bit-width = <2>; 675 anatop-min-bit-val = <1>; 676 anatop-min-voltage = <725000>; 677 anatop-max-voltage = <1450000>; 678 }; 679 680 reg_pcie: regulator-vddpcie { 681 compatible = "fsl,anatop-regulator"; 682 regulator-name = "vddpcie"; 683 regulator-min-microvolt = <725000>; 684 regulator-max-microvolt = <1450000>; 685 anatop-reg-offset = <0x140>; 686 anatop-vol-bit-shift = <9>; 687 anatop-vol-bit-width = <5>; 688 anatop-delay-reg-offset = <0x170>; 689 anatop-delay-bit-shift = <26>; 690 anatop-delay-bit-width = <2>; 691 anatop-min-bit-val = <1>; 692 anatop-min-voltage = <725000>; 693 anatop-max-voltage = <1450000>; 694 }; 695 696 reg_soc: regulator-vddsoc { 697 compatible = "fsl,anatop-regulator"; 698 regulator-name = "vddsoc"; 699 regulator-min-microvolt = <725000>; 700 regulator-max-microvolt = <1450000>; 701 regulator-always-on; 702 anatop-reg-offset = <0x140>; 703 anatop-vol-bit-shift = <18>; 704 anatop-vol-bit-width = <5>; 705 anatop-delay-reg-offset = <0x170>; 706 anatop-delay-bit-shift = <28>; 707 anatop-delay-bit-width = <2>; 708 anatop-min-bit-val = <1>; 709 anatop-min-voltage = <725000>; 710 anatop-max-voltage = <1450000>; 711 }; 712 713 tempmon: tempmon { 714 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; 715 interrupt-parent = <&gpc>; 716 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 717 fsl,tempmon = <&anatop>; 718 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; 719 nvmem-cell-names = "calib", "temp_grade"; 720 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; 721 }; 722 }; 723 724 usbphy1: usbphy@20c9000 { 725 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; 726 reg = <0x020c9000 0x1000>; 727 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 728 clocks = <&clks IMX6SX_CLK_USBPHY1>; 729 fsl,anatop = <&anatop>; 730 }; 731 732 usbphy2: usbphy@20ca000 { 733 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; 734 reg = <0x020ca000 0x1000>; 735 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 736 clocks = <&clks IMX6SX_CLK_USBPHY2>; 737 fsl,anatop = <&anatop>; 738 }; 739 740 snvs: snvs@20cc000 { 741 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 742 reg = <0x020cc000 0x4000>; 743 744 snvs_rtc: snvs-rtc-lp { 745 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 746 regmap = <&snvs>; 747 offset = <0x34>; 748 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 749 }; 750 751 snvs_poweroff: snvs-poweroff { 752 compatible = "syscon-poweroff"; 753 regmap = <&snvs>; 754 offset = <0x38>; 755 value = <0x60>; 756 mask = <0x60>; 757 status = "disabled"; 758 }; 759 760 snvs_pwrkey: snvs-powerkey { 761 compatible = "fsl,sec-v4.0-pwrkey"; 762 regmap = <&snvs>; 763 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 764 linux,keycode = <KEY_POWER>; 765 wakeup-source; 766 status = "disabled"; 767 }; 768 }; 769 770 epit1: epit@20d0000 { 771 reg = <0x020d0000 0x4000>; 772 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 773 }; 774 775 epit2: epit@20d4000 { 776 reg = <0x020d4000 0x4000>; 777 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 778 }; 779 780 src: reset-controller@20d8000 { 781 compatible = "fsl,imx6sx-src", "fsl,imx51-src"; 782 reg = <0x020d8000 0x4000>; 783 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 785 #reset-cells = <1>; 786 }; 787 788 gpc: gpc@20dc000 { 789 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc"; 790 reg = <0x020dc000 0x4000>; 791 interrupt-controller; 792 #interrupt-cells = <3>; 793 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 794 interrupt-parent = <&intc>; 795 clocks = <&clks IMX6SX_CLK_IPG>; 796 clock-names = "ipg"; 797 798 pgc { 799 #address-cells = <1>; 800 #size-cells = <0>; 801 802 power-domain@0 { 803 reg = <0>; 804 #power-domain-cells = <0>; 805 }; 806 807 pd_pu: power-domain@1 { 808 reg = <1>; 809 #power-domain-cells = <0>; 810 power-supply = <®_soc>; 811 clocks = <&clks IMX6SX_CLK_GPU>; 812 }; 813 814 pd_disp: power-domain@2 { 815 reg = <2>; 816 #power-domain-cells = <0>; 817 clocks = <&clks IMX6SX_CLK_PXP_AXI>, 818 <&clks IMX6SX_CLK_DISPLAY_AXI>, 819 <&clks IMX6SX_CLK_LCDIF1_PIX>, 820 <&clks IMX6SX_CLK_LCDIF_APB>, 821 <&clks IMX6SX_CLK_LCDIF2_PIX>, 822 <&clks IMX6SX_CLK_CSI>, 823 <&clks IMX6SX_CLK_VADC>; 824 }; 825 826 pd_pci: power-domain@3 { 827 reg = <3>; 828 #power-domain-cells = <0>; 829 power-supply = <®_pcie>; 830 }; 831 }; 832 }; 833 834 iomuxc: pinctrl@20e0000 { 835 compatible = "fsl,imx6sx-iomuxc"; 836 reg = <0x020e0000 0x4000>; 837 }; 838 839 gpr: iomuxc-gpr@20e4000 { 840 compatible = "fsl,imx6sx-iomuxc-gpr", 841 "fsl,imx6q-iomuxc-gpr", "syscon"; 842 reg = <0x020e4000 0x4000>; 843 }; 844 845 sdma: sdma@20ec000 { 846 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma"; 847 reg = <0x020ec000 0x4000>; 848 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 849 clocks = <&clks IMX6SX_CLK_IPG>, 850 <&clks IMX6SX_CLK_SDMA>; 851 clock-names = "ipg", "ahb"; 852 #dma-cells = <3>; 853 /* imx6sx reuses imx6q sdma firmware */ 854 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 855 }; 856 }; 857 858 aips2: bus@2100000 { 859 compatible = "fsl,aips-bus", "simple-bus"; 860 #address-cells = <1>; 861 #size-cells = <1>; 862 reg = <0x02100000 0x100000>; 863 ranges; 864 865 crypto: crypto@2100000 { 866 compatible = "fsl,sec-v4.0"; 867 #address-cells = <1>; 868 #size-cells = <1>; 869 reg = <0x2100000 0x10000>; 870 ranges = <0 0x2100000 0x10000>; 871 interrupt-parent = <&intc>; 872 clocks = <&clks IMX6SX_CLK_CAAM_MEM>, 873 <&clks IMX6SX_CLK_CAAM_ACLK>, 874 <&clks IMX6SX_CLK_CAAM_IPG>, 875 <&clks IMX6SX_CLK_EIM_SLOW>; 876 clock-names = "mem", "aclk", "ipg", "emi_slow"; 877 878 sec_jr0: jr@1000 { 879 compatible = "fsl,sec-v4.0-job-ring"; 880 reg = <0x1000 0x1000>; 881 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 882 }; 883 884 sec_jr1: jr@2000 { 885 compatible = "fsl,sec-v4.0-job-ring"; 886 reg = <0x2000 0x1000>; 887 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 888 }; 889 }; 890 891 usbotg1: usb@2184000 { 892 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; 893 reg = <0x02184000 0x200>; 894 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 895 clocks = <&clks IMX6SX_CLK_USBOH3>; 896 fsl,usbphy = <&usbphy1>; 897 fsl,usbmisc = <&usbmisc 0>; 898 fsl,anatop = <&anatop>; 899 ahb-burst-config = <0x0>; 900 tx-burst-size-dword = <0x10>; 901 rx-burst-size-dword = <0x10>; 902 status = "disabled"; 903 }; 904 905 usbotg2: usb@2184200 { 906 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; 907 reg = <0x02184200 0x200>; 908 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 909 clocks = <&clks IMX6SX_CLK_USBOH3>; 910 fsl,usbphy = <&usbphy2>; 911 fsl,usbmisc = <&usbmisc 1>; 912 ahb-burst-config = <0x0>; 913 tx-burst-size-dword = <0x10>; 914 rx-burst-size-dword = <0x10>; 915 status = "disabled"; 916 }; 917 918 usbh: usb@2184400 { 919 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; 920 reg = <0x02184400 0x200>; 921 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 922 clocks = <&clks IMX6SX_CLK_USBOH3>; 923 fsl,usbphy = <&usbphynop1>; 924 fsl,usbmisc = <&usbmisc 2>; 925 phy_type = "hsic"; 926 fsl,anatop = <&anatop>; 927 dr_mode = "host"; 928 ahb-burst-config = <0x0>; 929 tx-burst-size-dword = <0x10>; 930 rx-burst-size-dword = <0x10>; 931 status = "disabled"; 932 }; 933 934 usbmisc: usbmisc@2184800 { 935 #index-cells = <1>; 936 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc"; 937 reg = <0x02184800 0x200>; 938 clocks = <&clks IMX6SX_CLK_USBOH3>; 939 }; 940 941 fec1: ethernet@2188000 { 942 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; 943 reg = <0x02188000 0x4000>; 944 interrupt-names = "int0", "pps"; 945 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 947 clocks = <&clks IMX6SX_CLK_ENET>, 948 <&clks IMX6SX_CLK_ENET_AHB>, 949 <&clks IMX6SX_CLK_ENET_PTP>, 950 <&clks IMX6SX_CLK_ENET_REF>, 951 <&clks IMX6SX_CLK_ENET_PTP>; 952 clock-names = "ipg", "ahb", "ptp", 953 "enet_clk_ref", "enet_out"; 954 fsl,num-tx-queues = <3>; 955 fsl,num-rx-queues = <3>; 956 fsl,stop-mode = <&gpr 0x10 3>; 957 status = "disabled"; 958 }; 959 960 mlb: mlb@218c000 { 961 reg = <0x0218c000 0x4000>; 962 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 965 clocks = <&clks IMX6SX_CLK_MLB>; 966 status = "disabled"; 967 }; 968 969 usdhc1: mmc@2190000 { 970 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 971 reg = <0x02190000 0x4000>; 972 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 973 clocks = <&clks IMX6SX_CLK_USDHC1>, 974 <&clks IMX6SX_CLK_USDHC1>, 975 <&clks IMX6SX_CLK_USDHC1>; 976 clock-names = "ipg", "ahb", "per"; 977 bus-width = <4>; 978 status = "disabled"; 979 }; 980 981 usdhc2: mmc@2194000 { 982 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 983 reg = <0x02194000 0x4000>; 984 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 985 clocks = <&clks IMX6SX_CLK_USDHC2>, 986 <&clks IMX6SX_CLK_USDHC2>, 987 <&clks IMX6SX_CLK_USDHC2>; 988 clock-names = "ipg", "ahb", "per"; 989 bus-width = <4>; 990 status = "disabled"; 991 }; 992 993 usdhc3: mmc@2198000 { 994 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 995 reg = <0x02198000 0x4000>; 996 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 997 clocks = <&clks IMX6SX_CLK_USDHC3>, 998 <&clks IMX6SX_CLK_USDHC3>, 999 <&clks IMX6SX_CLK_USDHC3>; 1000 clock-names = "ipg", "ahb", "per"; 1001 bus-width = <4>; 1002 status = "disabled"; 1003 }; 1004 1005 usdhc4: mmc@219c000 { 1006 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 1007 reg = <0x0219c000 0x4000>; 1008 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1009 clocks = <&clks IMX6SX_CLK_USDHC4>, 1010 <&clks IMX6SX_CLK_USDHC4>, 1011 <&clks IMX6SX_CLK_USDHC4>; 1012 clock-names = "ipg", "ahb", "per"; 1013 bus-width = <4>; 1014 status = "disabled"; 1015 }; 1016 1017 i2c1: i2c@21a0000 { 1018 #address-cells = <1>; 1019 #size-cells = <0>; 1020 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 1021 reg = <0x021a0000 0x4000>; 1022 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1023 clocks = <&clks IMX6SX_CLK_I2C1>; 1024 status = "disabled"; 1025 }; 1026 1027 i2c2: i2c@21a4000 { 1028 #address-cells = <1>; 1029 #size-cells = <0>; 1030 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 1031 reg = <0x021a4000 0x4000>; 1032 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1033 clocks = <&clks IMX6SX_CLK_I2C2>; 1034 status = "disabled"; 1035 }; 1036 1037 i2c3: i2c@21a8000 { 1038 #address-cells = <1>; 1039 #size-cells = <0>; 1040 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 1041 reg = <0x021a8000 0x4000>; 1042 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1043 clocks = <&clks IMX6SX_CLK_I2C3>; 1044 status = "disabled"; 1045 }; 1046 1047 memory-controller@21b0000 { 1048 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; 1049 reg = <0x021b0000 0x4000>; 1050 clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>; 1051 }; 1052 1053 fec2: ethernet@21b4000 { 1054 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; 1055 reg = <0x021b4000 0x4000>; 1056 interrupt-names = "int0", "pps"; 1057 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1058 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1059 clocks = <&clks IMX6SX_CLK_ENET>, 1060 <&clks IMX6SX_CLK_ENET_AHB>, 1061 <&clks IMX6SX_CLK_ENET_PTP>, 1062 <&clks IMX6SX_CLK_ENET2_REF_125M>, 1063 <&clks IMX6SX_CLK_ENET_PTP>; 1064 clock-names = "ipg", "ahb", "ptp", 1065 "enet_clk_ref", "enet_out"; 1066 fsl,stop-mode = <&gpr 0x10 4>; 1067 status = "disabled"; 1068 }; 1069 1070 weim: weim@21b8000 { 1071 #address-cells = <2>; 1072 #size-cells = <1>; 1073 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim"; 1074 reg = <0x021b8000 0x4000>; 1075 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1076 clocks = <&clks IMX6SX_CLK_EIM_SLOW>; 1077 fsl,weim-cs-gpr = <&gpr>; 1078 status = "disabled"; 1079 }; 1080 1081 ocotp: efuse@21bc000 { 1082 #address-cells = <1>; 1083 #size-cells = <1>; 1084 compatible = "fsl,imx6sx-ocotp", "syscon"; 1085 reg = <0x021bc000 0x4000>; 1086 clocks = <&clks IMX6SX_CLK_OCOTP>; 1087 1088 cpu_speed_grade: speed-grade@10 { 1089 reg = <0x10 4>; 1090 }; 1091 1092 tempmon_calib: calib@38 { 1093 reg = <0x38 4>; 1094 }; 1095 1096 tempmon_temp_grade: temp-grade@20 { 1097 reg = <0x20 4>; 1098 }; 1099 }; 1100 1101 sai1: sai@21d4000 { 1102 compatible = "fsl,imx6sx-sai"; 1103 reg = <0x021d4000 0x4000>; 1104 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1105 clocks = <&clks IMX6SX_CLK_SAI1_IPG>, 1106 <&clks IMX6SX_CLK_SAI1>, 1107 <&clks 0>, <&clks 0>; 1108 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1109 dma-names = "rx", "tx"; 1110 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>; 1111 status = "disabled"; 1112 }; 1113 1114 audmux: audmux@21d8000 { 1115 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux"; 1116 reg = <0x021d8000 0x4000>; 1117 status = "disabled"; 1118 }; 1119 1120 sai2: sai@21dc000 { 1121 compatible = "fsl,imx6sx-sai"; 1122 reg = <0x021dc000 0x4000>; 1123 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1124 clocks = <&clks IMX6SX_CLK_SAI2_IPG>, 1125 <&clks IMX6SX_CLK_SAI2>, 1126 <&clks 0>, <&clks 0>; 1127 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1128 dma-names = "rx", "tx"; 1129 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>; 1130 status = "disabled"; 1131 }; 1132 1133 qspi1: spi@21e0000 { 1134 #address-cells = <1>; 1135 #size-cells = <0>; 1136 compatible = "fsl,imx6sx-qspi"; 1137 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; 1138 reg-names = "QuadSPI", "QuadSPI-memory"; 1139 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1140 clocks = <&clks IMX6SX_CLK_QSPI1>, 1141 <&clks IMX6SX_CLK_QSPI1>; 1142 clock-names = "qspi_en", "qspi"; 1143 status = "disabled"; 1144 }; 1145 1146 qspi2: spi@21e4000 { 1147 #address-cells = <1>; 1148 #size-cells = <0>; 1149 compatible = "fsl,imx6sx-qspi"; 1150 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>; 1151 reg-names = "QuadSPI", "QuadSPI-memory"; 1152 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 1153 clocks = <&clks IMX6SX_CLK_QSPI2>, 1154 <&clks IMX6SX_CLK_QSPI2>; 1155 clock-names = "qspi_en", "qspi"; 1156 status = "disabled"; 1157 }; 1158 1159 uart2: serial@21e8000 { 1160 compatible = "fsl,imx6sx-uart", 1161 "fsl,imx6q-uart", "fsl,imx21-uart"; 1162 reg = <0x021e8000 0x4000>; 1163 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1164 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1165 <&clks IMX6SX_CLK_UART_SERIAL>; 1166 clock-names = "ipg", "per"; 1167 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; 1168 dma-names = "rx", "tx"; 1169 status = "disabled"; 1170 }; 1171 1172 uart3: serial@21ec000 { 1173 compatible = "fsl,imx6sx-uart", 1174 "fsl,imx6q-uart", "fsl,imx21-uart"; 1175 reg = <0x021ec000 0x4000>; 1176 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1177 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1178 <&clks IMX6SX_CLK_UART_SERIAL>; 1179 clock-names = "ipg", "per"; 1180 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; 1181 dma-names = "rx", "tx"; 1182 status = "disabled"; 1183 }; 1184 1185 uart4: serial@21f0000 { 1186 compatible = "fsl,imx6sx-uart", 1187 "fsl,imx6q-uart", "fsl,imx21-uart"; 1188 reg = <0x021f0000 0x4000>; 1189 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1190 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1191 <&clks IMX6SX_CLK_UART_SERIAL>; 1192 clock-names = "ipg", "per"; 1193 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; 1194 dma-names = "rx", "tx"; 1195 status = "disabled"; 1196 }; 1197 1198 uart5: serial@21f4000 { 1199 compatible = "fsl,imx6sx-uart", 1200 "fsl,imx6q-uart", "fsl,imx21-uart"; 1201 reg = <0x021f4000 0x4000>; 1202 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1203 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1204 <&clks IMX6SX_CLK_UART_SERIAL>; 1205 clock-names = "ipg", "per"; 1206 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; 1207 dma-names = "rx", "tx"; 1208 status = "disabled"; 1209 }; 1210 1211 i2c4: i2c@21f8000 { 1212 #address-cells = <1>; 1213 #size-cells = <0>; 1214 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 1215 reg = <0x021f8000 0x4000>; 1216 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1217 clocks = <&clks IMX6SX_CLK_I2C4>; 1218 status = "disabled"; 1219 }; 1220 }; 1221 1222 aips3: bus@2200000 { 1223 compatible = "fsl,aips-bus", "simple-bus"; 1224 #address-cells = <1>; 1225 #size-cells = <1>; 1226 reg = <0x02200000 0x100000>; 1227 ranges; 1228 1229 spba-bus@2240000 { 1230 compatible = "fsl,spba-bus", "simple-bus"; 1231 #address-cells = <1>; 1232 #size-cells = <1>; 1233 reg = <0x02240000 0x40000>; 1234 ranges; 1235 1236 csi1: csi@2214000 { 1237 reg = <0x02214000 0x4000>; 1238 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1239 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, 1240 <&clks IMX6SX_CLK_CSI>, 1241 <&clks IMX6SX_CLK_DCIC1>; 1242 clock-names = "disp-axi", "csi_mclk", "dcic"; 1243 status = "disabled"; 1244 }; 1245 1246 pxp: pxp@2218000 { 1247 compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp"; 1248 reg = <0x02218000 0x4000>; 1249 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1250 clocks = <&clks IMX6SX_CLK_PXP_AXI>; 1251 clock-names = "axi"; 1252 power-domains = <&pd_disp>; 1253 status = "disabled"; 1254 }; 1255 1256 csi2: csi@221c000 { 1257 reg = <0x0221c000 0x4000>; 1258 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1259 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, 1260 <&clks IMX6SX_CLK_CSI>, 1261 <&clks IMX6SX_CLK_DCIC2>; 1262 clock-names = "disp-axi", "csi_mclk", "dcic"; 1263 status = "disabled"; 1264 }; 1265 1266 lcdif1: lcdif@2220000 { 1267 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; 1268 reg = <0x02220000 0x4000>; 1269 interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>; 1270 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, 1271 <&clks IMX6SX_CLK_LCDIF_APB>, 1272 <&clks IMX6SX_CLK_DISPLAY_AXI>; 1273 clock-names = "pix", "axi", "disp_axi"; 1274 power-domains = <&pd_disp>; 1275 status = "disabled"; 1276 }; 1277 1278 lcdif2: lcdif@2224000 { 1279 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; 1280 reg = <0x02224000 0x4000>; 1281 interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>; 1282 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>, 1283 <&clks IMX6SX_CLK_LCDIF_APB>, 1284 <&clks IMX6SX_CLK_DISPLAY_AXI>; 1285 clock-names = "pix", "axi", "disp_axi"; 1286 power-domains = <&pd_disp>; 1287 status = "disabled"; 1288 }; 1289 1290 vadc: vadc@2228000 { 1291 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>; 1292 reg-names = "vadc-vafe", "vadc-vdec"; 1293 clocks = <&clks IMX6SX_CLK_VADC>, 1294 <&clks IMX6SX_CLK_CSI>; 1295 clock-names = "vadc", "csi"; 1296 power-domains = <&pd_disp>; 1297 status = "disabled"; 1298 }; 1299 }; 1300 1301 adc1: adc@2280000 { 1302 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; 1303 reg = <0x02280000 0x4000>; 1304 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1305 clocks = <&clks IMX6SX_CLK_IPG>; 1306 clock-names = "adc"; 1307 fsl,adck-max-frequency = <30000000>, <40000000>, 1308 <20000000>; 1309 status = "disabled"; 1310 }; 1311 1312 adc2: adc@2284000 { 1313 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; 1314 reg = <0x02284000 0x4000>; 1315 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1316 clocks = <&clks IMX6SX_CLK_IPG>; 1317 clock-names = "adc"; 1318 fsl,adck-max-frequency = <30000000>, <40000000>, 1319 <20000000>; 1320 status = "disabled"; 1321 }; 1322 1323 wdog3: watchdog@2288000 { 1324 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; 1325 reg = <0x02288000 0x4000>; 1326 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1327 clocks = <&clks IMX6SX_CLK_IPG>; 1328 status = "disabled"; 1329 }; 1330 1331 ecspi5: spi@228c000 { 1332 #address-cells = <1>; 1333 #size-cells = <0>; 1334 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 1335 reg = <0x0228c000 0x4000>; 1336 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1337 clocks = <&clks IMX6SX_CLK_ECSPI5>, 1338 <&clks IMX6SX_CLK_ECSPI5>; 1339 clock-names = "ipg", "per"; 1340 status = "disabled"; 1341 }; 1342 1343 uart6: serial@22a0000 { 1344 compatible = "fsl,imx6sx-uart", 1345 "fsl,imx6q-uart", "fsl,imx21-uart"; 1346 reg = <0x022a0000 0x4000>; 1347 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1348 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1349 <&clks IMX6SX_CLK_UART_SERIAL>; 1350 clock-names = "ipg", "per"; 1351 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>; 1352 dma-names = "rx", "tx"; 1353 status = "disabled"; 1354 }; 1355 1356 pwm5: pwm@22a4000 { 1357 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 1358 reg = <0x022a4000 0x4000>; 1359 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1360 clocks = <&clks IMX6SX_CLK_PWM5>, 1361 <&clks IMX6SX_CLK_PWM5>; 1362 clock-names = "ipg", "per"; 1363 #pwm-cells = <3>; 1364 }; 1365 1366 pwm6: pwm@22a8000 { 1367 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 1368 reg = <0x022a8000 0x4000>; 1369 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1370 clocks = <&clks IMX6SX_CLK_PWM6>, 1371 <&clks IMX6SX_CLK_PWM6>; 1372 clock-names = "ipg", "per"; 1373 #pwm-cells = <3>; 1374 }; 1375 1376 pwm7: pwm@22ac000 { 1377 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 1378 reg = <0x022ac000 0x4000>; 1379 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1380 clocks = <&clks IMX6SX_CLK_PWM7>, 1381 <&clks IMX6SX_CLK_PWM7>; 1382 clock-names = "ipg", "per"; 1383 #pwm-cells = <3>; 1384 }; 1385 1386 pwm8: pwm@22b0000 { 1387 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 1388 reg = <0x0022b0000 0x4000>; 1389 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1390 clocks = <&clks IMX6SX_CLK_PWM8>, 1391 <&clks IMX6SX_CLK_PWM8>; 1392 clock-names = "ipg", "per"; 1393 #pwm-cells = <3>; 1394 }; 1395 }; 1396 1397 pcie: pcie@8ffc000 { 1398 compatible = "fsl,imx6sx-pcie"; 1399 reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>; 1400 reg-names = "dbi", "config"; 1401 #address-cells = <3>; 1402 #size-cells = <2>; 1403 device_type = "pci"; 1404 bus-range = <0x00 0xff>; 1405 ranges = <0x81000000 0 0 0x08f80000 0 0x00010000>, /* downstream I/O */ 1406 <0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */ 1407 num-lanes = <1>; 1408 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1409 interrupt-names = "msi"; 1410 #interrupt-cells = <1>; 1411 interrupt-map-mask = <0 0 0 0x7>; 1412 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1413 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1414 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1415 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1416 clocks = <&clks IMX6SX_CLK_PCIE_AXI>, 1417 <&clks IMX6SX_CLK_LVDS1_OUT>, 1418 <&clks IMX6SX_CLK_PCIE_REF_125M>, 1419 <&clks IMX6SX_CLK_DISPLAY_AXI>; 1420 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; 1421 power-domains = <&pd_disp>, <&pd_pci>; 1422 power-domain-names = "pcie", "pcie_phy"; 1423 status = "disabled"; 1424 }; 1425 }; 1426 };
Cache object: 84076914111cf2d52800f34686c5152e
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